Abstract: An on-chip metal-insulator-metal (MIM) capacitor with enhanced capacitance is provided by forming the MIM capacitor along sidewall surfaces and a bottom surface of each trench of a plurality of trenches formed in a back-end-of-the-line (BEOL) metallization stack to increase a surface area of the MIM capacitor.

Abstract: A pattern is defined in a dielectric layer. The dielectric layer includes a low-k dielectric region and a high-k dielectric region. The high-k dielectric region includes a phase change material which is an alloy of tantalum and nitrogen and is a high-k insulator in a deposited state. The pattern includes a first set of features in the low-k dielectric region and a second set of features in the high-k dielectric region. A surface treatment process is performed on the phase change layer to produce a top surface layer having electrically conductive properties. A metal layer is deposited in the first and second set of features. Thus, a set of conductive lines is formed in the low-k dielectric region and a metal insulator metal capacitor in the high-k dielectric region.

Abstract: An apparatus according to one embodiment includes a sensor having an active region, a magnetic shield adjacent the active region, and a spacer between the active region and the magnetic shield. The spacer includes an electrically conductive ceramic layer. An apparatus according to another embodiment includes a sensor having an active tunnel magnetoresistive region, a magnetic shield adjacent the tunnel magnetoresistive region, and a spacer between the tunnel magnetoresistive region and the magnetic shields. The spacer includes an electrically conductive ceramic layer.

Abstract: According to an exemplary embodiment, a semiconductor device is provided. The semiconductor device includes a first seal ring and a first circuit. The first circuit includes a first capacitor and a first inductor connected in series. The first circuit is connected between the first seal ring and a ground.

Abstract: Disclosed is a solder particle including a plastic core; a copper-free metal layer which is formed on an external surface of the plastic core; and a solder layer which is formed on the copper-free metal layer and contains not less than 85 wt % tin. Thus, it is possible to provide a solder particle with a copper-free metal layer, which is excellent in strength and conductivity and prevents or minimizes generation of a void during a reflow process or the like.

Abstract: Some embodiments include an integrated memory having an array of capacitors. The array has edges. The capacitors along the edges are edge capacitors, and the other capacitors are internal capacitors. The edge capacitors have inner edges facing toward the internal capacitors, and have outer edges in opposing relation to the inner edges. An insulative beam extends laterally between the capacitors. The insulative beam is along upper regions of the capacitors. First void regions are under the insulative beam, along lower regions of the internal capacitors, and along the inner edges of the edge capacitors. Peripheral extensions of the insulative beam extend laterally outward of the edge capacitors, and second void regions are under the peripheral extensions and along the outer edges of the edge capacitors. Some embodiments included integrated assemblies having two or more memory array decks stacked on atop another. Some embodiments include methods of forming memory arrays.

Abstract: The present invention provides a low-temperature polysilicon thin film transistor array substrate and a method of fabricating the same, and a display device. The array substrate comprises: a substrate; a polysilicon active layer provided on the substrate; a first insulation layer provided on the active layer; a plurality of gates and a gate line provided on the first insulation layer; a second insulation layer provided on the gates; a source, a drain, a data line and a pixel electrode electrically connected with the drain, which are provided on the second insulation layer, the source covers the plurality of gates. The plurality of gates are provided directly below the source, so that the leakage current is reduced and the aperture ratio of panel is improved.

Abstract: Disclosed herein is an integrated circuit (IC) including a first metal layer running in a first direction, a second metal layer running in a second direction perpendicular to the first direction, the second metal layer above the first metal layer and a third metal layer running in the first direction above the second metal layer. A viabar electrically connects the first metal layer to the third metal layer, the viabar running in the first direction wherein the viabar vertically extends from the first metal layer to the third metal layer. A method of manufacturing the IC is provided.

Abstract: A method of manufacturing a plurality of through-holes in a layer of first material, for example for the manufacturing of a probe comprising a tip containing a channel. To manufacture the through-holes in a batch process, a layer of first material is deposited on a wafer comprising a plurality of pits a second layer is provided on the layer of first material, and the second layer is provided with a plurality of holes at central locations of the pits; using the second layer as a shadow mask when depositing a third layer at an angle, covering a part of the first material with said third material at the central locations, and etching the exposed parts of the first layer using the third layer as a protective layer.

Abstract: A method is provided for forming a stack of film layers for use in 3D memory devices. The method starts with providing a substrate in a processing chamber of a deposition reactor. Then one or more process gases suitable for forming a dielectric layer are supplied into the processing chamber of the deposition reactor forming a dielectric layer on the substrate. Then one or more process gases suitable for forming a metallic layer are supplied into the processing chamber of the deposition reactor forming a metallic layer on the dielectric layer. Then one or more process gases suitable for forming a metallic nitride adhesion layer are supplied into the processing chamber of the deposition reactor forming a metallic nitride adhesion layer on the metallic layer. The sequence is then repeated to form a desired number of layers.

Abstract: A method for manufacturing a metal-insulator-metal (MIM) capacitor with a top electrode that is free of sidewall damage is provided. A bottom electrode layer is formed with a first material. An inter-electrode dielectric layer is formed over the bottom electrode layer. A top electrode layer is formed over the inter-electrode dielectric layer and without the first material. A first etch is performed into the top electrode layer and the inter-electrode dielectric layer to form a top electrode. A second etch into the bottom electrode layer to form a bottom electrode. The present application is also directed towards a MIM capacitor resulting from performing the method.

Abstract: A method for forming a metal-insulator-metal (MIM) capacitor structure is provided. The method includes providing a substrate and forming an interconnect structure over the substrate. The interconnect structure includes a top metal layer, and wherein the top metal layer includes a first portion and a second portion. The method includes forming an insulating layer on the first portion of the top metal layer; and forming a metal pad on the insulating layer. The metal pad includes a first portion and a second portion, the MIM capacitor is constructed by the first portion of the top metal layer, the insulating layer and the first portion of the metal pad, and the second portion of the metal pad directly contacts the first portion of the metal pad and the second portion of the top metal layer.

Abstract: Semiconductor device assemblies having stacked semiconductor dies and thermal transfer devices that include vapor chambers are disclosed herein. In one embodiment, a semiconductor device assembly includes a first semiconductor die having a base region, at least one second semiconductor die at the base region, and a thermal transfer device attached to the first and second dies. The thermal transfer device includes an encapsulant at least partially surrounding the second die and a via formed in the encapsulant. The encapsulant at least partially defines a cooling channel that is adjacent to a peripheral region of the first die. The via includes a working fluid and/or a solid thermal conductor that at least partially fills the channel.

Abstract: A sensor for an integrated circuit (IC) structure is disclosed. The sensor includes a sensor layer in a layer of the IC structure, the sensor layer including: a first conductive structure disposed proximate a perimeter of the IC structure; and a second conductive structure disposed parallel to the first conductive structure and proximate the perimeter of the IC structure. The sensor also includes a set of interdigitating conductive elements including a first plurality of conductive elements electrically coupled to the first conductive structure interdigitating with a second plurality of conductive elements electrically coupled to the second conductive structure.

Abstract: The present disclosure relates to an integrated circuit configured to mitigate damage to MIM decoupling capacitors. In some embodiments, the integrated chip has a lower metal interconnect layer arranged over a substrate. A plurality of MIM (metal-insulator-metal) structures are arranged over the lower metal interconnect layer, and a plurality of memory cells are arranged over the lower metal interconnect layer at a location laterally offset from the plurality of MIM structures. An upper metal interconnect layer is arranged over the plurality of MIM structures and the plurality of memory cells. One or both of the lower metal interconnect layer and the upper metal interconnect layer are comprised within a conductive path that electrically couples the plurality of MIM structures in a series connection. The plurality of MIM structures and the plurality of memory cells comprise multi-layer structures having a substantially same shape.

Abstract: According to one embodiment, a semiconductor memory device includes a wiring layer, an insulating layer, a contact plug, a pillar and a pad. The wiring layer is electrically connected to a memory cell. The insulating layer is provided on the wiring layer. The contact plug is provided in the insulating layer and is electrically connected to an end of the wiring layer. The pillar is provided through the wiring layer and the insulating layer which are located between the memory cell and the contact plug. The pad is electrically connected to one end of the pillar.

Abstract: An electronic package includes a carrier and a semiconductor chip. In a first aspect a lid is attached to the chip and subsequently the gap between the lid and the carrier is filled by a seal band that includes seal band material and a plurality of shim members. In another aspect, an interleaved seal band includes a pattern of a first type of seal band material and a second type of seal band material. In another aspect, the lid includes a plurality of surfaces at different topographies to reduce the thickness of the seal band between the topographic lid and the carrier. In yet another aspect the electronic package further includes a frame concentric with the chip. The lid is attached to the frame with a solder, epoxy or elastomer and placed on the chip with a thermal interface material. The seal band material is dispensed on the chip carrier and the frame is then moved towards the chip carrier allowing a minimum seal band thickness.

Abstract: An electronic device includes a semiconductor body and a dielectric layer extending over the semiconductor body. A galvanic isolation module includes a first metal region extending in the dielectric layer at a first height and a second metal region extending in the dielectric layer at a second height greater than the first height. The first and second metal regions are capacitively or magnetically coupleable together. The second metal region includes a side wall and a bottom wall coupled to one another through rounded surface portions.

Abstract: A circular memory device includes a plurality of bottom electrodes, a plurality of top electrodes, a ferroelectric layer, and a plurality of memory storage locations within the ferroelectric layer at a crossover point of each of the bottom electrodes and each top electrode. Contact pads of the bottom electrodes and top electrodes may include a perimeter that defines an annular sector that allows a memory operation to be performed on the circular memory device across a range of rotational positions. In an example implementation, the memory operation may be performed on the circular memory device regardless of the rotational orientation of the circular memory device relative to a reader.

Abstract: One aspect of the disclosure relates to an interposer. The interposer may include: a first dielectric layer extending from a substrate in a direction away from a front side of the substrate; a back-end-of-the-line (BEOL) region extending from the substrate in a direction away from the back side of the substrate; a deep trench (DT) capacitor within the substrate and extending toward a back side of the substrate, the DT capacitor having a first portion within the substrate and a second portion within the first dielectric layer; and a through silicon via (TSV) adjacent to the DT capacitor and extending through the first dielectric layer, the substrate, and the BEOL region.

Abstract: A method of fabricating a display device including forming one or more thin-film transistors (“TFTs”) each configured to include an active layer, a gate insulating layer, a gate electrode, a source electrode, and a drain electrode on a substrate. A storage capacitor including a first storage electrode and a second storage electrode overlapping the first storage electrode with the gate insulating layer interposed there between is also formed on the substrate. A top surface of the first storage electrode may include hillocks and the gate insulating layer is formed between the first storage electrode and the second storage electrode to conform to the shape of the top surface of the first storage electrode with the hillocks.

Abstract: Metal silicates or phosphates are deposited on a heated substrate by the reaction of vapors of alkoxysilanols or alkylphosphates along with reactive metal amides, alkyls or alkoxides. For example, vapors of tris(tert-butoxy)silanol react with vapors of tetrakis(ethylmethylamido) hafnium to deposit hafnium silicate on surfaces heated to 300° C. The product film has a very uniform stoichiometry throughout the reactor. Similarly, vapors of diisopropylphosphate react with vapors of lithium bis(ethyldimethylsilyl)amide to deposit lithium phosphate films on substrates heated to 250° C. Supplying the vapors in alternating pulses produces these same compositions with a very uniform distribution of thickness and excellent step coverage.

Abstract: A method for fabricating an electronic package is provided, which includes the steps of: providing an insulating layer having at least an electronic element embedded therein; forming at least a first via hole on one side of the insulating layer; forming a first conductor in the first via hole of the insulating layer; forming on the insulating layer a first circuit structure electrically connected to the electronic element and the first conductor; and forming a second via hole on the other side of the insulating layer, wherein the second via hole communicates with the first via hole. As such, the second via hole and the first via hole constitute a through hole. Since the through hole is fabricated through two steps, the aspect ratio (depth/width) of the through hole can be adjusted according to the practical need so as to improve the process yield.

Abstract: A semiconductor memory device includes a conducting layer and an insulating layer that are disposed above a semiconductor substrate, a plurality of pillars that extend in a direction which crosses a surface of the semiconductor substrate, and a plate that is disposed between the plurality of pillars and extends in the same direction as the pillars. A surface of the plate, which faces the pillars, has convex portions and non-convex portions.

Abstract: One aspect of the disclosure relates to a method of forming an integrated circuit structure. The method may include: providing a substrate having a front side and a back side, the substrate including: a deep trench (DT) capacitor within the substrate extending toward the back side of substrate, and a through silicon via (TSV) adjacent to the DT capacitor within the substrate extending toward the back side of the substrate, the TSV including a metal substantially surrounded by a liner layer and an insulating layer substantially surrounding the liner layer; etching the back side of the substrate to expose the TSV on the back side of the substrate; and forming a first dielectric layer covering the exposed TSV on the back side of the substrate and extending away from the front side of the substrate.

Abstract: A method of forming a capacitor includes depositing a dielectric metal oxide layer of a first phase to a thickness no greater than 75 Angstroms over an inner conductive capacitor electrode material. The first phase dielectric metal oxide layer has a k of at least 15. Conductive RuO2 is deposited over and into physical contact with the dielectric metal oxide layer. Then, the RuO2 and the dielectric metal oxide layer are annealed at a temperature below 500° C. The RuO2 in physical contact with the dielectric metal oxide during the annealing facilitates a change of the dielectric metal oxide layer from the first phase to a second crystalline phase having a higher k than the first phase. The annealed dielectric metal oxide layer is incorporated into a capacitor dielectric region of a capacitor construction. Other implementations are disclosed.

Abstract: A semiconductor integrated circuit device may include a through silicon via (TSV), a keep out zone and a plurality of dummy patterns. The TSV may be arranged in a selection region of a semiconductor substrate. The keep out zone may be configured to define a peripheral region of the TSV. The dummy patterns may be arranged in the keep out zone to receive a conductive signal. The dummy patterns may function as an electrode of a reservoir capacitor.

Abstract: Oxygen is likely to be released or an oxygen vacancy is likely to occur during a manufacturing process particularly at a side surface of an oxide semiconductor layer. When an oxygen vacancy occurs at the side surface of the oxide semiconductor layer, a problem arises in that the resistance of the side surface is reduced, the apparent threshold voltage of a transistor varies, and variation in the threshold voltage is increased. Further, the variation in the threshold voltage may cause unintentional current to flow between a source and a drain, which might lead to an increase in the off-state current of the transistor and deterioration in the electric characteristics of the transistor. A semiconductor device in which a multilayer film including an oxide semiconductor layer and an oxide layer surrounding the oxide semiconductor layer is used for a channel formation region is provided.

Abstract: A device comprises a destination substrate; a multilayer structure on the destination substrate, wherein the multilayer structure comprises a plurality of printed capacitors stacked on top of each other with an offset between each capacitor along at least one edge of the capacitors; and wherein each printed capacitor includes a plurality of electrically connected capacitors. Each printed capacitor of the plurality of printed capacitors can be a horizontal or a vertical capacitor. Each printed capacitor can include a plurality of capacitor layers, each capacitor layer including a plurality of electrically connected capacitors.

Abstract: Provided herein are semiconductor devices with through electrodes and methods of fabricating the same. The methods may include providing a semiconductor substrate having top and bottom surfaces facing each other, forming on the top surface of the semiconductor substrate a main via having a hollow cylindrical structure and a metal line connected to the main via, forming an interlayered insulating layer on the top surface of the semiconductor substrate to cover the main via and the metal line, removing a portion of the semiconductor substrate to form a via hole exposing a portion of a bottom surface of the main via, and forming in the via hole a through electrode that is electrically connected to the main via. The bottom surface of the main via is overlapped by a circumference of the via hole, when viewed in a plan view.

Abstract: A semiconductor package includes a die pad, a semiconductor die mounted on the die pad, a plurality of leads including a power lead disposed along a peripheral edge of the die pad, at least one connecting bar connecting the die pad, a power bar disposed on one side of the connecting bar, and a surface mount device (SMD) having a first terminal and a second terminal. The first terminal is electrically connected to the ground level through a first bond wire. The second terminal is electrically connected a power level through a second bond wire.

Abstract: A switched-capacitor DC-to-DC converter includes a first P-channel MOS transistor, a first N-channel MOS transistor, a second P-channel MOS transistor, and a second N-channel MOS transistor which are connected in series. Drain terminals of the first P-channel MOS transistor and the first N-channel MOS transistor are connected to each other through a first node, and drain terminals of the second P-channel MOS transistor and the second N-channel MOS transistor are connected to each other through a second node. A capacitor is coupled between the first and second nodes. The capacitor includes a first capacitor and a second capacitor which are coupled in parallel between the first and second nodes.

Abstract: A semiconductor device includes a base member, a first structure body, a second structure body, a first contact portion, a second contact portion, and a first post. The first structure body is provided above the base member. The first structure body has a first terrace in a front surface of a first end portion of the first electrode layer. The second structure body is provided on the first structure body other than the first end portion. The second structure body has a second terrace in a front surface of a second end portion of the second electrode layer. The side surface of the second electrode layer is at a first level difference between the first terrace and the second terrace. The first post is disposed between the first contact portion and the second contact portion. The first post crosses the first level difference.

Abstract: Various embodiments relate to a semiconductor package structure. The semiconductor package structure includes a first chip having a first surface and a second surface opposite the first surface. The semiconductor package structure further includes a supporter surrounding an edge of the first chip. The semiconductor package structure further includes a conductive layer disposed over the first surface of the first chip and electrically connected to the first chip. The semiconductor package structure further includes an insulation layer disposed over the first surface of the first chip, wherein the insulation layer extends toward and overlaps the supporter in a vertical projection direction. The semiconductor package structure further includes an encapsulant between the first chip and the supporter and surrounding at least the edge of the first chip.

Abstract: An in-cell touch panel and a display device are disclosed. In the in-cell touch panel, a plurality of mutually independent self-capacitance electrodes arranged in the same layer are disposed on an array substrate in accordance the self-capacitance principle; a touch detection chip can determine the touch position by the detection of the capacitance variation of the self-capacitance electrodes; leads arranged in the same layer as pixel electrodes are disposed at gaps between the pixel electrodes and configured to connect the self-capacitance electrodes to the touch detection chip. The touch panel can reduce the manufacturing cost and improve the productivity.

Abstract: Provided are a method of fabricating a hafnium oxide layer and a method of fabricating a semiconductor device using the same. The method of fabricating a tetragonal hafnium oxide layer includes providing a substrate and then forming an initial hafnium oxide layer on the substrate. The initial hafnium oxide layer may have an amorphous structure, a monoclinic crystal structure, or a mixed structure thereof on the substrate. Phase-changing the initial hafnium oxide layer to a tetragonal hafnium oxide layer by heating the initial hafnium oxide layer at a temperature equal to or higher than a phase change temperature to the tetragonal hafnium oxide layer, is performed. Then, the heated tetragonal hafnium oxide layer may be rapidly cooled to suppress nucleation and growth of a monoclinic hafnium oxide in the tetragonal hafnium oxide layer.

Abstract: A metal capacitor is formed with good conductivity for both nodes of the capacitor and improved reliability. An embodiment includes a first layer of alternating first and second metal lines, a second layer of alternating third and fourth metal lines, a dielectric layer between the first and second layers, and vias in the dielectric layer connecting the first and second metal lines with the third and fourth metal lines, respectively, wherein each metal line comprises alternating first segments having a first width and second segments having a second width, the first width being greater than the second width, each first segment lying adjacent to a second segment of an adjacent metal line, and only first segments of the metal lines overlapping the vias.

Abstract: A metal-insulator-metal capacitor includes a bottom electrode comprising a nitride of a metal, an insulator disposed on the bottom electrode and comprising an oxide of the metal, and a top electrode disposed on the insulator and comprising a nitride of the metal. Optionally, the insulator further includes an oxynitride of the metal, at least a portion of the oxynitride being characterized by a progressive change in the ratio of oxygen to nitrogen over thickness.

Abstract: An isolation system, isolation device, and Integrated Circuit are disclosed. The isolation system is described to include an integrated circuit chip having a first capacitive plate, a second capacitive plate positioned with respect to the first capacitive plate to enable a capacitive coupling therebetween, an enhanced isolation layer positioned between the first capacitive the second capacitive plate that facilitates an electrical isolation between the first capacitive plate and the second capacitive plate, a first bonding wire that is in electrical communication with the second capacitive plate, and an isolation trench that at least partially circumscribes the first capacitive plate and is positioned between the first capacitive plate and the first bonding wire.

Abstract: A capacitance structure includes a first input terminal configured to input a first input signal, a first output terminal configured to output the first output signal, a second input terminal configured to input a second input signal, a second output terminal configured to output a second output signal, and a plurality of trench cells. Each of the plurality of trench cells includes a first electrode and a second electrode. The first electrodes of the plurality of trenches are interconnected to form a first electrode of the capacitor structure, the second electrodes of the plurality of trench cells are interconnected to form a second electrode of the capacitor structure, the first electrode of the capacitor structure is connected to the first input signal, and the second electrode of the capacitor structure is connected to the input second signal.

Abstract: A semiconductor device includes an electrical insulating layer with superior heat resistance, heat dissipation, and durability, and which is manufactured through a process with good cost performance and process performance. In a semiconductor device including a first substrate to which a semiconductor chip is mounted directly or indirectly, and a white insulating layer formed on a surface of the first substrate and functioning as a reflecting material, the semiconductor chip is an LED, at least the surface of the first substrate is made of a metal, and a stacked structure of the white insulating layer and a metal layer is formed by coating a liquid material, which contains SiO2 in the form of nanoparticles and a white inorganic pigment, over the surface of the first substrate and baking the coated liquid material.

Abstract: A touch screen panel includes a substrate having active and non-active areas, a plurality of first sensing electrodes in the active area, a plurality of second sensing electrodes in the active area, a plurality of row outer lines in the non-active area, a plurality of column outer lines in the non-active area, and first compensation patterns in the non-active area. The plurality of first sensing electrodes may be arranged in rows, each row line having a first end and a second end. The plurality of second sensing electrodes may be arranged in columns, each column having a first end and a second end. The plurality of row outer lines may be connected to respective first row line end. The plurality of column outer lines may be connected to respective first column line ends. The first compensation patterns may be connected respectively to the second row line ends.

Abstract: The invention relates to a capacitor structure (2) comprising a silicon substrate (4) with first and second sides (6, 8), a double double Metal Insulator Metal trench capacitor (10) including a basis electrode (12), an insulator layer (16, 20), a second and a third conductive layers (18, 22); and comprising a second pad (26) and a fourth pad (30) coupled to the basis electrode (12), a first pad (24) and a third pad (28) coupled together, the first pad (24) being located on the same substrate side than the second pad (26), the third pad (28) being located on the same substrate side than the fourth pad (30), the third pad (28) being coupled to the second conductive layer (18), said second conductive layer (18) being flush with or protruding from the opposite second side (8).

Abstract: Structures and methods of forming moisture barrier capacitor on a semiconductor component are disclosed. The capacitor is located on the periphery of a semiconductor chip and includes an inner plate electrically connected to a voltage node, an outer plate with fins for electrically connecting to a different voltage node.

Abstract: A device includes a chip assembled on an interposer. An electrically-insulating layer coats an upper surface of the interposer around the chip. First metal lines run on the upper surface of the interposer and are arranged between conductive elements of connection to the chip. An end of each first metal line is arranged to extend beyond a projection of the chip on the interposer. A thermally-conductive via connects the end of the first metal line to a heat sink supported at an upper surface of the device.

Abstract: An embodiment device includes a semiconductor substrate and an interconnect structure over the semiconductor substrate. The interconnect structure includes a functional circuit region and a first portion of a seal ring spaced apart from the functional circuit region by a buffer zone. The device also includes a passivation layer over the interconnect structure and a second portion of the seal ring over the passivation layer and connected the first portion of the seal ring. The second portion of the seal ring is disposed in the buffer zone.

Abstract: A method of fabricating a semiconductor device includes forming a first dielectric layer over a substrate that includes a gate structure, forming a first trench in the first dielectric layer, forming dielectric spacers along sidewalls of the first trench, removing a portion of the dielectric spacers to expose a portion of the sidewalls, forming a first metal feature in the first trench over the another portion of the dielectric spacers and along the exposed portions of the sidewalls of the first trench, forming a second dielectric layer over the first metal feature and the gate structure and forming a second trench through the second dielectric layer to expose a portion of the first metal feature and a third trench through the second dielectric layer and the first dielectric layer to expose a portion of the gate structure in the same etching process.

Abstract: A multilayer semiconductor device structure comprising a first buried oxide and a first semiconductor device layer fabricated above the first buried oxide is provided. The first semiconductor device layer comprises a patterned top surface. The patterned surface comprises insulator material and conductor material. The surface density of the insulator material is greater than 40 percent. The multilayer semiconductor device structure further comprises a second buried oxide bonded to the patterned surface of the first semiconductor device layer and a second semiconductor device layer fabricated above the second buried oxide.

Abstract: Provided are space-efficient capacitors that have a higher quality factor than conventional designs and improve coupling of electrical energy from a through-glass via (TGV) to a dielectric. For example, provided is a TGV having a non-rectangular cross-section, where one end of the TGV is coupled to a first metal plate. A dielectric material is formed on the first metal plate. A second metal plate is formed on the dielectric material in a manner that overlaps at least a portion of the first metal plate to form at least one overlapped region of the dielectric material. At least a part of the perimeter of the overlapped region is non-planar. The overlapped region can be formed in a shape of a closed ring, in a plurality of portions of a ring shape, in substantially a quarter of a ring shape, and/or in substantially a half of a ring shape.

Abstract: Hall effect devices and field effect transistors are formed incorporating a carbon-based nanostructure layer such as carbon nanotubes and/or graphene with a sacrificial metal layer formed there over to protect the carbon-based nanostructure layer during processing.