Abstract: A method includes bonding a first device die and a second device die to a substrate, and filling a gap between the first device die and the second device die with a gap-filling material. A top portion of the gap-filling material covers the first device die and the second device die. Vias are formed to penetrate through the top portion of the gap-filling material. The vias are electrically coupled to the first device die and the second device die. The method further includes forming redistribution lines over the gap-filling material using damascene processes, and forming electrical connectors over and electrically coupling to the redistribution lines.

Abstract: A microwave IC waveguide device module includes: a substrate having a throughhole; a microwave IC provided on or above the first face of the substrate; a waveguide member provided below the second face of the substrate opposite from the first face, the waveguide member having an electrically conductive waveguide face which opposes the throughhole; an electrically conductive member covering at least a portion of the second face that extends in a manner of following along the waveguide face; and an artificial magnetic conductor on both sides of the waveguide member. The substrate includes an inner-wall electrically conductive portion covering an inner wall of the throughhole and being electrically connected with the electrically conductive member. The signal terminal and the ground terminal of the IC are electrically connected respectively with two portions of the inner-wall electrically conductive portion opposing each other with the throughhole interposed therebetween.

Abstract: A semiconductor memory device includes a substrate having an active region, word lines extending across the active region, a bit line on the active region between the word lines, a bit line node contact between the bit line and the active region, and a storage node contact on an end portion of the active region, wherein one or more of the bit line node contact or the storage node contact include silicon germanium.

Abstract: A sacrificial interposer test structure including a release layer, a dummy layer on the release layer, one or more conductive pads embedded in the dummy layer, wherein each of the one or more conductive pads has an exposed surface, and a tie layer on the dummy layer and on each exposed surface of the one or more conductive pads.

Abstract: A power integrated module, including at least one first bridge formed in a chip, wherein the first bridge includes: a first upper bridge switch, formed by a plurality of first sub switches formed in the chip connected in parallel, and including a first, a second and a control end; a first lower bridge switch, formed by a plurality of second sub switches formed in the chip connected in parallel, and including a first, a second and a control end; a first electrode, connected to the first end of the first upper bridge switch; a second electrode, connected to the second end of the first lower bridge switch; and a third electrode, connected to the second end of the first upper bridge switch and the first end of the first lower bridge switch, wherein the first, the second and the third electrode are bar-type electrodes arranged side by side.

Abstract: An integrated trench capacitor and method for making the trench capacitor is disclosed. The method includes forming a trench in a silicon layer, forming a first dielectric on the exposed surface of the trench, performing an anisotropic etch of the first dielectric to expose silicon at the bottom of the trench, implanting a dopant into exposed silicon at the bottom of the trench, forming a first polysilicon layer over the first dielectric, forming a second dielectric over the first polysilicon layer, and forming a second polysilicon layer over the second dielectric to fill the trench.

Abstract: Certain aspects of the present disclosure provide an integrated circuit (IC) that includes at least one of a via-based vertical capacitor structure or a via-based vertical resistor structure. The IC includes a substrate oriented in a horizontal plane, electrically conductive layers disposed above the substrate, and electrically insulative layers disposed above the substrate and interposed between the plurality of electrically conductive layers. At least one of the vertical capacitor structure or the vertical resistor structure is disposed in the electrically conductive layers and the electrically insulative layers.

Abstract: A coreless package substrate with dual side solder resist layers is disclosed. The coreless package substrate has a top side and a bottom side opposite of the top side and includes a single build-up structure formed of at least one insulating layer, at least one via, and at least one conductive layer. The coreless package substrate also includes a bottom plurality of contact pads on the bottom side, and a top plurality of contact pads on the top side. A bottom solder resist layer is on the bottom side, and a top solder resist layer is on the top side. The concept of dual side solder resist is extended to packages with interconnect bridge with C4 interconnection pitch over a wide range.

Abstract: A method includes calculating a maximum value of an on-die decoupling capacitor for an integrated circuit (IC) design based on a switching current defined by a number of simultaneously switching bits for the IC design. The method also includes calculating a total decoupling capacitance value offered by spacer cells in the IC design. The method further includes determining an optimal on-die decoupling capacitance value for the IC design as a function of the maximum value of the on-die decoupling capacitor and the total decoupling capacitance value offered by the spacer cells.

Abstract: The present disclosure, in some embodiments, relates to an integrated chip. The integrated chip includes a lower interconnect layer disposed within a first inter-level dielectric (ILD) layer over a substrate. A plurality of MIM (metal-insulator-metal) structures are disposed within a second inter-level dielectric (ILD) layer over the lower interconnect layer. An upper interconnect layer is coupled to the plurality of MIM structures at first locations that are directly over second locations at which the lower interconnect layer is coupled to the plurality of MIM structures. One or both of the lower interconnect layer and the upper interconnect layer are comprised within a conductive path that electrically couples the plurality of MIM structures in a series connection.

Abstract: A tapered metal nitride structure having a gentle sloping (i.e., tapered) sidewall is provided that includes an oxygen rich metal nitride portion located between each metal nitride portion of a stack of metal nitride portions. The structure is formed by incorporating/introducing oxygen into an upper portion of a first metal nitride layer to form an oxygen rich metal nitride surface layer. A second nitride is then formed atop the oxygen rich metal nitride surface layer. The steps of oxygen incorporation/addition and nitride layer formation may be repeated any number of times. An etch mask is then provided and thereafter a sputter etch is performed to provide the tapered metal nitride structure. The tapered metal nitride structure may be used as an electrode in a semiconductor device.

Abstract: A capacitor includes a first set of conductive fingers having a first conductive pitch at a first interconnect layer and arranged in a first unidirectional routing. The capacitor further includes a second set of conductive fingers having a second conductive pitch at a second interconnect layer and arranged in a second unidirectional routing that is orthogonal to the first unidirectional routing. The first conductive pitch is different from the second conductive pitch. A first set of through finger vias electrically couples the first set of conductive fingers of the first interconnect layer to the second set of conductive fingers of the second interconnect layer. A third set of conductive fingers at a third conductive layer are parallel to, but offset from, the first set of conductive fingers. A second set of through finger vias electrically couples the third set of conductive fingers to the second set of conductive fingers.

Abstract: A method for fabricating a fingerprint sensor includes providing a base substrate including a plurality of pixel regions, forming a sensing dielectric structure on the base substrate in the plurality of pixel regions, and forming a sensing connection structure in the sensing dielectric structure. The sensing dielectric structure exposes the sensing connection structure, and the sensing connection structure is connected to the base substrate. The method also includes forming a plurality of electrode plates on surfaces of the sensing dielectric structure and the sensing connection structure, forming a plurality of protrusions on surfaces of the electrode plates by performing a bulging treatment process on the plurality of electrode plates, and forming an insulation medium structure on the plurality of electrode plates.

Abstract: In an embodiment, a semiconductor device includes: a lead-frame including one or more electrically conductive areas, one or more dielectric layers over the electrically conductive area or areas, one or more electrically conductive layer over the one or more dielectric layers thus forming one or more capacitors each including the dielectric layer sandwiched between an electrically conductive area and the electrically conductive layer. The semiconductor device also includes a semiconductor die on the lead-frame electrically connected to the one or more electrically conductive layers.

Abstract: A method includes forming an adhesive layer over a carrier, forming a sacrificial layer over the adhesive layer, forming through-vias over the sacrificial layer, and placing a device die over the sacrificial layer. The Method further includes molding and planarizing the device die and the through-vias, de-bonding the carrier by removing the adhesive layer, and removing the sacrificial layer.

Abstract: RF semiconductor chips may be packaged on wafer level on the basis of a two-step process for providing a package material, thereby providing very short electrical connections between antenna structures formed in the package material and the semiconductor chip. In some illustrative embodiments, the antenna structures may be provided above the semiconductor chip, which results in a very space-efficient overall configuration.

Abstract: A multilayer ceramic capacitor includes a body a first internal electrode and a second internal electrode disposed with a dielectric layer interposed therebetween, a first connecting electrode connected to the first internal electrode through the body, a second connecting electrode connected to the second internal electrode through the body, a first external electrode disposed on one surface of the body and connected to the first connecting electrode, and a second external electrode disposed on one surface of the body, spaced apart from the first external electrode, and connected to the second connecting electrode, wherein the first and second external electrodes each include a first electrode layer disposed on the body and including ceramics, and a second electrode layer disposed on the first electrode layer and having the content of ceramics smaller than that of the first electrode layer.

Abstract: Methods for fabricating a structure that includes a metal-insulator-metal (MIM) capacitor and structures that include a MIM capacitor. The MIM capacitor includes a layer stack with a first electrode, a second electrode, and a third electrode. The layer stack includes a pilot opening extending at least partially through at least one of the first electrode, the second electrode, and the third electrode. A dielectric layer is arranged over the metal-insulator-metal capacitor, and includes a via opening extending vertically to the pilot opening. A via is arranged in the via opening and the pilot opening. The pilot opening has a cross-sectional area that is less than a cross-sectional area of the via opening.

Abstract: A method for fabricating a semiconductor device includes: forming a mold stack pattern including a plurality of openings in an upper portion of a substrate and including a mold layer and a supporter layer which are stacked; forming a bottom electrode layer filling the plurality of the openings and covering the supporter layer; forming a filler portion disposed inside the plurality of the openings, a barrier portion extended upwardly from the filler portion, and an electrode cutting portion exposing a surface of the supporter layer by selectively etching the bottom electrode layer; forming a supporter by using the barrier portion as an etch barrier and etching the supporter layer exposed by the electrode cutting portion; selectively removing the barrier portion to form a hybrid pillar-type bottom electrode disposed inside the plurality of the openings; and removing the mold layer.

Abstract: A metal-insulator-metal (MIM) capacitor structure includes source and drain regions formed within a semiconductor substrate, a first conducting layer formed over the source and drain regions, and a dielectric layer formed over the first conducting layer. The MIM capacitor structure further includes a second conducting layer formed over the dielectric layer, and a sidewall dielectric formed adjacent the first conducting layer and the dielectric layer. An electric field is created indirectly through the sidewall dielectric to an adjacent field effect transistor (FET) channel in the semiconductor substrate.

Abstract: According to one embodiment, a semiconductor memory device includes a first memory chip, a circuit chip, and an external connection electrode on a surface of the first memory chip. The first memory chip comprises first conductors stacked via an insulator, and a first pillar passing the first conductors. The circuit chip comprises a substrate, a control circuit, and a second conductor connected to the control circuit, the circuit chip being attached to the first memory chip. The external connection electrode comprises a portion extending from a side of the surface of the first memory chip through the first memory chip and connected to the second conductor. Part of the first conductors is between the external connection electrode and the substrate.

Abstract: A semiconductor device includes a substrate, a first gate structure including first gate electrodes that are vertically stacked on the substrate, first channels penetrating the first gate structure to contact the substrate, a second gate structure including a channel connection layer on the first gate structure and second gate electrodes on the channel connection layer, second channels penetrating the second gate structure to contact the first channels, respectively, and separation regions penetrating the second gate structure and the first gate structure and extending in a first direction. The second gate electrodes are vertically stacked on the channel connection layer. The channel connection layer is between the separation regions and has at least one sidewall that is spaced apart from sidewalls of the separation regions.

Abstract: A plurality of semiconductor devices (5) are formed on a semiconductor wafer (1). A film thickness measurement wiring pattern (3,4) is formed on a dicing line (6,7) defining the plurality of semiconductor devices (5). An SOG film (10) is formed on the semiconductor devices (5) and the film thickness measurement wiring pattern (3,4). A film thickness of the SOG film (10) at a central part of the film thickness measurement wiring pattern (3,4) is measured. The film thickness measurement wiring pattern (3,4) is a rectangular pattern having long sides parallel to the dicing line (3,4).

Abstract: Moisture detection and ingression monitoring systems and methods of manufacture are provided. The moisture detection structure includes chip edge sealing structures including at least one electrode forming a capacitor structured to detect moisture ingress within an integrated circuit. The at least one electrode and a second electrode of the capacitor is biased to ground and to a moisture detection circuit or vice versa, respectively.

Abstract: A method of forming a capacitor includes the following steps. First, a substrate is provided. A dielectric layer is formed over the substrate. A first patterning process is performed to form a first contact plug through the whole thickness of the dielectric layer and a second patterning process is performed to form a second contact plug in the dielectric layer and spaced apart from the first contact plug in a pre-determined distance, wherein the first contact plug and the second contact plug are capacitively coupled.

Abstract: A method for forming a semiconductor device structure is provided. The method includes forming a first hole and a second hole in a first surface of a substrate. The method includes forming a first insulating layer in the first hole and the second hole. The method includes forming a conductive layer over the first insulating layer and in the first hole and the second hole. The method includes forming a second insulating layer over the conductive layer in the first recess. The second insulating layer has a second recess in the first recess. The method includes forming a conductive structure in the second recess. The method includes partially removing the substrate, the first insulating layer, the conductive layer, and the second insulating layer from a second surface of the substrate to expose the conductive structure and the conductive layer in the first hole and the second hole.

Abstract: An integrated circuit includes a stacked MIM capacitor and a thin film resistor and methods of fabricating the same are disclosed. A capacitor bottom metal in one capacitor of the stacked MIM capacitor and the thin film resistor are substantially at the same layer of the integrated circuit, and the capacitor bottom metal and the thin film resistor are also made of substantially the same materials. The integrated circuit with both of a stacked MIM capacitor and a thin film resistor can be made in a cost benefit way accordingly, so as to overcome disadvantages mentioned above.

Abstract: A semiconductor device is disclosed. In one example, the semiconductor device includes: an electronic component having a top surface, a bottom surface, and two end portions; a plurality of contacts disposed on the top surface; and a plurality of metal nodes disposed on the plurality of contacts. The plurality of contacts includes two end contacts disposed at the two end portions respectively and at least one intermediate contact disposed between the two end contacts. The plurality of metal nodes includes two end metal nodes disposed on the two end contacts respectively and at least one intermediate metal node disposed on the at least one intermediate contact.

Abstract: High aspect ratio passive electrical components are presented formed from a single-piece silicon (Si) substrate having a textured surface with at least one high aspect ratio structure. The high aspect ratio structure includes a Si core having a width (CX), a height (CZ), and a minimum aspect ratio of CZ-to-CX of at least 5:1. An electrical conductor layer overlies the Si core. The electrical component may be a capacitor, inductor, or transmission line. In the case of a capacitor, the substrate textured first surface is made up of a plurality of adjacent high aspect ratio conductor-dielectric-Si (CDS) structures. Each CDS structure includes: a Si core, a dielectric layer overlying the Si core, and an electrical conductor layer overlying the dielectric layer. The Si cores may be formed in the geometry of parallel ridges, columns, or as a honeycomb. Each Si core comprises at least 90% of the CDS structure height.

Abstract: A semiconductor arrangement includes an active region including a semiconductor device. The semiconductor arrangement includes a capacitor. The capacitor includes a first electrode over at least one dielectric layer over the active region. The first electrode surrounds an open space within the capacitor. The first electrode has a non-linear first electrode sidewall.

Abstract: A method of making a fusion bonded circuit structure. A substrate is provided with a seed layer of a conductive material. A first resist layer is deposited on the seed layer. The first resist layer is processed to create first recesses corresponding to a desired first circuitry layer. The first recesses expose, portions of the seed layer of conductive material. The substrate is electroplated to create first conductive traces defined by the first recesses. The first resist layer is removed to reveal the first conductive traces. The substrate is etched to remove exposed portions of the seed layer adjacent the first conductive traces. A portion of the seed layer is interposed between the first conductive traces and the substrate. A first layer of LCP is fusion boned to the first major surface of the substrate to encapsulate the first conductive traces in an LCP material. The first LCP layer can be laser drilled to expose the conductive traces.

Abstract: One or more embodiments are directed to semiconductor packages that include conductive test pads that are electrically coupled to, but distinct from, the leads of the package. In one embodiment the test pads are located on the plastic packaging material, such as encapsulation material, of the package and are electrically coupled to the leads of the package by traces. The traces may also be located on the packaging material and portions of the leads. In one embodiment, all of the test pads are located on a single surface of the packaging material of the package, which may allow for ease of electrical testing of the package.

Abstract: A power system for a vehicle comprising: a battery; a charging interface for receiving external power to charge the battery; a network connecting the battery and the charging interface, wherein at least a part of the network is a DC network; an active EMI filter between the battery and the charging interface in the DC network.

Abstract: A semiconductor device includes a base structure including contacts and a first interlevel dielectric (ILD) layer, a metal-insulator metal (MIM) capacitor structure on the base structure, a second ILD layer on the MIM capacitor structure, and a plurality of vias including a first via on a first one of the contacts and penetrating through the first and second ILD layers, first and third etch tuning layers of the MIM capacitor structure and a second plate of the MIM capacitor structure, and a second via on a second one of the contacts and penetrating through the first and second ILD layers, a second etch tuning layer of the MIM capacitor structure, and first and third plates of the MIM capacitor structure.

Abstract: Many integrated circuit die are fabricated on a wafer. Each die includes integrated functional circuitry with an array of fuse elements that are visible to optical inspection. An electrical wafer sort is performed to test the integrated functional circuitry of each die. The array of fuse elements for each die on the wafer are programmed through the electrical wafer sort process with data bits defining a die identification that specifies a location of the die on the wafer. The die is then encapsulated in a package. In the event of package failure, a decapsulation is performed to access the die. Optical inspection of the array of fuse elements is then made to extract the die identification.

Abstract: The invention provides a semiconductor device including a capacitor capable of securing capacity and exhibiting improved reliability and a semiconductor package comprising the same. The semiconductor device includes: a substrate having a cell block; a plurality of capacitors, which are in the cell block of the substrate and have first electrodes; and a support pattern, which contacts sidewalls of the first electrodes of the plurality of capacitors and supports the plurality of capacitors, wherein the support pattern includes an upper support pattern including: a first upper pattern having a plate-like structure connected as a whole in the cell block; and a second upper pattern, which contacts a bottom surface of the first upper pattern and has a top surface having a smaller area than the bottom surface of the first upper pattern, the upper support pattern contacting sidewalls of upper ends of the first electrodes.

Abstract: In a thin-film capacitor, a first extraction electrode provided along a side surface of a first groove portion is in contact with a first electrode layer and is not in contact with a second electrode layer. Also, a second extraction electrode provided along a side surface of a second groove portion is in contact with the second electrode layer exposed on the side surface of the second groove portion and is not in contact with the first electrode layer. Thus, a capacitor structure in which the first electrode layer in contact with the first extraction electrode and the second electrode layer in contact with the second extraction electrode are laminated with a dielectric layer therebetween is formed between the first groove portion and the second groove portion.

Abstract: A package structure includes a substrate, a metal-insulator-metal capacitor, a circuit redistribution structure, and a chip. The metal-insulator-metal capacitor is disposed over the substrate and includes a first electrode, a second electrode, and an insulating layer. The circuit redistribution structure is disposed over the metal-insulator-metal capacitor and includes a first circuit redistribution layer and a second circuit redistribution layer. The first circuit redistribution layer includes a first wire electrically connected to the first electrode and a second wire electrically connected to the second electrode. The second circuit redistribution layer is disposed on the first circuit redistribution layer and includes a third wire electrically connected to the first wire and a fourth wire electrically connected to the second wire. The chip is disposed over the circuit redistribution structure and electrically connected to the third wire and the fourth wire.

Abstract: A resin substrate includes a thermoplastic resin base body, a mounting land conductor on a surface of the resin base body to be connected to a component, first and second reinforcement conductor patterns, and first interlayer connection conductors. The first and second reinforcement conductor patterns are each embedded in the resin base body and have a planar shape that includes a position overlapping the mounting land conductor when viewing the resin base body in plan view. The first interlayer connection conductors connect the first and second reinforcement conductor patterns in a thickness direction of the resin base body. The first interlayer connection conductors are arranged at positions different from the mounting land conductor when viewing the resin base body in plan view.

Abstract: A semiconductor device can include a plurality of landing pads arranged according to a layout on a substrate, wherein a cross-sectional shape of each of the landing pads has a diamond shape so that opposing interior angles of the diamond shape are equal to one another and adjacent interior angles of the diamond shape are unequal to one another.

Abstract: Devices and methods for forming a device are disclosed. A substrate is provided. The substrate has first and second major surfaces. A capacitor is disposed in the substrate. The capacitor includes a first electrode, a second electrode and an insulator separating the first and second electrodes. The second electrode encloses the first electrode and the insulator.

Abstract: To obtain a compact and high output power conversion device by achieving high heat dispersion performance and a reduction in heat generation, and enabling an efficient arrangement of power modules of three-phase circuits, four switchable power semiconductor chips of each of the power modules are arranged so that two pairs of circuits for one phase connected in series are connected in parallel to form a circuit for two phases, the lead frame includes two positive potential leads, two AC potential leads, and one negative potential lead that are separated from each other, the four switchable power semiconductor chips are individually arranged on four leads of the two positive potential leads and the two AC potential leads, the two positive potential leads each have an end portion connected to a bus bar via a welding point individually provided for each phase, and the bus bar is provided in common.

Abstract: A semiconductor device according to a first aspect of the present invention includes a device main body, a single power supply wiring board, a plurality of output wiring boards, and a plurality of semiconductor elements. In a long-side direction of the device main body, the narrow portion of one of any two adjacent wiring boards faces the wide portion of another one of the any two adjacent wiring boards. In a short-side direction of the device main body, the narrow portion and the wide portion of each of the output wiring boards respectively face the wide portion and the narrow portion, in a single pair, of the power supply wiring board. In the long-side direction of the device main body a width of each of the output wiring boards is smaller than a sum of widths of the narrow portion and the wide portion, in a single pair, of the power supply wiring board.

Abstract: A multilayer electronic component includes first, second, and third ceramic layers, first and second inner electrodes, and a via-electrode. The first, second and third ceramic layers are sequentially stacked on each other. The first inner electrode is sandwiched between the first and second ceramic layers. The second inner electrode is sandwiched between the second and third ceramic layers. The via-electrode electrically connects the first and second inner electrodes. A projection is integrally provided with the via-electrode. The projection projects from the via-electrode towards an outer peripheral direction and is inserted into the second ceramic layer in a layered arrangement.

Abstract: A method is described for stacking a plurality of cores. For example, one embodiment comprises: mounting an uncore die on a package, the uncore die comprising a plurality of exposed landing slots, each landing slot including an inter-die interface usable to connect vertically to a cores die, the uncore die including a plurality of uncore components usable by cores within the cores die; and vertically coupling a first cores die comprising a first plurality of cores on top of the uncore die, the cores spaced on the first cores die to correspond to all or a first subset of the landing slots on the uncore die, each of the cores having an inter-die interface positioned to be communicatively coupled to a corresponding inter-die interface within a landing slot on the uncore die when the first cores die is vertically coupled on top of the uncore die.

Abstract: A multilayer thin-film capacitor includes a multilayer body in which a plurality of dielectric layers and first and second internal electrode layers are alternately stacked, and first and second external electrodes are disposed on the multilayer body and connected to the first and second internal electrode layers, respectively. The multilayer thin-film capacitor may include a first edge via connected to the external electrode and disposed at or adjacent at least one edge of an upper surface of the multilayer body, and a second edge via connected to the second external electrode and disposed at or adjacent at least one edge of the upper surface of the multilayer body.

Abstract: A method for fabricating an electronic package is provided, which includes the steps of: providing an insulating layer having at least an electronic element embedded therein; forming at least a first via hole on one side of the insulating layer; forming a first conductor in the first via hole of the insulating layer; forming on the insulating layer a first circuit structure electrically connected to the electronic element and the first conductor; and forming a second via hole on the other side of the insulating layer, wherein the second via hole communicates with the first via hole. As such, the second via hole and the first via hole constitute a through hole. Since the through hole is fabricated through two steps, the aspect ratio (depth/width) of the through hole can be adjusted according to the practical need so as to improve the process yield.

Abstract: The disclosure is directed to semiconductor structures and, more particularly, to Metal-Insulator-Metal (MIM) capacitor structures and methods of manufacture. The method includes: forming at least one gate structure; removing material from the at least one gate structure to form a trench; depositing capacitor material within the trench and at an edge or outside of the trench; and forming a first contact in contact with a first conductive material of the capacitor material and a second contact in contact with a second conductive material of the capacitor material.

Abstract: A molecular sensor includes a substrate defining a substrate plane, and a plurality of pairs of electrode sheets above or below the substrate at an angle to the substrate plane. The molecular sensor further includes a plurality of inner dielectric sheets between each electrode sheet in each pair of electrode sheets of the plurality of pairs, and an outer dielectric sheet between each pair of electrode sheets of the plurality of pairs.

Abstract: According to one embodiment, a semiconductor memory device includes a first memory chip, a circuit chip, and an external connection electrode on a surface of the first memory chip. The first memory chip comprises first conductors stacked via an insulator, and a first pillar passing the first conductors. The circuit chip comprises a substrate, a control circuit, and a second conductor connected to the control circuit, the circuit chip being attached to the first memory chip. The external connection electrode comprises a portion extending from a side of the surface of the first memory chip through the first memory chip and connected to the second conductor. Part of the first conductors is between the external connection electrode and the substrate.