Abstract: According to an exemplary embodiment, a semiconductor device is provided. The semiconductor device includes a first seal ring and a first circuit. The first circuit includes a first capacitor and a first inductor connected in series. The first circuit is connected between the first seal ring and a ground.

Abstract: A metal-oxide-semiconductor transistor includes a substrate, a gate insulating layer disposed on the surface of the substrate layer, a metal gate disposed on the gate insulating layer and having at least one plug hole, at least one dielectric plug disposed in the plug hole, and two diffusion regions disposed at two sides of the metal gate in the substrate. The metal gate is configured to operate under an operation voltage greater than 5 v.

Abstract: A semiconductor device and methods of formation are provided herein. A semiconductor device includes a conductor concentrically surrounding an insulator, and the insulator concentrically surrounding a column. The conductor, the insulator and the conductor are alternately configured to be a transistor, a resistor, or a capacitor. The column also functions as a via to send signals from a first layer to a second layer of the semiconductor device. The combination of via and at least one of a transistor, a capacitor, or a resistor in a semiconductor device decreases an area penalty as compared to a semiconductor device that has vias formed separately from at least one of a transistor, a capacitor, or resistor.

Abstract: An electronic apparatus includes: a first substrate; an electrode over the first substrate; a first conductor having a porous structure above the first substrate, the first conductor covering an upper surface and a side surface of the electrode; and an insulator above the first substrate, the insulator covering an upper surface and a side surface of the first conductor, wherein the insulator has an opening that exposes the first conductor.

Abstract: An electronic circuit structure is formed with first and second dies bonded together. A first active layer is formed in the first die, and a second active layer is formed in the second die. The first and second dies are bonded together, with an isolation capacitor, through which the first and second active layers communicate, disposed between the first and second dies.

Abstract: A semiconductor integrated circuit device may include a through silicon via (TSV), a keep out zone and a plurality of dummy patterns. The TSV may be arranged in a selection region of a semiconductor substrate. The keep out zone may be configured to define a peripheral region of the TSV. The dummy patterns may be arranged in the keep out zone to receive a conductive signal. The dummy patterns may function as an electrode of a reservoir capacitor.

Abstract: A method of making a stack of the type comprising a first electrode, an active layer, and a second electrode, for use in an electronic device, in particular of the organic photodetector type or the organic solar cell type, the method comprising the following steps: a) depositing a first layer (2) of conductive material on a substrate (1) in order to form the first electrode; b) depositing an active layer (3) in the form of a thin organic semiconductor layer, this layer including non-continuous zones (30); c) locally eliminating the first conductive layer (2) through the non-continuous zones (30) of the active layer by chemical attack; and d) depositing a second layer (4) of conductive material on the active layer (3) in order to form the second conductive electrode.

Abstract: A fingerprint sensor having ESD protection has a body and an ESD protection circuit. The body has a fingerprint sensing electrode array and an ESD protection electrode providing an ESD protection to the fingerprint sensing electrode array. The ESD protection circuit is connected respectively to the ESD protection electrode, a high electric potential terminal and a low electric potential terminal. The ESD protection circuit provides a first static electricity discharge path to the high electric potential terminal, and a second static electricity discharge path to the low electric potential terminal. The fingerprint sensor provides two static electricity discharge paths, so that the fingerprint sensor has a better ESD protection.

Abstract: A first semiconductor structure including a first bonding oxide layer having a first metallic structure embedded therein and a second semiconductor structure including a second bonding oxide layer having second metallic structure embedded therein are provided. A high-k dielectric material is formed on a surface of the first metallic structure. A nitride surface treatment process is performed to provide a nitrided surface layer to each structure. The nitrided surface layer includes nitridized oxide regions located in an upper portion of the bonding oxide layers and either a nitridized high-k dielectric material located in at least an upper portion of the high k dielectric material or a nitridized metallic region located in an upper portion of the second metallic structure. The nitrogen within the nitridized metallic region is then selectively removed to restore the upper portion of the second metallic structure to its original composition. Bonding is then performed.

Abstract: A stacked semiconductor device includes: a plurality of stacked integrated-circuit chips that are to be mounted onto a substrate and including at least one power-supply target chip; a decoupling through-electrode transmission line including a decoupling power-supply-side through-electrode wiring line coupled to a power-supply terminal of the at least one power-supply target chip and a decoupling ground-side through-electrode wiring line coupled to a ground terminal of the at least one power-supply target chip; a resistor and a capacitor provided one of the a plurality of integrated-circuit chips that is located at a termination of the decoupling through-electrode transmission line, the resistor having an impedance substantially equal to a characteristic impedance of the decoupling through-electrode transmission line, wherein the resistor and the capacitor are coupled in series.

Abstract: The present invention generally relates to a MEMS DVC having a shielding electrode structure between the RF electrode and one or more other electrodes that cause a plate to move. The shielding electrode structure may be grounded and, in essence, block or shield the RF electrode from the one or more electrodes that cause the plate to move. By shielding the RF electrode, coupling of the RF electrode to the one or more electrodes that cause the plate to move is reduced and capacitance modulation is reduced or even eliminated.

Abstract: Some features pertain to an integrated device that includes a die and a first redistribution portion coupled to the die. The first redistribution portion includes at least one dielectric layer and a capacitor. The capacitor includes a first plate, a second plate, and an insulation layer located between the first plate and the second plate. The first redistribution portion further includes several first pins coupled to the first plate of the capacitor. The first redistribution portion further includes several second pins coupled to the second plate of the capacitor. In some implementations, the capacitor includes the first pins and/or the second pins. In some implementations, at least one pin from the several first pins traverses through the second plate to couple to the first plate of the capacitor. In some implementations, the second plate comprises a fin design.

Abstract: An integrated circuit chip includes a semiconductor substrate having thereon a plurality of inter-metal dielectric (IMD) layers and a plurality of first conductive layers embedded in respective said plurality of IMD layers, wherein said first conductive layers comprise copper; a first insulating layer overlying said plurality of IMD layers and said plurality of first conductive layers; at least a first wiring line in a second conductive layer overlying said first insulating layer, for distributing power signal or ground signal, wherein said second conductive layer comprise aluminum; and at least a second wiring line in a third conductive layer overlying said second conductive layer, for distributing power signal or ground signal.

Abstract: Metal-insulator-metal (MIM) capacitors with insulator stacks having a plurality of metal oxide layers are described. For example, a MIM capacitor for a semiconductor device includes a trench disposed in a dielectric layer disposed above a substrate. A first metal plate is disposed along the bottom and sidewalls of the trench. An insulator stack is disposed above and conformal with the first metal plate. The insulator stack includes a first metal oxide layer having a first dielectric constant and a second metal oxide layer having a second dielectric constant. The first dielectric constant is higher than the second dielectric constant. The MIM capacitor also includes a second metal plate disposed above and conformal with the insulator stack.

Abstract: A semiconductor device includes a first metallization layer including a first dielectric layer. A first conductive layer and a first conductive structure are embedded in the first dielectric layer. A second dielectric layer is disposed on the first metallization layer. A second conductive layer is disposed on the second dielectric layer and has a lateral dimension in a lateral direction larger than a lateral dimension of the first conductive layer in the lateral direction. A third dielectric layer is disposed on the second conductive layer. A first contact is disposed in the third dielectric layer and extends through the second conductive structure in a first peripheric region thereof that does not overlap the first conductive layer to contact the first conductive structure. A capacitor structure includes the first conductive layer, the second dielectric layer and the second conductive layer.

Abstract: Capacitor and contact structures are provided, as well as methods for forming the capacitor and contact structures. The methods include, for instance, providing a layer of conductive material above a conductive structure and above a lower electrode of a capacitor; etching the layer of conductive material to define a conductive material hard mask and an upper electrode of the capacitor, the conductive material hard mask being disposed at least partially above the conductive structure; and forming a first conductive contact structure and a second conductive contact structure, the first conductive contact structure extending through an opening in the conductive material hard mask and conductively contacting the conductive structure, and the second conductive contact structure conductively contacting one of the lower electrode of the capacitor, or the upper electrode of the capacitor.

Abstract: A semiconductor device has a semiconductor wafer. The semiconductor wafer includes a plurality of semiconductor die. An insulating layer is formed over an active surface of the semiconductor die. A trench is formed in a non-active area of the semiconductor wafer between the semiconductor die. The trench extends partially through the semiconductor wafer. A carrier with adhesive layer is provided. The semiconductor die are disposed over the adhesive layer and carrier simultaneously as a single unit. A backgrinding operation is performed to remove a portion of the semiconductor wafer and expose the trench. The adhesive layer holds the semiconductor die in place during the backgrinding operation. An encapsulant is deposited over the semiconductor die and into the trench. The carrier and adhesive layer are removed. The encapsulated semiconductor die are cleaned and singulated into individual semiconductor devices. The electrical performance and functionality of the semiconductor devices are tested.

Abstract: A multilayer wiring board includes: a functional area which includes a thin film capacitor having a dielectric layer between an upper electrode and a lower electrode; and a peripheral area other than the functional area, wherein a mooring portion in which the dielectric layer and a conductive layer are laminated is provided in at least a portion of the peripheral area, and a roughness of a surface of the conductive layer which contacts the dielectric layer is greater than a roughness of a surface of the upper electrode or the lower electrode which contacts the dielectric layer.

Abstract: A semiconductor device includes a lower electrode on a lower structure, a dielectric layer conformally covering a surface of the lower electrode, an upper electrode conformally covering a surface of the dielectric layer, and a barrier layer on the upper electrode. The barrier layer and the upper electrode define a space on a sidewall of the lower electrode.

Abstract: According to one embodiment a semiconductor memory device includes a first stacked body, a pillar, a memory film, a capacitive element, a first wiring, and a second wiring. The capacitive element includes a first conductive member and a second conductive member. A first length of the first conductive member in a first direction is larger than a second length of the first conductive member in a second direction crossing the first direction. A third length of the first conductive member in a third direction crossing the first direction and the second direction is larger than the second length. A fourth length of the second conductive member in the first direction is larger than a fifth length of the second conductive member in the second direction. A sixth length of the second conductive member in the third direction is larger than the fifth length.

Abstract: A method of forming a device comprises forming a through via extending from a surface of a substrate into the substrate. The method also comprises forming a first insulating layer over the surface of the substrate. The method further comprises forming a first metallization layer in the first insulating layer, the first metallization layer electrically connecting the through via. The method additionally comprises forming a capacitor over the first metallization layer. The capacitor comprises a first capacitor dielectric layer over the first metallization layer and a second capacitor dielectric layer over the first capacitor dielectric layer. The method also comprises forming a second metallization layer over and electrically connecting the capacitor.

Abstract: A method is provided for forming a metal-insulator-metal capacitor in a replacement metal gate module. The method includes providing a gate cap formed on a gate. The method further includes removing a portion of the gate cap and forming a recess in the gate. A remaining portion of the gate forms a first electrode of the capacitor. The method also includes depositing a dielectric on remaining portions of the gate cap and the remaining portion of the gate. The method additionally includes depositing a conductive material on the dielectric. The method further includes removing a portion of the conductive material and portions of the dielectric to expose a remaining portion of the conductive material and a remaining portion of the dielectric. The remaining portion of the conductive material forms a second electrode of the capacitor. The remaining portion of the dielectric forms an insulator of the capacitor.

Abstract: A semiconductor device having through-substrate vias is disclosed. In one aspect, the device includes a substrate having at least one front-end-of-line (FEOL) device and a back-end-of-line (BEOL) comprising a metal pad. The device additionally includes at least one first contact plug contacting the at least one FEOL device and at least one second contact plug underneath the metal pad and in electrical contact therewith. At least one second contact plug has one end contacting the metal pad and has other end contacting a material that is not part of a FEOL device.

Abstract: According to an embodiment of the invention there may be provided a die that may include a first capacitor layer that comprises (a) a first capacitor conductive plate, and (b) a first capacitor layer dielectric material that partially surrounds the first capacitor conductive plate; a first conductor; an intermediate metal layer that comprises (a) an intermediate metal layer conductor that is made of Copper, and (b) an intermediate metal layer dielectric material that partially surrounds the intermediate metal layer conductor; wherein the first conductor is positioned between a substrate of the die and the intermediate metal layer; a redistribution layer that comprises (a) a redistribution layer conductor that is electrically coupled to an interface pad of the die, (b) a second capacitor conductive plate, and (c) a redistribution layer dielectric material that partially surrounds the redistribution layer conductor and the second capacitor conductive plate; wherein a certain portion of the intermediate metal la

Abstract: Some embodiments include an integrated structure having a stack of alternating dielectric levels and conductive levels, vertically-stacked memory cells within the conductive levels, an insulative material over the stack and a select gate material over the insulative material. An opening extends through the select gate material, through the insulative material, and through the stack of alternating dielectric and conductive levels. A first region of the opening within the insulative material is wider along a cross-section than a second region of the opening within the select gate material, and is wider along the cross-section than a third region of the opening within the stack of alternating dielectric levels and conductive levels. Channel material is within the opening and adjacent the insulative material, the select gate material and the memory cells. Some embodiments include methods of forming vertically-stacked memory cells.

Abstract: A microelectronic system including hydrogen barriers and copper pillars for wafer level packaging and method of fabricating the same are provided. Generally, the method includes: forming an insulating hydrogen barrier over a surface of a first chip; exposing at least a portion of an electrical contact electrically coupled to a component in the first chip by removing a portion of the insulating hydrogen barrier, the component including a material susceptible to degradation by hydrogen; forming a conducting hydrogen barrier over at least the exposed portion of the electrical contact; and forming a copper pillar over the conducting hydrogen barrier. In one embodiment, the material susceptible to degradation is lead zirconate titanate (PZT) and the microelectronic systems device is a ferroelectric random access memory including a ferroelectric capacitor with a PZT ferroelectric layer. Other embodiments are also disclosed.

Abstract: Provided is a capacitor structure including a substrate, a dielectric layer, a first conductive layer, and a cup-shaped capacitor. The dielectric layer is located on the substrate. The first conductive layer is located in the dielectric layer. The cup-shaped capacitor penetrates through the first conductive layer and is located in the dielectric layer. The cup-shaped capacitor includes a bottom electrode, a capacitor dielectric layer, and a top electrode. Two sidewalls of the bottom electrode are electrically connected to the first conductive layer. The capacitor dielectric layer covers a surface of the bottom electrode. The top electrode covers a surface of the capacitor dielectric layer. The capacitor dielectric layer is located between the top electrode and the bottom electrode. A top surface of the bottom electrode is lower than a top surface of the top electrode. Also the invention provides a method of manufacturing the capacitor structure.

Abstract: A package substrate is provided. The package substrate includes: a dielectric layer; a passive component embedded in the dielectric layer and contacting the dielectric layer; and a circuit layer embedded in the dielectric layer and having a first surface aligned with a second surface of the dielectric layer.

Abstract: In one embodiment, an apparatus comprises a capacitor and a die. The die comprises a resistor switch coupled between a power line and the capacitor, wherein the resistor switch has an adjustable resistance, and the power line and the capacitor are both external to the die. The die also comprises a circuit configured to receive power from the power line, and a controller configured to open the resistor switch if the power line is powered down.

Abstract: A sensing method and circuit of fingerprint sensor is disclosed. In a first phase, the sensing method supplies a first to third voltages to an electrode plate to be measured, a read-out circuit of the electrode plate to be measured and a conductor adjacent to the electrode plate to be measured, respectively. In a second phase, the sensing method stops supplying the first to third voltages and supplies voltage to the conductor and connects the electrode plate to be measured to the read-out circuit so the read-out circuit reads out a measurement result of the electrode plate to be measured. According to the sensing method and circuit, the measurement result of the electrode plate to be measured is not affect by capacitors between the electrode plate to be measured and the conductor.

Abstract: Embodiments of the present disclosure include devices and sensor packages and methods of forming the same. An embodiment is a device including a first semiconductor chip. The first semiconductor chip includes a first substrate, a first conductive pad over the first substrate. The device further includes a second semiconductor chip having a second surface bonded to a first surface of the first semiconductor chip. The second semiconductor chip includes a second substrate and a second conductive pad over the second substrate. The second conductive pad and the first conductive pad form a first capacitor.

Abstract: Packaging solutions for large area, GaN die comprising one or more lateral GaN power transistor devices and systems are disclosed. Packaging assemblies comprise an interposer sub-assembly comprising the lateral GaN die and a leadframe. The GaN die is electrically connected to the leadframe using bump or post interconnections, silver sintering, or other low inductance interconnections. Then, attachment of the GaN die to the substrate and the electrical connections of the leadframe to contacts on the substrate are made in a single process step. The sub-assembly may be mounted in a standard power module, or alternatively on a substrate, such as a printed circuit board. For high current applications, the sub-assembly also comprises a ceramic substrate for heat dissipation. This packaging scheme provides interconnections with lower inductance and higher current capacity, simplifies fabrication, and enables improved thermal matching of components, compared with conventional wirebonded power modules.

Abstract: An electronic device is provided. A first PCB includes a plurality of ground pads. A fingerprint sensor includes a sensing array, an insulating surface disposed on the sensing array, and a second PCB disposed between the sensing array and the first PCB. The sensing array senses fingerprint information of a user. The second PCB includes a substrate having a first surface and a second surface opposite the first surface, a metal trace disposed on the first surface and adjacent to the sensing array, and a plurality of ESD pads disposed on the second surface and coupled to the first ground pads of the first PCB, respectively. When an ESD event occurs, ESD energy is discharged from the metal trace to the first ground pads of the first PCB through a plurality of vias and the ESD pads without passing through the sensing array.

Abstract: Certain embodiments provide a parallel capacitor including a substrate configured by a dielectric, upper electrodes, and a lower electrode. The upper electrodes are provided in an upper electrode region on a surface of the substrate. The lower electrode is provided on an entire surface of a lower electrode region including a region corresponding to the upper electrode region of an underside of the substrate, the lower electrode region being wider than the region. A single-operation capacity of each capacitor on both ends is smaller than the single-operation capacity of a capacitor in a center portion. The capacitors on the both ends are configured by the upper electrodes arranged on both ends of the substrate, the lower electrode, and the substrate. The capacitor in the center portion is configured by the upper electrode arranged in a center portion of the substrate, the lower electrode, and the substrate.

Abstract: A method for the formation of a MIM capacitor on a substrate is described. Initially, a target comprising a metal is sputtered in the presence of nitrogen to form at least a portion of a bottom electrode. Next, the target is further sputtered in the presence of oxygen to form at least a part of an insulator. Finally, the target is even further sputtered in the presence of nitrogen to form a portion of a top electrode. The insulator is sandwiched between the bottom electrode and the top electrode. The formation of the bottom electrode, the insulator, and the top electrode is performed in a sputter deposition chamber without removing the substrate therefrom.

Abstract: In the wiring board of the present invention, the land pattern for power supply, connected to the semiconductor element connection pad for power supply through a via conductor and arranged below the segment region, includes a strip-shaped continued portion in the position corresponding to the outer peripheral portion except the outer peripheral side of the mounting portion in the segment region, and the strip-shaped continued portion and the power supply plane arranged therebelow are connected through a via conductor.

Abstract: The present invention provides a method for manufacturing a flexible display device, which includes the following steps: (1) providing a flexible substrate and a number of clamps; (2) securing edges of the flexible substrate with the number of clamps; and (3) subjecting the flexible substrate to operations of exposure, development, etching, thin film deposition, annealing, and film formation, wherein in each of the operations, the clamps are adjusted in order to adjust flatness and amount of contraction of the flexible substrate and also, the clamps are adjusted to adjust angle of the flexible substrate.

Abstract: Apparatuses, systems, and methods for ion traps are described herein. One apparatus includes a number of microwave (MW) rails and a number of radio frequency (RF) rails formed with substantially parallel longitudinal axes and with substantially coplanar upper surfaces. The apparatus includes two sequences of direct current (DC) electrodes with each sequence formed to extend substantially parallel to the substantially parallel longitudinal axes of the MW rails and the RF rails. The apparatus further includes a number of through-silicon vias (TSVs) formed through a substrate of the ion trap and a trench capacitor formed in the substrate around at least one TSV.

Abstract: An array substrate and a manufacturing method thereof, and a display device are provided.

Abstract: The invention provides a semiconductor package assembly. The semiconductor package assembly includes a first semiconductor package. The first semiconductor package includes a first semiconductor die having first pads thereon. First vias are disposed on the first semiconductor die, coupled to the first pads. A first dynamic random access memory (DRAM) die is mounted on the first semiconductor die, coupled to the first vias. A second semiconductor package is stacked on the first semiconductor package. The second semiconductor package includes a body having a die-attach surface and a bump-attach surface opposite to the die-attach surface. A second dynamic random access memory (DRAM) die is mounted on the die-attach surface, coupled to the body through the bonding wires. The number of input/output (I/O) pins of first DRAM die is different from the number of input/output (I/O) pins of the second DRAM die.

Abstract: Provided are space-efficient capacitors that have a higher quality factor than conventional designs and improve coupling of electrical energy from a through-glass via (TGV) to a dielectric. For example, provided is a TGV having a non-rectangular cross-section, where one end of the TGV is coupled to a first metal plate. A dielectric material is formed on the first metal plate. A second metal plate is formed on the dielectric material in a manner that overlaps at least a portion of the first metal plate to form at least one overlapped region of the dielectric material. At least a part of the perimeter of the overlapped region is non-planar. The overlapped region can be formed in a shape of a closed ring, in a plurality of portions of a ring shape, in substantially a quarter of a ring shape, and/or in substantially a half of a ring shape.

Abstract: A proximity switch assembly and method for detecting activation of a proximity switch assembly is provided. The assembly includes a plurality of proximity switches each having a proximity sensor providing a sense activation field. A first proximity sensor generates a first activation field and comprises first and second electrodes having first fingers interdigitated with second fingers. A second proximity sensor generates a second activation field and comprises third and fourth electrode fingers having third fingers interdigitated with fourth fingers. The first and second electrodes are interleaved with the third and fourth electrodes.

Abstract: A semiconductor device includes a semiconductor die, a power switch, a gate driver, and decoupling capacitor. The power switch includes a power FET having a plurality of power FET segments formed in the semiconductor die. The gate driver has a plurality of gate driver segments formed in the semiconductor die, at least a portion of the gate driver segments being distributed among the power FET segments. The decoupling capacitor has a plurality of decoupling capacitor segments formed in the semiconductor die, the decoupling capacitor segments being distributed among the gate driver segments.

Abstract: A semiconductor device comprising: a first, a second and a third conductive layer; the second conductive layer being located between the first and third conductive layers; wherein respective regions of the first and second conductive layers form a first capacitor; and respective regions of the second and third conductive layers form a second capacitor.

Abstract: In an example, a capacitor in an integrated circuit (IC), includes: a first finger capacitor formed in at least one layer of the IC having a first bus and a second bus; a second finger capacitor formed in the at least one layer of the IC having a first bus and a second bus, where a longitudinal edge of the second bus of the second finger capacitor is adjacent a longitudinal edge of the first bus of the first finger capacitor and separated by a dielectric gap; and a first metal segment formed on a first layer above the at least one layer, the first metal segment being electrically coupled to the first bus of the first finger capacitor and increasing a width and a height of the first bus of the first finger capacitor.

Abstract: An electronic module includes a substrate including at least one structure that reduces stress flow through the substrate, wherein the structure includes at least one trench in a surface of the substrate, and a plurality of capacitor legs disposed on an upper surface of the substrate.

Abstract: A package substrate is provided that includes a core substrate and a capacitor embedded in the core substrate including a first side. The capacitor includes a first electrode and a second electrode disposed at opposite ends of the capacitor. The package also includes a first power supply metal plate extending laterally in the core substrate. The first power supply metal plate is disposed directly on the first electrode of the capacitor from the first side of the core substrate. A first via extending perpendicular to the first metal plate and connected to the first power supply metal plate from the first side of the core substrate.

Abstract: A method of manufacturing a capacitor for a semiconductor device includes forming a lower electrode, forming a dielectric layer on the lower electrode, forming a first upper electrode on the dielectric layer, adsorbing an organic silicon source onto a surface of the first upper electrode, and forming a second upper electrode on the first upper electrode onto which the organic silicon source is adsorbed. Related devices and fabrication methods are also discussed.

Abstract: A deep trench capacitor is provided. The deep trench capacitor may include: a deep trench in a substrate, the deep trench including an lower portion having a width that is wider than a width of the rest of the deep trench; a compressive stress layer against the substrate in the lower portion; a metal-insulator-metal (MIM) stack over the compressive stress layer, the MIM stack including a node dielectric between an inner electrode and an outer electrode; and a semiconductor core within the MIM stack.

Abstract: A buried conductive layer is formed underneath a buried insulator layer of a semiconductor-on-insulator (SOI) substrate. A deep isolation trench laterally surrounding a portion of the buried conductive layer is formed, and is filled with at least a dielectric liner to form a deep capacitor trench isolation structure. Contact via structures are formed through the buried insulator layer and a top semiconductor layer and onto the portion of the buried conductive layer, which constitutes a buried conductive conduit. The deep capacitor trench isolation structure may be formed concurrently with at least one deep trench capacitor. A patterned portion of the top semiconductor layer may be employed as an additional conductive conduit for signal transmission. Further, the deep capacitor trench isolation structure may include a conductive portion, which can be electrically biased to control the impedance of the signal path including the buried conductive conduit.