Abstract: An atomic layer deposition apparatus includes: a film-forming container 11 in which a film-forming process is performed; a vertically movable stage 14 provided in the film-forming container 11 and being configured to hold a substrate 100; a stage stopper 17 configured to stop rising of the stage 14 and, when in contact with the stage 14, partitioning a film-forming space S in which the film-forming process is performed and a transporting space in which transport of the substrate 100 is performed; a peripheral stage deposition prevention member 15 covering a peripheral portion of the stage 14; and a stage stopper deposition prevention member 24 provided on the stage stopper 17.

Abstract: A method (200, 300, 500) for producing an electrically conductive pattern on substrate (202, 402), comprising: providing electrically conductive solid particles onto an area of the substrate in a predefined pattern (508), where the pattern (403) comprises a contact area (404B) for connecting to an electronic component and a conductive structure (404A) having at least a portion (414) adjacent to the contact area, heating the conductive particles to a temperature higher than a characteristic melting point of the particles to establish a melt (510), and pressing the melt against the substrate in a nip, the temperature of the contact portion of which being lower than the aforesaid characteristic melting point so as to solidify the particles into essentially electrically continuous layer within the contact area and within the conductive structure in accordance with the pattern (512), wherein the thermal masses of the contact area and the at least adjacent portion of the conductive structure are configured substant

Abstract: Disclosed herein is a method of forming a semiconductor structure. The method includes the steps of: forming a first dielectric layer having a first through hole on a precursor substrate, in which the first through hole passes through the first dielectric layer; filling a sacrificial material in the first through hole; forming a second dielectric layer having a second through hole over the first dielectric layer, in which the second through hole exposes the sacrificial material in the first through hole, and the second through hole has a bottom width less than a top width of the first through hole; removing the sacrificial material after forming the second dielectric layer having the second through hole; forming a barrier layer lining sidewalls of the first and second through holes; and forming a conductive material in the first and second through holes.

Abstract: A semiconductor arrangement is provided. The semiconductor arrangement includes a molding layer and a first capacitor. The first capacitor includes a first vertical conductive structure within the molding layer, a second vertical conductive structure within the molding layer, and a first high-k dielectric material between the first vertical conductive structure and the second vertical conductive structure.

Abstract: A PD unit has a Tr-side Si/SiO2 interface formed to be p-type, and has an embedded PD. The PD, which is n-type, performs photoelectric conversion, and accumulates an electrical charge. A TG transfers the electrical charge accumulated in the PD to an FD. An Amp is connected to the FD. An RST is connected to a Reset Drain (RD), and resets the FD. An FDG is a conversion-efficiency switching switch. An FC is a MOS capacitance (gate electrode) that is connected to the FDG. A SEL selects a pixel that outputs a signal.

Abstract: A capacitor includes a structure including a plurality of openings penetrating from a first surface of the structure to a second surface opposing the first surface; a capacitor layer disposed on the second surface of the structure and in the plurality of the openings and including a dielectric layer, and a first electrode and a second electrode, the dielectric layer interposed between the first electrode and the second electrode; a first connection layer disposed on the first surface of the structure and connected to the first electrode; a second connection layer disposed on the capacitor layer on the second surface and connected to the second electrode of the structure; and first and second terminals disposed on opposite side surfaces of the structure and connected to the first connection layer and the second connection layer, respectively.

Abstract: An electronic apparatus includes a conductive member and a printed circuit board, wherein the printed circuit board includes a printed wiring board having a signal wiring formed thereon, a first semiconductor device configured to output a digital signal to the signal wiring, and a second semiconductor device configured to input the digital signal output from the first semiconductor device via the signal wiring, wherein the signal wiring has a signal wiring pattern formed on a surficial layer located opposite the conductive member in the printed wiring board, and wherein the conductive member has an aperture formed therein and located opposite the signal wiring pattern or includes a flat plate portion and a recessed portion recessed in a direction more away from the printed wiring board than the flat plate portion.

Abstract: A semiconductor memory device and a method of forming the same are provided, with the semiconductor memory device including a substrate, a stacked structure, plural openings, plural flared portions and an electrode layer. The stacked structure is disposed on the substrate and includes alternately stacked oxide material layers and stacked nitride material layers. Each of the openings is disposed in the stacked structure, and each of the flared portions is disposed under each of the openings, in connection with each opening. The electrode layer is disposed on surfaces of each opening and each flared portion.

Abstract: A method of manufacturing a semiconductor device includes forming a first electrode, forming a preliminary dielectric layer on the first electrode, forming a second electrode on the preliminary dielectric layer, and at least partially phase-changing the preliminary dielectric layer to form a dielectric layer. An interfacial energy between the first electrode and the dielectric layer may be less than an interfacial energy between the first electrode and the preliminary dielectric layer.

Abstract: An array of capacitors on an integrated circuit includes a plurality of unit capacitors. Each unit capacitor includes an isolated capacitor node formed in a pillar structure. Each unit capacitor further includes a shared capacitor adjacent to the isolated capacitor node. The shared capacitor node is electrically coupled to shared capacitor nodes of other unit capacitors in the array. Each unit capacitor further includes a shield node coupled to a low impedance node and formed adjacent to the isolated capacitor node to reduce the chance of capacitance forming between conductors to the isolated nodes and the shared nodes thereby preventing unwanted charge from entering the shared nodes and reducing linearity of the array.

Abstract: A semiconductor device includes a first electrode on a substrate, a second electrode on the substrate, a dielectric layer structure between the first electrode and the second electrode, and a crystallization inducing layer between the dielectric layer structure and the first electrode. The dielectric layer structure includes a first dielectric layer including a first dielectric material and a second dielectric layer on the first dielectric layer and including a second dielectric material.

Abstract: The disclosure is directed to semiconductor structures and, more particularly, to Metal-Insulator-Metal (MIM) capacitor structures and methods of manufacture. The method includes: forming at least one gate structure; removing material from the at least one gate structure to form a trench; depositing capacitor material within the trench and at an edge or outside of the trench; and forming a first contact in contact with a first conductive material of the capacitor material and a second contact in contact with a second conductive material of the capacitor material.

Abstract: Provided are MIM capacitor and method of manufacturing the same. The MIM capacitor includes a first electrode, a second electrode, a third electrode, a first insulating layer, a second insulating layer, and a first spacer. The first electrode and the third electrode are electrically connected to each other. The first insulating layer is between the first electrode and the second electrode. The second insulating layer is between the second electrode and the third electrode. The first spacer is located between a sidewall of the first electrode and the first insulating layer.

Abstract: The disclosure is directed to semiconductor structures and, more particularly, to Metal-Insulator-Metal (MIM) capacitor structures and methods of manufacture. The method includes: forming at least one gate structure; removing material from the at least one gate structure to form a trench; depositing capacitor material within the trench and at an edge or outside of the trench; and forming a first contact in contact with a first conductive material of the capacitor material and a second contact in contact with a second conductive material of the capacitor material.

Abstract: A semiconductor device includes a capacitive device, a first conductive via, and a second conductive via. The capacitive device includes a first conductive plate, a first insulating plate, a second conductive plate, a second insulating plate, and a third conductive plate. The first conductive via is electrically coupled to the first conductive plate and the third conductive plate, and the first conductive via penetrated through a first film stack with a first thickness. The second conductive via is electrically coupled to the second conductive plate, and the second conductive via penetrated through a second film stack with a second thickness. The second thickness is substantially equal to the first thickness.

Abstract: Disclosed is a semiconductor package including a semiconductor chip, a first outer capacitor on the semiconductor chip including a first electrode and a second electrode, a second outer capacitor on the semiconductor chip including a first electrode pattern and a second electrode pattern, and a conductive pattern on the semiconductor chip and electrically connected to the first electrode of the first outer capacitor and the first electrode pattern of the second outer capacitor. The second electrode of the first outer capacitor is insulated from the second electrode pattern of the second outer capacitor.

Abstract: A non-volatile storage apparatus comprises a non-volatile memory structure and a plurality of I/O pads in communication with the non-volatile memory structure. The I/O pads include a power I/O pad, a ground I/O pad and data/control I/O pads. The non-volatile storage apparatus further comprises one or more capacitors connected to the power I/O pad. The one or more capacitors are positioned in one or more metal interconnect layers below the I/O pads.

Abstract: The present invention discloses a method of manufacturing a capacitor, which includes the steps of forming a capacitor recess in a sacrificial layer, wherein the sidewall of capacitor recess has a wave profile, forming a bottom electrode layer on the sidewall of capacitor recess, filling up the capacitor recess with a supporting layer, removing the sacrificial layer to forma capacitor pillar made up by the bottom electrode layer and the supporting layer, forming a capacitor dielectric layer on the capacitor pillar, and forming a top electrode layer on the capacitor dielectric layer.

Abstract: Aspects of the present disclosure are directed to systems and methods to reduce inductance on an integrated circuit package of a memory sub-system. A memory sub-system is also hereinafter referred to as a “memory device.” An example of a memory sub-system is a storage system, such as a SSD, and can be embodied as an integrated circuit package, including but not limited to a pin grid array (PGA), and ball grid array (BGA).

Abstract: Dielectric patterns may be additionally disposed in margin portions, and thicknesses of the dielectric patterns may be controlled to improve the reliability of a capacitor component.

Abstract: A capacitor structure includes a semiconductor substrate, a first vertical diffusion plate disposed in the semiconductor substrate, a first shallow trench isolation (STI) structure disposed in the semiconductor substrate and surrounding the first vertical diffusion plate, and a second vertical diffusion plate disposed in the semiconductor substrate and surrounding the first STI structure. The first vertical diffusion plate further includes a first lower portion that is part of the semiconductor substrate. The first lower portion is surrounded and electrically isolated by a first wafer-backside trench isolation structure. The first wafer-backside trench isolation structure is in direct contact with a bottom of the first STI structure.

Abstract: Conformal hermetic dielectric films suitable as dielectric diffusion barriers over 3D topography. In embodiments, the dielectric diffusion barrier includes a dielectric layer, such as a metal oxide, which can be deposited by atomic layer deposition (ALD) techniques with a conformality and density greater than can be achieved in a conventional silicon dioxide-based film deposited by a PECVD process for a thinner contiguous hermetic diffusion barrier. In further embodiments, the diffusion barrier is a multi-layered film including a high-k dielectric layer and a low-k or intermediate-k dielectric layer (e.g., a bi-layer) to reduce the dielectric constant of the diffusion barrier. In other embodiments a silicate of a high-k dielectric layer (e.g., a metal silicate) is formed to lower the k-value of the diffusion barrier by adjusting the silicon content of the silicate while maintaining high film conformality and density.

Abstract: A capacitor structure includes an insulative layer, a first electrode over the insulative layer, a dielectric layer over the first electrode, and a second electrode over the dielectric layer. The first electrode includes a first portion extending along a lateral direction of the insulative layer and a second portion connected to the first portion and extending along a depth direction of the insulative layer. The dielectric layer is substantially conformal with respect to a profile of the first electrode. A semiconductor structure thereof and a method for forming the same are also provided.

Abstract: A semiconductor device is provided. The semiconductor device includes a substrate which includes a cell region including first and second regions, and a peri region more adjacent to the second region than adjacent to the first region, first and second lower electrodes disposed in the first and second regions, respectively, first and second lower support patterns disposed on outer walls of the first and second lower electrodes, respectively, an upper support pattern disposed on outer walls of the first and second lower electrodes, and being on and spaced apart from the first and second lower support patterns, a dielectric layer disposed on surfaces of the first and second lower electrodes, the first and second lower support patterns, and the upper support pattern, and an upper electrode disposed on a surface of the dielectric layer, wherein thickness of the first lower support pattern is smaller than thickness of the second lower support pattern.

Abstract: An IC device carrier includes organic substrate layers and wiring line layers therein. To reduce stain of the organic substrate layers and to provide decoupling capacitance, one or more decoupling capacitor stiffeners (DCS) are applied to the top side metallization (TSM) surface of the IC device carrier. The DCS(s) reduce the amount of curvature of the IC device carrier and reduce the strain seen by the organic substrate layers, thereby mitigating the risk for cracks forming and expanding or other damage within the carrier. The DCS(s) also include two or more capacitor plates and provides capacitance to electrically decouple electrical subsystems of the system of which the DCS is apart.

Abstract: According to one embodiment, a semiconductor memory device includes a first memory chip, a circuit chip, and an external connection electrode on a surface of the first memory chip. The first memory chip comprises first conductors stacked via an insulator, and a first pillar passing the first conductors. The circuit chip comprises a substrate, a control circuit, and a second conductor connected to the control circuit, the circuit chip being attached to the first memory chip. The external connection electrode comprises a portion extending from a side of the surface of the first memory chip through the first memory chip and connected to the second conductor. Part of the first conductors is between the external connection electrode and the substrate.

Abstract: A semiconductor structure and a method of fabricating thereof are provided. The semiconductor structure includes a substrate and a capacitor structure. The substrate has a first blind hole and a trench. The first blind hole communicates with the trench. The first blind hole has a first depth, and the trench has a second depth smaller than the first depth. The capacitor structure includes a first inner conductor, a first inner insulator, and an outer conductor. The first inner conductor is in the first blind hole. The first inner insulator surrounds the first inner conductor. The outer conductor has a first portion surrounding the first inner insulator and an extending portion extending from the first portion. The first portion is in the first blind hole, and the extending portion is in the trench. The first inner conductor is separated from the outer conductor by the first inner insulator.

Abstract: A wafer level package which includes an IC chip; a rewiring layer on the IC chip; and a capacitor embedded in the rewiring layer.

Abstract: A method for fabricating a semiconductor device includes the following steps. First, a contact structure is formed in the insulating layer. Preferably, the contact structure includes a bottom portion in part of the insulating layer and a top portion on part of the bottom portion and extending to cover part of the insulating layer. Next, a dielectric layer is formed on the bottom portion and the top portion, part of the dielectric layer is removed to form a first opening exposing part of the top portion and part of the bottom portion, and a capacitor is formed in the first opening and contacting the pad portion and the contact portion directly.

Abstract: A package includes a substrate having an electronic component flip chip mounted thereto by flip chip bumps. The electronic component includes an active surface and an inactive surface. Electrically conductive columns (TSV) extend through the electronic component between the active surface and the inactive surface. A RDL structure is coupled to the inactive surface, the RDL structure redistributing the pattern of the electrically conductive columns at the inactive surface to a pattern of inactive surface RDL lands. The inactive surface RDL lands are exposed through via apertures of a package body. By using the inactive surface of the electronic component to distribute the inactive surface RDL lands, the allowable size of the electronic component is maximized.

Abstract: Devices and methods are provided for fabricating a metal-insulator-metal capacitor within an interconnect structure (e.g., back-end-of-line interconnect structure) to provide capacitive decoupling between positive and negative power supply voltage lines of a power distribution network. Various via contact configurations including interlevel via contacts and truncated via contacts are utilized to connect the metal-insulator-metal capacitor electrodes to power supply voltage lines of the power distribution network to provide an array of high-density, low resistance via contact connections at various locations across the capacitor electrodes to reduce the resistance of the metal-insulator-metal capacitor and, thus, enhance the transient response time and increase the cutoff frequency of the metal-insulator-metal capacitor.

Abstract: A method of forming an apparatus comprises forming a first metal nitride material over an upper surface of a conductive material within an opening extending through at least one dielectric material through a non-conformal deposition process. A second metal nitride material is formed over an upper surface of the first metal nitride material and side surfaces of the at least one dielectric material partially defining boundaries of the opening through a conformal deposition process. A conductive structure is formed over surfaces of the second metal nitride material within the opening. Apparatuses and electronic systems are also described.

Abstract: A memory stack comprises at least two memory components. The memory components have a first data link interface and are to transmit signals on a data link coupled to the first data link interface at a first voltage level. A buffer component has a second data link interface coupled to the data link. The buffer component is to receive signals on the second data link interface at the first voltage level. A level shifting latch produces a second voltage level in response to receiving the signals at the second data link interface, where the second voltage level is higher than the first voltage level.

Abstract: A method for fabricating a capacitor includes: forming a bottom electrode; forming a dielectric layer on the bottom electrode; forming a metal oxide layer including a metal having a high electronegativity on the dielectric layer; forming a sacrificial layer on the metal oxide layer to reduce the metal oxide layer to a metal layer; and forming a top electrode on the sacrificial layer to convert the reduced metal layer into a high work function interface layer.

Abstract: According to one embodiment, there is provided a semiconductor device including a stacked body, a semiconductor columnar member, an insulating film, and a structure. The stacked body is disposed above a semiconductor substrate. In the stacked body, a conductive film and an insulating layer are alternately disposed in a stacking direction. The semiconductor columnar member penetrates the stacked body in the stacking direction. The insulating film surrounds the semiconductor columnar member and penetrates the stacked body in the stacking direction. The structure is disposed in a peripheral circuit region on the semiconductor substrate. The peripheral circuit region is a region including a plurality of circuit blocks. The structure has a plate-shaped portion extending at least between the plurality of circuit blocks.

Abstract: A memory cell and method for utilizing the memory cell are described. The memory cell includes at least one ferroelectric transistor (FE-transistor) and at least one selection transistor coupled with the FE-transistor. An FE-transistor includes a transistor and a ferroelectric capacitor for storing data. The ferroelectric capacitor includes ferroelectric material(s). In some aspects, the memory cell consists of a FE-transistor and a selection transistor. In some aspects, the transistor of the FE-transistor includes a source, a drain and a gate coupled with the ferroelectric capacitor. In this aspect, the selection transistor includes a selection transistor source, a selection transistor drain and a selection transistor gate. In this aspect, a write port of the memory cell is the selection transistor source or the selection transistor drain. The other of the selection transistor source and drain is coupled to the ferroelectric capacitor.

Abstract: A semiconductor device including: a semiconductor substrate; at least one circuit block provided on a main surface of the semiconductor substrate and having a predetermined function; a wiring layer including plural metal layers that connect the circuit block; and plural capacitors including a first capacitor connected to the circuit block and that uses the plurality of metal layers, and a second capacitor that uses an active area disposed within the main surface of the semiconductor substrate, wherein at least one of the first capacitor and at least one of the second capacitor are stacked in a stacking direction of layers of the semiconductor.

Abstract: A semiconductor memory device includes a semiconductor substrate, a first support layer, a first electrode, a capacitor dielectric layer, and a second electrode. The first support layer is disposed on the semiconductor substrate. The first electrode is disposed on the semiconductor substrate and penetrates the first support layer. The capacitor dielectric layer is disposed on the first electrode. The second electrode is disposed on the semiconductor substrate, and at least a part of the capacitor dielectric layer is disposed between the first electrode and the second electrode. The first support layer includes a carbon doped nitride layer, and a carbon concentration of a bottom portion of the first support layer is higher than a carbon concentration of a top portion of the first support layer.

Abstract: The present disclosure relates to a semiconductor device and a manufacturing method, and more particularly to a semiconductor interposer device. The semiconductor interposer device includes a substrate and a first metallization layer formed on the substrate. A first dielectric layer is formed on the first metallization layer and a second metallization layer is formed on the substrate. A first conducting line is formed in the first metallization layer and second and third conducting lines are formed in the second metallization layer. A metal-insulator-metal (MIM) capacitor is formed in the first dielectric layer and over the first conducting line.

Abstract: A capacitor cell for a semiconductor device, wherein the capacitor cell comprises: a capacitor having a first node and a second node; a first electrode structure, comprising a first contact point and a second contact point, wherein the first contact point and the second contact point are electrically connected to the first node of said capacitor and located at two different edges of the capacitor cell; and a second electrode structure, comprising a third contact point and a fourth contact point, wherein the third contact point and the fourth contact point are electrically connected to the second node of said capacitor and located at said two different edges of the capacitor cell.

Abstract: A method includes bonding a first device die and a second device die to a substrate, and filling a gap between the first device die and the second device die with a gap-filling material. A top portion of the gap-filling material covers the first device die and the second device die. Vias are formed to penetrate through the top portion of the gap-filling material. The vias are electrically coupled to the first device die and the second device die. The method further includes forming redistribution lines over the gap-filling material using damascene processes, and forming electrical connectors over and electrically coupling to the redistribution lines.

Abstract: A microwave IC waveguide device module includes: a substrate having a throughhole; a microwave IC provided on or above the first face of the substrate; a waveguide member provided below the second face of the substrate opposite from the first face, the waveguide member having an electrically conductive waveguide face which opposes the throughhole; an electrically conductive member covering at least a portion of the second face that extends in a manner of following along the waveguide face; and an artificial magnetic conductor on both sides of the waveguide member. The substrate includes an inner-wall electrically conductive portion covering an inner wall of the throughhole and being electrically connected with the electrically conductive member. The signal terminal and the ground terminal of the IC are electrically connected respectively with two portions of the inner-wall electrically conductive portion opposing each other with the throughhole interposed therebetween.

Abstract: A semiconductor memory device includes a substrate having an active region, word lines extending across the active region, a bit line on the active region between the word lines, a bit line node contact between the bit line and the active region, and a storage node contact on an end portion of the active region, wherein one or more of the bit line node contact or the storage node contact include silicon germanium.

Abstract: A sacrificial interposer test structure including a release layer, a dummy layer on the release layer, one or more conductive pads embedded in the dummy layer, wherein each of the one or more conductive pads has an exposed surface, and a tie layer on the dummy layer and on each exposed surface of the one or more conductive pads.

Abstract: A power integrated module, including at least one first bridge formed in a chip, wherein the first bridge includes: a first upper bridge switch, formed by a plurality of first sub switches formed in the chip connected in parallel, and including a first, a second and a control end; a first lower bridge switch, formed by a plurality of second sub switches formed in the chip connected in parallel, and including a first, a second and a control end; a first electrode, connected to the first end of the first upper bridge switch; a second electrode, connected to the second end of the first lower bridge switch; and a third electrode, connected to the second end of the first upper bridge switch and the first end of the first lower bridge switch, wherein the first, the second and the third electrode are bar-type electrodes arranged side by side.

Abstract: An integrated trench capacitor and method for making the trench capacitor is disclosed. The method includes forming a trench in a silicon layer, forming a first dielectric on the exposed surface of the trench, performing an anisotropic etch of the first dielectric to expose silicon at the bottom of the trench, implanting a dopant into exposed silicon at the bottom of the trench, forming a first polysilicon layer over the first dielectric, forming a second dielectric over the first polysilicon layer, and forming a second polysilicon layer over the second dielectric to fill the trench.

Abstract: Certain aspects of the present disclosure provide an integrated circuit (IC) that includes at least one of a via-based vertical capacitor structure or a via-based vertical resistor structure. The IC includes a substrate oriented in a horizontal plane, electrically conductive layers disposed above the substrate, and electrically insulative layers disposed above the substrate and interposed between the plurality of electrically conductive layers. At least one of the vertical capacitor structure or the vertical resistor structure is disposed in the electrically conductive layers and the electrically insulative layers.

Abstract: A coreless package substrate with dual side solder resist layers is disclosed. The coreless package substrate has a top side and a bottom side opposite of the top side and includes a single build-up structure formed of at least one insulating layer, at least one via, and at least one conductive layer. The coreless package substrate also includes a bottom plurality of contact pads on the bottom side, and a top plurality of contact pads on the top side. A bottom solder resist layer is on the bottom side, and a top solder resist layer is on the top side. The concept of dual side solder resist is extended to packages with interconnect bridge with C4 interconnection pitch over a wide range.

Abstract: A method includes calculating a maximum value of an on-die decoupling capacitor for an integrated circuit (IC) design based on a switching current defined by a number of simultaneously switching bits for the IC design. The method also includes calculating a total decoupling capacitance value offered by spacer cells in the IC design. The method further includes determining an optimal on-die decoupling capacitance value for the IC design as a function of the maximum value of the on-die decoupling capacitor and the total decoupling capacitance value offered by the spacer cells.

Abstract: The present disclosure, in some embodiments, relates to an integrated chip. The integrated chip includes a lower interconnect layer disposed within a first inter-level dielectric (ILD) layer over a substrate. A plurality of MIM (metal-insulator-metal) structures are disposed within a second inter-level dielectric (ILD) layer over the lower interconnect layer. An upper interconnect layer is coupled to the plurality of MIM structures at first locations that are directly over second locations at which the lower interconnect layer is coupled to the plurality of MIM structures. One or both of the lower interconnect layer and the upper interconnect layer are comprised within a conductive path that electrically couples the plurality of MIM structures in a series connection.