Abstract: In a DRAM having a structure in which a storage node electrode is formed via an insulator film in a trench formed in a memory cell region to thereby form a capacitor, and in which the storage node electrode is connected in the source/drain regions of a MOSFET through a storage node contact formed in a part of the insulator film, the trench is disposed so as to deviate widthwise in a channel region of the MOSFET, so that the distance between adjacent element regions is reduced without causing misalignment of masks used in the formation of the storage node contact, thereby to provide a miniaturized high-reliability DRAM. In addition, the storage node contact and the trench can be formed in large size.

Abstract: A semiconductor memory device according to the present invention comprises a memory cell having one transistor and one stacked capacitor. The stacked capacitor is stacked on the surface of a semiconductor substrate. Further, the stacked capacitor has a structure extending on a gate electrode and a word line through an insulating layer. A lower electrode layer of the capacitor has various concave/convex shapes, i.e. step portions and projecting portions formed on the surface thereof. These shapes are made by employing various etching processes. The lower electrode layer has such various concave/convex shapes formed thereon, so that a surface area and capacitance of the capacitor can be increased.

Abstract: In a semiconductor device including charge storage capacitors, each of which includes a patterned electrode having electrode side and top surfaces, a dielectric film on the side and top surfaces, and a covering electrode on the dielectric film, the patterned electrode is composed of a lower silicon layer having layer side and top surfaces and an upper silicon layer lying on the layer side and top surfaces and having the electrode side and top surfaces. The dielectric film may be in direct contact with the electrode side and top surfaces. In this event, the lower silicon layer is preferably doped to a lower concentration between 10.sup.15 and 10.sup.18 atoms per cubic centimeter and the upper silicon layer, to a higher concentration between 10.sup.18 and 10.sup.20 atoms per cubic centimeter. Alternatively, a barrier metal film may be interposed between the dielectric film and the electrode side and top surfaces.

Abstract: A semiconductor memory cell and device having a tubular formed storage electrode of a capacitor through which a bit line passes. The source, gate and drain of a switching transistor are arranged in a direction parallel to a longitudinal axis of the tubular storage electrode. An active region also is arranged in a parallel or superposing direction relative to the bit line and in a perpendicular direction relative to the word line. A manufacturing method thereof includes forming a switching transistor, forming a part of the capacitor storage electrode connected with the drain of the switching transistor, forming an oxide film side wall, forming a bit line in parallel to a longitudinal axis of the active region, forming a capacitor storage electrode of tubular form, covering the surface of the capacitor storage electrode with a capacitor dielectric film, and forming a plate electrode of the capacitor thereon.

Abstract: A silicon layer having an increased surface area by providing a highly granulated surface area, and a method for manufacturing the same are disclosed. The highly granulated surface of the silicon layer of the present invention provides greater surface area relative to the surface area of the present silicon layer where both layers have the same (length and width) dimensions. The present invention provides a silicon layer for a charge storage electrode having an increased surface area by forming the surface of the silicon layer into a highly granulated topography, which is used as a charge storage electrode, to enable the capacitance of the stacked capacitor to be increased relative to a prior art stacked capacitor having the same area of the silicon layer but with less granulated topography, and provides a process of making a highly granulated silicon layer having an increased surface area relative to the existing methods of making a silicon layer and its associated surface area.

Abstract: An improved mask and method of forming a deep and width trench in a substrate and the resulting structure is disclosed. A substrate material such as silicon has deposited thereon a first layer of sacrificial material as a first component of an etch mask, the sacrificial material being a material such as polysilicon that is either etched by or absorbs the same ions which reactively ion etch the substrate. A second layer of material, which resists reactive ion etching, such as silicon dioxide, is deposited over the first layer of material as a second component of the etch mask. The silicon dioxide is patterned in the form of the trench to be formed in the substrate. The layer polysilicon material is then reactive ion etched and the reactive ion etching continued to form a trench in the silicon substrate. The polysilicon acts as a sacrificial material being etched by any ions that are reflected from the silicon dioxide or are directed at an angle such that they strike the layer of polysilicon material.

Abstract: A semiconductor memory device according to the present invention comprises a memory cell having one transistor and one stacked capacitor. The stacked capacitor is stacked on the surface of a semiconductor substrate. Further, the stacked capacitor has a structure extending on a gate electrode and a word line through an insulating layer. A lower electrode layer of the capacitor has various concave/convex shapes, i.e. step portions and projecting portions formed on the surface thereof. These shapes are made by employing various etching processes. The lower electrode layer has such various concave/convex shapes formed thereon, so that a surface area and capacitance of the capacitor can be increased.

Abstract: A MOS capacitor, with the polysilicon gate level as one plate, the gate oxide as the insulator, and the underlying semiconductor tub region as the other plate, is used to increase electrostatic discharge (ESD) protection. In an illustrative embodiment, wherein the substrate is n-type and the tub is p-type, the polysilicon level is connected to the negative power supply voltage conductor (V.sub.SS), and the underlying semiconductor region is connected to the positive power supply conductor (V.sub.DD). Since the tub region is p-type, an accumulation-type capacitor is formed. Surprisingly, the thin gate oxide is sufficient to withstand the high ESD voltages, with the protection increasing in one design from less than 1000 volts without the capacitor to 2000 volts with the capacitor.

Abstract: A method including covering the area to be laser trimmed with a first insulative layer having a thickness sufficiently thin that a layer can trim the area through the first insulative layer. An etch stop is formed on the first insulative layer over the area to be trimmed and covered with a second insulative layer. A portion of the second insulative layer is etched to expose the etch stop and a portion of the etch stop is then removed to expose a portion of the first insulative layer and laser trimming is conducted through the exposed first insulative layer. The etch stop is part of a first level of interconnects made of the same material and simultaneously with the etch stop. The area to be trimmed is part of a second level of contacts that interconnect another second material.

Abstract: A semiconductor device having a built-in capacitor comprises a substrate, an internal electrode provided on a top side of the substrate, a dielectric film provided so as to cover the internal electrode for establishing a predetermined capacitance, a surface electrode provided on the dielectric film so as to make a contact therewith, a plurality of through holes formed in the substrate in correspondence to the internal electrode so as to extend from a bottom side to the top side, and a back-side electrode provided on the bottom side of the substrate including the through holes so as to make a contact with the internal electrode through the through holes.

Abstract: A method of forming an electrically conductive polysilicon capacitor plate on a semiconductor substrate includes: a) providing a first layer of conductively doped polysilicon atop a semiconductor substrate to a first selected thickness; b) providing a thin layer of oxide atop the first polysilicon layer to a thickness of from about 2 Angstroms to about 30 Angstroms, the thin oxide layer having an outwardly exposed surface; and c) providing a second layer of conductively doped polysilicon having an outer exposed surface over the outwardly exposed thin oxide surface, the first polysilicon layer being electrically conductive with the second polysilicon layer through the thin layer of oxide, the second polysilicon layer having a second thickness from about 500 Angstroms to about 700 Angstroms, the thin oxide layer reducing silicon atom mobility during polysilicon deposition to induce roughness into the outer exposed polysilicon surface.