Abstract: A high surface area capacitor comprising a double metal layer of an electrode metal and a barrier material deposited on hemispherical grain (HSG) silicon and a high dielectric constant (HDC) material deposited over the double metal layer. An upper cell plate electrode is deposited over the HDC material. The double metal layer preferably comprises one noble metal for the electrode metal and an oxidizable metal for the barrier material. The noble metal alone would normally allow oxygen to diffuse into and oxidize any adhesion layer and/or undesirably oxidize any silicon-containing material during the deposition of the HDC material. The barrier metal is used to form a conducting oxide layer or a conducting layer which stops the oxygen diffusion. The HSG polysilicon provides a surface roughness that boosts cell capacitance. The HDC material is also used to boost cell capacitance.

Abstract: Capacitance for MIM capacitors is increased by connecting another interdigitated pattern at the poly level in parallel with overlying patterns at the metal levels. The poly layout is optimized to maximize intralevel capacitive coupling through sidewall nitride.

Abstract: In a semiconductor chip, conductive tracks run in a rewiring layer from contact pads to contact elevations. The contact pads are formed as vias. The conductive tracks are constructed in sections as bottom electrodes of trimming capacitors. The top electrode of the trimming capacitors is formed by a metal plane of the rewiring layer.

Abstract: A method of utilizing passive circuit components in an integrated circuit comprising the steps of providing a plurality of integrated capacitive elements and a plurality of integrated inductive elements interconnected to form an electrical circuit wherein each inductive element has a width and creates a circumferential magnetic field. Each integrated inductive element is oriented such that the circumferential magnetic field is parallel to the plane of each adjacent integrated capacitive element and parallel to the width of the integrated inductive element so that the resistance of the electrical circuit is decreased and the quality factor is increased.

Abstract: A capacitor comprises a first conducting film 12 formed on a substrate 10, a first dielectric film 14 formed on the first conducting film, a second conducting film 18 formed on the first dielectric film, a second dielectric film 22 formed above the second conducting film, covering the edge of the second conducting film, a third conducting film 34 formed above the second dielectric film, covering a part of the second dielectric film covering the edge of the second conducting film. The capacitor further comprises an insulation film 28 covering the edge of the second conducing film or the part of the second dielectric film. An effective thickness of the insulation film between the second conducting film and the third conducing film in the region near the edge of the second conducting film can be increased, whereby concentration of electric fields in the region near the edge of the second conducting film. Consequently, the capacitor can have large capacitance without lowering voltage resistance.

Abstract: A semiconductor device includes a silicon substrate 10 having a trench isolation region 24. A plurality of dummy convex regions 32 are formed in the trench isolation region 24. The trench isolation region 24 defines a row direction and a column direction. Also, the trench isolation region 24 define first virtual linear lines L1 that extend in a direction traversing the row direction and second virtual linear lines L2 that extend in a direction traversing the column direction. The first virtual linear lines L1 and the row direction define an angle of 2-40 degree, and the second virtual linear lines L2 and the column direction define an angle of 2-40 degree. The dummy convex regions 32 are disposed on the first virtual linear lines L1 and the second virtual linear lines L2.

Abstract: A mesh capacitor structure in an integrated circuit can be made up by arranging at least a unit capacitor module in a coupling way, thereby enhancing its total capacitance by coupling capacitance. The unit capacitor module includes a plurality of first conductive strips extending in parallel with each other in a lateral direction and a plurality of second conductive strips formed over the plurality of first conductive strips and extending in parallel with each other in a longitudinal direction. In addition, a plurality of conductive plugs are formed at intersections between the odd-numbered second conductive strips and the odd-numbered or even-numbered first conductive strips, thereby forming a first electrode, and between the even-numbered second conductive strips and the even-numbered or odd-numbered first conductive strips, thereby forming a second electrode with an electrical polarity opposite to that of the first electrode.

Abstract: By using a solid solution of tantalum pentoxide and niobium pentoxide as a dielectric film installed between upper electrode and lower electrode in a capacitor which is used in a semiconductor device, the capacitor structure can be simplified to improve reliability of the semiconductor device while reducing the production cost thereof.

Abstract: An integrated circuit chip is provided having both a conventional DRAM vertical transfer device and an integrated vertical storage capacitor or anti-fuse that can be accessed directly without having to turn on a transfer gate. The mechanism for accessing the integrated capacitor or anti-fuse directly can be a modified doping profile within the vertical cell that provides a low resistance punch-through FET. Alternatively, the mechanism can be a pair of overlapping or nearly overlapping diffusions within the vertical cell.

Abstract: The present invention provides an encapsulated 3-D conductive pillar and a method of formation thereof. Significant economic savings are achieved by filling a substantial portion of the volume of the pillar with a lesser expensive conductive material. Additionally, the encapsulated 3-D conductor pillar forms a suitable unreactive, oxygen-stable electrode for use with high-dielectric constant (HDC) materials as the encapsulating barrier layer metal provides a stable conductive interface between the HDC material and the encapsulated conductive material.

Abstract: A capacitor array of a semiconductor device including a plurality of capacitors is provided. The capacitor array includes a plurality of lower electrodes, which are formed over a semiconductor substrate. A dielectric layer formed over the lower electrodes, and an upper electrode formed over the dielectric layer. The plurality of lower electrodes are insulated from each other either by an insulating layer having pores of a low dielectric constant, or by an air gap.

Abstract: A semiconductor memory incorporates cylinder-type stacked capacitors. Each capacitor has a lower electrode and an upper electrode facing each other via a dielectric film. The lower electrode of each capacitor is supported by a beam-like insulator at a side portion of the electrode, the side portion being apart from a lower edge of the lower electrode.

Abstract: Inductor losses to a semiconducting substrate are eliminated in an IC structure by etching a well into the substrate down to the insulating layer coating the substrate and fabricating a grounded Faraday shield in the shape of elongated segments in the bottom of the well. The well lies directly below the inductor and is optionally filled with cured low-k organic dielectric or air.

Abstract: The present invention is equipped with a ferroelectric film having concave and convex patterns formed on both sides thereof corresponding to respective electrodes of a plurality of capacitors. A first substrate has first electrodes of the plurality of capacitors formed on one surface thereof. A second substrate has second electrodes of the plurality of capacitors formed on the other surface thereof. First and second anisotropic conduction films are provided between one surface of the ferroelectric film and the first substrate and between the other surface of the ferroelectric film and the second electrode film, respectively, to thereby establish conduction between the convex sections of the ferroelectric film of the capacitors and the electrodes of the capacitors. Since the multiple capacitors can be formed without conducting an etching (lithography) process, damages that may be inflicted on the ferroelectric film when the ferroelectric capacitors are formed can be reduced.

Abstract: Methods of forming a uniform cell nitride dielectric layer over varying substrate materials such as an insulation material and a conductive or semiconductive material, methods of forming capacitors having a uniform nitride dielectric layer deposited onto varying substrate materials such as an insulation layer and overlying conductive or semiconductive electrode, and capacitors formed from such methods are provided. In one embodiment of forming a uniform cell nitride layer in a capacitor construction, a surface-modifying agent is implanted into exposed surfaces of an insulation layer of a capacitor container by low angle implantation to alter the surface properties of the insulation layer for enhanced nucleation of the depositing cell nitride material, preferably while rotating the substrate for adequate implantation of the modifying substance along the top corner portion of the container.

Abstract: The effective area of a MIM capacitor is increased by forming a lower electrode that includes hemispherical grain lumps. The hemispherical grain lumps are formed by heat-treating a metal layer in an oxygen and/or nitrogen atmosphere, thus oxidizing the surface of the metal layer or growing the crystal grains of the metal layer. The MIM capacitor may be formed of Pt, Ru, Rh, Os, Ir, or Pd, and the hemispherical grain lumps may be formed of Pt, Ru, Rh, Os, Ir, or Pd. Since the metal layer is primarily heat-treated during the formation of the lower electrode, it is possible to reduce the degree to which the surface morphology of the lower electrode is rapidly changed due to a heat treatment subsequent to forming a dielectric layer and an upper electrode.

Abstract: The present invention relates to a thin film capacitor device having a copper wiring layer, a dielectric layer, and a barrier layer interposed between the wiring layer and the dielectric layer. The barrier layer has the function of preventing diffusion of copper of the wiring layer. The thin film capacitor device may also include an insulating substrate, a planarizing layer, an adhesion layer, and an intermediate layer. The present invention may also relate to a printed circuit substrate having the described thin film capacitor device built therein as a capacitor.

Abstract: An inductor has a spiral aluminum track deposited on an oxide layer over a silicon substrate. The substrate is etched away to form a trench, which extends around beneath the track and provides an air gap having a low dielectric constant. The oxide layer has an inner region within the track, an outer region outside the track and a bridging region extending between the other regions. The bridging region is comprised of intact bridges and gaps therebetween, which are open to the trench and through which an etchant has access to the silicon substrate to form the trench by etching.

Abstract: An integrated circuit is fabricated with a layer of polysilicon located on top of shallow trench regions. The polysilicon is patterned so that the trench features are not exposed during an etching operation performed on the polysilicon layer. The process of fabricating transistor gate electrodes, therefore, is improved by reducing etch byproducts contributed by the shallow trench region features.

Abstract: A means for fabrication of solenoidal inductors integrated in a semiconductor chip is provided. The solenoidal coil is partially embedded in a deep well etched into the chip substrate. The non-embedded part of the coil is fabricated as part of the BEOL metallization layers. This allows for a large cross-sectional area of the solenoid turns, thus reducing the turn-to-turn capacitive coupling. Because the solenoidal coils of this invention have a large diameter cross-section, the coil can be made with a large inductance value and yet occupy a small area of the chip. The fabrication process includes etching of a deep cavity in the substrate after all the FEOL steps are completed; lining said cavity with a dielectric followed by fabrication of the part of the coil that will be embedded by deposition of a conductive material metal through a mask; deposition of dielectric and planarization of same by CMP.

Abstract: A contact structure in a semiconductor device and a method of forming the same are provided. The contact structure includes a lower interconnection having a capacitor upper electrode of memory cells; an interlayer dielectric layer formed on the lower interconnection and having a contact hole that exposes a portion of the lower interconnection; and an upper interconnection formed on the interlayer dielectric layer and electrically connected to the lower interconnection through the contact hole. The lower portion of the lower interconnection has a larger width than the bottom of the contact hole and extends downward or below the bottom of the contact hole so that the lower interconnection has a T-shape in cross-section. With these structures, the lower interconnection can be prevented from being pierced when the contact holes are formed. Consequently, stable and uniform contact resistance can be obtained.

Abstract: Apparatus and method for providing high dielectric constant decoupling capacitors for semiconductor structures. The high dielectric constant decoupling capacitor can be fabricated by depositing high dielectric constant material between adjacent conductors on the same level, between conductors in successive levels, or both, to thereby provide very large capacitance value without any area or reliability penalty.

Abstract: Implemented are a semiconductor device comprising a trench type capacitor having such a structure that a soft error tolerance is excellent, a contact resistance between an electrode and a metal wiring has a small value, a fringe capacitance on an end is reduced and area penalty is not increased, and a method for manufacturing the semiconductor device. The trench type capacitor is formed to have a bottom face in a BOX layer (2) without penetrating the BOX layer (2). Moreover, an end of the capacitor, that is, each of ends of a first electrode (6), a dielectric film (7) and a second electrode (8) is flattened. An insulating film (16) and a side wall (9) are formed to cover the ends of the first electrode (6), the dielectric film (7) and the second electrode (8). Furthermore, a contact plug (10) for connecting the second electrode (8) to a metal wiring (14a) provided as an upper layer is buried in a region surrounded by the side wall (9).

Abstract: An integrated circuit having capacitive elements for smoothing a supply voltage is described. In this case, at least one additional metal electrode, which is configured as a high frequency-optimized capacitance and is distinguished by an extremely low sheet resistance, is connected in parallel with the MOS capacitances. By connecting the areally highly effective MOS capacitance, which, however, is connected with a somewhat higher impedance, in parallel with areally less effective metal capacitances, which, however, are connected to the supply voltage in a very low-impedance manner, it is possible to obtain broadband buffering and thus decoupling of high-frequency interference signals. Very high-frequency interference components are attenuated on the chip and do not pass into the system surrounding the integrated circuit.

Abstract: Methods of forming capacitors and resultant capacitor structures are described. In one embodiment, a capacitor storage node layer is formed over a substrate and has an uppermost rim defining an opening into an interior volume. At least a portion of the rim is capped by forming a material which is different from the capacitor storage node layer over the rim portion. After the rim is capped, a capacitor dielectric region and a cell electrode layer are formed over the storage node layer. In another embodiment, a capacitor storage node layer is formed within a container which is received within an insulative material. A capacitor storage node layer is formed within the container and has an outer surface. A layer of material is formed within less than the entire capacitor container and covers less than the entire capacitor storage node layer outer surface. The layer of material comprises a material which is different from the insulative material within which the capacitor container is formed.

Abstract: Disclosed herein is a method of manufacturing a semiconductor capacitor. In the semiconductor capacitor manufacturing method, an amorphous film composed of non-doped silicon is formed. The amorphous film is changed to a lower film having projections and depressions defined in the surface thereof by heat treatment. An amorphous film composed of impurity-doped silicon is formed over the surface of the lower film. Further, the amorphous film composed of the impurity-doped silicon is changed to an upper film having projections and depressions defined in the surface thereof by heat treatment with the projections and depressions provided over the surface of the lower film as a basis. The semiconductor capacitor is equipped with an electrode having the lower film and the upper film.

Abstract: There are contained the steps of forming an undoped or low impurity concentration amorphous silicon film to project from an upper surface of a first insulating film, introducing selectively impurity into an uppermost surface of the amorphous silicon film to form the uppermost surface of the amorphous silicon film as a high concentration impurity region, forming hemispherical grained silicon on the uppermost surface of the amorphous silicon film at a first density and on a side surface at a second density higher than the first density by exposing the amorphous silicon film to a silicon compound gas and then annealing the amorphous silicon film in a low pressure atmosphere, and introducing the impurity into the hemispherical grained silicon and the amorphous silicon film. Accordingly, a semiconductor device having a capacitor, in which a cylindrical storage electrode from an upper surface of which silicon projections are difficult to come off is formed, can be provided.

Abstract: A micro electro-mechanical systems device having variable capacitance is controllable over the full dynamic range and not subject to the “snap effect” common in the prior art. The device features an electrostatic driver (120) having a driver capacitor of fixed capacitance (121) in series with a second driver capacitor of variable capacitance (126). A MEMS variable capacitor (130) is controlled by applying an actuation voltage potential to the electrostatic driver (120). The electrostatic driver (120) and MEMS variable capacitor (130) are integrated in a single, monolithic device.

Abstract: Capacitance for MIM capacitors is increased by connecting another interdigitated pattern at the poly level in parallel with overlying patterns at the metal levels. The poly layout is optimized to maximize intralevel capacitive coupling through sidewall nitride.

Abstract: In a semiconductor memory having a number of stacked capacitor memory cells each having a cylindrical lower electrode which is in the form of a cylinder having an open top and a closed bottom, an upper end of a partition, which is formed of an insulating material between adjacent cylindrical lower electrodes, has an sharpened tip end and an inclined surface descending from the sharpened tip end toward each adjacent cylindrical lower electrode. With this arrangement, it is possible to prevent silicon grains of a hemi-spherical grain silicon from nidating on the partition, thereby prevent a short-circuiting between the adjacent cylindrical lower electrodes, without reducing the capacitance of the memory cell.

Abstract: A semiconductor device with a semiconductor body (1) provided with a memory capacitor (12, 26) with a lower electrode (11, 23) consisting of a layer of semiconductor material (7, 23) having a rough surface (8, 24) formed by hemispherical grains (9, 25) of the relevant semiconductor material on which a dielectric layer (12, 27) and an upper electrode (13, 28) are provided. The semiconductor material from which the lower electrode is manufactured is Si1−xGex, wherein 0.2<x<1. The semiconductor device can be manufactured in a simple manner because a layer of Si1−xGex having a rough surface formed by hemispherical grains of this material can be simply directly formed through deposition by means of usual CVD (Chemical Vapor Deposition) processes.

Abstract: A thin film capacitor is provided with a thin film protection element to protect the capacitor from damage that can result due to the occurrence of an electrostatic discharge event. The thin film capacitor includes two conductive film portions forming capacitor plates and a dielectric film forming the capacitor dielectric. The protection element may take the form of a thin film diode or a series of thin film diodes connected electrically in parallel with the thin film capacitor. The whole device can be fabricated using a stoichiometric silicon nitride layer to produce the capacitor dielectric and a non-stoichiometric silicon rich silicon nitride layer to provide the diode semiconductor material. One diode is formed by one capacitor plate, the semiconductor layer and an upper diode contact.

Abstract: The invention encompasses a method of forming a dielectric material. A nitrogen-comprising layer is formed on at least some of the surface of a rugged polysilicon substrate to form a first portion of a dielectric material. After the nitrogen-comprising layer is formed, at least some of the substrate is subjected to dry oxidation with one or both of NO and N2O to form a second portion of the dielectric material. The invention also encompasses a method of forming a capacitor. A layer of rugged silicon is formed over a substrate, and a nitrogen-comprising layer is formed on the layer of rugged silicon. Some of the rugged silicon is exposed through the nitrogen-comprising layer. After the nitrogen-comprising layer is formed, at least some of the exposed rugged silicon is subjected to dry oxidation conditions with one or both of NO and N2O. Subsequently, a conductive material layer is formed over the nitrogen-comprising layer. Additionally, the invention encompasses a capacitor structure.

Abstract: A dummy pattern for use in a chemical mechanical polishing (CMP) process is disposed in a field dummy region within a p− well region, isolated by an isolating insulating film, wherein the p− well region has a potential fixed by a ground electrode. The dummy pattern includes a gate insulating film dummy pattern and a gate electrode dummy pattern, formed in the same layers as a gate insulating film and a gate electrode, respectively, of an NMOS transistor. The gate electrode dummy pattern is connected with a contact plug, which in turn is connected with a power supply electrode (Vcc) interconnection line. Thus, a decoupling condenser, formed of the field dummy region within the p− well, the gate insulating film dummy pattern and the gate electrode dummy pattern by utilizing the dummy patterns for use in the CMP process, is connected in parallel with a primary electronic circuit.

Abstract: A microwave-frequency microcircuit assembly includes an integrated circuit structure having a circuit ground. A support structure includes a grounded metallic carrier, and a dielectric substrate having a top surface, a bottom surface contacting the carrier, and a capacitor via extending through the dielectric substrate. A metallization on the top surface of the substrate includes an input metallization trace to the integrated circuit structure, an output metallization trace from the integrated circuit structure, and a substrate ground plane upon which the integrated circuit structure is affixed. A thin-film capacitor resides in the capacitor via and is electrically connected between the substrate ground plane and the carrier. An electrical resistor is connected between the circuit ground of the integrated circuit structure and the carrier to self-bias the integrated circuit structure.

Abstract: A capacitor having variable capacitance for a semiconductor device is formed on a device isolation area. A trench is formed in a semiconductor substrate for device isolation and a device isolating insulating film in which a bottom electrode of the capacitor is buried is formed in the trench. A first dielectric film is formed on the buried bottom electrode, a middle electrode is formed thereon and a second dielectric film and a top electrode are formed on the middle electrode, thereby having a three-layer electrode structure. The capacitor according to the present invention has variable capacitance in accordance with a voltage applied to top, bottom and middle electrodes, respectively.

Abstract: The multilayer electronic device comprises a dielectric body formed by stacking dielectric layers. Flat first internal electrodes and flat second internal electrodes insulated via dielectric layers and arranged facing to the first internal electrodes are alternately stacked. First through-hole electrodes are connected to the first internal electrodes by penetrating, penetrate the second internal electrodes without connecting thereto and extend crossing the internal electrodes. The second through-hole electrodes are connected to the second internal electrodes by penetrating, penetrate the first internal electrodes without connecting thereto and extend crossing the internal electrodes. The first terminal electrodes are arranged on the outer surface of the dielectric body and connected to the first through-hole electrodes.

Abstract: A technique for forming a high surface area electrode or storage node for a capacitor and devices formed thereby, including depositing a first layer of conductive material on a substrate, such that a discontinuous layer is formed. A second conductive material layer is deposited over the discontinuous first conductive material layer, such that the second conductive material layer grows or accumulates on the discontinuous first conductive material layer at a faster rate than on the exposed areas of the substrate in the discontinuous first conductive material layer to form a rough conductive material layer.

Abstract: A cylindrical capacitor structure and a corresponding method of manufacture. To form the cylindrical capacitor, a conductive section, an etching stop layer, a first insulation layer, a bit line structure and a second insulation layer are sequentially formed over a substrate. A portion of the second insulation layer and the first insulation layer is removed until the etching stop layer is exposed. Ultimately, a plurality of gap-connected cylindrical openings and node contact openings between spacers are sequentially formed. Conductive spacers are formed on the sidewalls of the cylindrical openings and the node contact openings. In the meantime, material similar to the conductive spacers fills the small gaps, thereby forming an upper electrode for the capacitor. A dielectric layer is formed over the capacitor electrode. The exposed etching stop layer at the bottom of the contact opening is removed to expose the conductive section above the substrate.

Abstract: The invention describes a high capacitance damascene capacitor. A etch-stop/capacitor dielectric layer 60 is sandwiched between two conductive plates 40 and 75 to form an integrated circuit capacitor. One metal plate 40 is copper formed using a damascene process. The high capacitance of the structure is due to the thin high k dielectric material used to form the etch-stop/capacitor dielectric layer 60.

Abstract: A production of a capacitor includes the simultaneous production, in at least part of an intertrack insulating layer (3) associated with a given metallization level, on the one hand, of the two electrodes (50, 70) and of the dielectric layer (60) of the capacitor and, on the other hand, of a conducting trench (41) which laterally extends the lower electrode of the capacitor, is electrically isolated from the upper electrode and has a transverse dimension smaller than the transverse dimension of the capacitor, and the production, in the interlevel insulating layer (8) covering the intertrack insulating layer, of two conducting pads (80, 81) which come into contact with the upper electrode of the capacitor and with the conducting trench, respectively.

Abstract: The present invention provides a semiconductor device having a metal oxide metal (MOM) capacitor formed over a semiconductor wafer. In one embodiment, the device is a MOM capacitor that includes a first metal layer formed over the semiconductor wafer, a metal silicide layer, such as a tungsten silicide, silicide nitride or a refractory metal silicide, located on the first metal layer and an oxide layer located on the metal silicide layer. The metal silicide layer, which in an advantageous embodiment may be tungsten silicide nitride, resists the corrosive effects of deglazing that may be conducted on other portions of the wafer and is substantially unaffected by the deglazing process, unlike titanium nitride (TiN). Additionally, the metal silicide can act as an etch stop for the etching process. The MOM capacitor is completed by a second metal layer that is located on the oxide layer.

Abstract: A capacitor in a semiconductor integrated circuit is fabricated having a fixed charge density introduced near an electrode/dielectric interface. The fixed charge density compensates for the effects of a depletion layer, which would otherwise lower the effective capacitance. By shifting the undesirable effect of the depletion capacitance outside of the operating voltage range, the capacitor is effectively converted to an accumulation mode. The fixed charge density is preferably introduced by a plasma nitridation process performed prior to formation of the capacitor dielectric.

Abstract: A significant and very effective decoupling capacitor and heat sink combination that, in a single structure provides both a heat sink and a decoupling capacitor in close proximity to the active circuit on the chip requiring either heat sinking or decoupling capacitance or both. This is achieved by forming on a semiconductor chip, having a buried oxide layer therein, an integrated high-performance decoupling capacitor that uses a metallic deposit greater than 30 microns thick formed on the back surface of the chip and electrically connected to the active chip circuit to result in a significant and very effective decoupling capacitor and heat sink in close proximity to the active circuit on the chip requiring such decoupling capacitance and heat sinking capabilities. The decoupling capacitance can use the substrate of the chip itself as one of the capacitive plates and a formed metallic deposit as the second capacitive plate which also serves as a heat sink for the active circuit formed in the chip.

Abstract: An integrated circuit device includes a dielectric layer having an opening therein, and a capacitor comprising in stacked relation a lower electrode lining the opening, a capacitor dielectric layer adjacent the lower electrode, and an upper electrode adjacent the capacitor dielectric layer. The capacitor has a substantially planar upper surface substantially flush with adjacent upper surface portions of the dielectric layer. Additionally, the edges of the lower electrode and the capacitor dielectric layer preferably terminate at the upper surface of the capacitor. Also, the capacitor dielectric may include a high-k, high quality and low leakage dielectric, and which prevents the reduction of the capacitor dielectric by the metal of the upper and lower metal electrodes.

Abstract: A method of fabricating a wide-based boxed-structured capacitor containing hemi-spherical silicon grains. A substrate is provided with a source/drain and a first dielectric layer is formed on the substrate with a node contact opening. Then a doped polysilicon layer and a doped amorphous silicon layer are formed sequentially on the first dielectric layer. An etching step is performed to etch the doped amorphous silicon layer and the doped polysilicon layer and a wide-based lower electrode is formed by adjusting flow speeds of chlorine and of hydrogen bromide. Hemi-spherical silicon grains are formed on the surface of the doped amorphous silicon layer in the lower electrode. A second dielectric layer and an upper electrode are formed sequentially on the lower electrode and the capacitor is completed.

Abstract: An inductor for a semiconductor device is formed within a groove in an insulating layer on a semiconductor substrate. A number of lower conductive lines are formed across the groove. A cylindrical insulator is formed over the lower conductive lines and aligned with the groove. Upper conductive lines are formed over the cylindrical insulator. The upper and lower conductive lines are slanted lengthwise along the groove in opposite directions to form a spiral coil having a circular cross-section, thereby preventing abrupt changes in the magnetic field. The ends of upper conductive lines contact the ends of the lower conductive lines so that the thickness of the coil is controlled by the thickness of the cylindrical insulator, thereby allowing the self-inductance to be increased and the positional density of the conductive lines to be freely controlled.

Abstract: A semiconductor device with a semiconductor body (1) provided with a memory capacitor (12, 26) with a lower electrode (11, 23) consisting of a layer of semiconductor material (7, 23) having a rough surface (8, 24) formed by hemispherical grains (9, 25) of the relevant semiconductor material on which a dielectric layer (12, 27) and an upper electrode (13, 28) are provided. The semiconductor material from which the lower electrode is manufactured is Si1-xGex, wherein 0.2<x<1. The semiconductor device can be manufactured in a simple manner because a layer of Si1-xGex having a rough surface formed by hemispherical grains of this material can be simply directly formed through deposition by means of usual CVD (Chemical Vapor Deposition) processes.

Abstract: The present invention describes the use of large thin film (TF) capacitors having capacitance C made in a separate set of TF layers ABOVE the Si and wiring levels of an integrated circuit (IC). This C is very large. This invention describes a two-level IC architecture in which a metal/insulator/metal (MIM) capacitor structure comprises the upper level, and CMOS logic and memory circuits made in the Si wafer substrate comprise the lower level. The added thin film capacitance serves to stabilize the power supply voltage at a constant level during GHz IC operation.

Abstract: A first concave portion for the element isolation, a second concave portion for an aligning mark, and a third concave portion for an anti-fuse portion are formed simultaneously within a silicon substrate. After a silicon oxide film is formed on the entire surface, the silicon oxide film positioned within the second and third concave portions is removed. Then, a gate insulating film is formed on the entire surface, followed by forming a polysilicon film on the gate insulating film. Further, these polysilicon film and gate insulating film are selectively removed to form a gate electrode above an element region, an aligning mark portion in the second concave portion, and a gate electrode for an anti-fuse portion on the bottom surface of the third concave portion.