Abstract: Extending high k material of a second dielectric layer to surround at least one thru-via designed to provide a signal other than a power signal to a die may eliminate discrete AC coupling capacitors to reduce cost and improve performance of the package.

Abstract: The invention includes a memory device having a capacitor in combination with a transistor. The memory device can be within a TFT construction. The capacitor is configured to provide both area and perimeter components of capacitance for capacitive enhancement. The capacitor includes a reference plate which splits into at least two prongs. Each of the prongs is surrounded by a lateral periphery. A dielectric material extends around the lateral peripheries of the prongs, and a storage node surrounds an entirety of the lateral peripheries of the prongs. The storage node is separated from the reference plate by at least the dielectric material. Also, the invention includes electronic systems comprising novel capacitor constructions.

Abstract: Metal-insulator-metal capacitor structures are formed in semiconductor substrates using an anodization procedure on deposited underlying metalization followed by deposition of the second metal and planarization by chemical-mechanical polishing or other procedures. The process is additive in character, as opposed to traditional subtractive etch processes for forming capacitor structures. In addition, the process can be used in damascene applications, and can be used to form a wide variety of capacitive structures while reducing the number of mask layers required for formation.

Abstract: The process comprises the steps of forming, on top of a semiconductor material wafer, a holed mask having a lattice structure and comprising a plurality of openings each having a substantially square shape and a side with an inclination of 45° with respect to the flat of the wafer; carrying out an anisotropic etch in TMAH of the wafer, using said holed mask, thus forming a cavity, the cross section of which has the shape of an upside-down isosceles trapezium; and carrying out a chemical vapor deposition using TEOS, thus forming a TEOS layer which completely closes the openings of the holed mask and defines a diaphragm overlying the cavity and on which a suspended integrated structure can subsequently be manufactured.

Abstract: A semiconductor device has an LSI device provided with a plurality of power supply line connection pads and ground line connection pad in a peripheral edge part of a circuit-formation surface, metal foil leads 5 electrically connected to each of the pads and adhered to the LSI device via an insulation layer, and decoupling capacitors mounted on one surface of the metal foil leads.

Abstract: A device includes a transistor, and two interdigital capacitors. The transistor is located on an imaginary extension line aligned with a common electrode of the two interdigital capacitors.

Abstract: A process for fabricating a crown-cell capacitor in a memory integrated circuit. The process includes the step of forming a transistor having a contact region 353 at a surface of a semiconductor substrate 300. The transistor, with the exception of the contact region, is covered with a first material 362, 366 and the first material and the contact region are then covered with a layer of a second material 370. The portion of the second layer covering the contact region is removed to expose the contact region so that the removal of the portions of the second layer forms a cavity characterized by a bottom formed of the first material and sides formed of the second material. Further steps in the process include forming a first conductive layer 372 in the cavity to contact the contact region and conform to the bottom and sides, forming a dielectric layer 376 over the first conductive layer, and forming a second conductive layer 378 over the dielectric layer.

Abstract: Disclosed is a method of increasing the capacitance of a trench capacitor by increasing sidewall area, comprising: Corming a trench in a silicon substrate, the trench having a sidewall; forming islands on the sidewall of the trench; and etching pits into the sidewall using the islands as a mask. The capacitor is completed by forming a node insulator on the pits and the sidewall; and filling said trench with a trench conductor.

Abstract: A storage capacitor structure of a planar display is disclosed. The storage capacitor includes a substrate, a bottom electrode, an insulator, and a top electrode. The bottom electrode or top electrode has an uneven surface toward the insulator interposed between the two electrodes in order to increase the capacitance of the storage capacitor structure. A method for fabricating such storage capacitor structure is also disclosed. It includes steps of providing a substrate; and forming a bottom electrode, an insulator, and a top electrode in sequence. The bottom electrode or the top electrode has the uneven surface by an etching step.

Abstract: A method of forming a corrugated capacitor on a semiconductor component. The method of forming the corrugated capacitor comprises a series of depositing alternating layers of doped silicon glass having different etch rates on a semiconductor component, covering the alternating layers with an etch-resistant material, and etching the alternating layers, thereby forming a capacitor structure having corrugated sides.

Abstract: The semiconductor device comprises a capacitor including a storage electrode 76, a capacitor dielectric film formed on the storage electrode 76, and a plate electrode formed on the capacitor dielectric film 78, the storage electrode 76 having an upper end rounded and having a larger thickness at the upper end than a thickness in the rest region. Whereby electric field concentration on the upper end of the storage electrode can be mitigated, and leakage current increase and dielectric breakdown of the capacitor dielectric film can be precluded.

Abstract: A decoupling device for decoupling a high-frequency noise wave in a digital circuit is formed as a line device including a portion of a semiconductor substrate, an insulator film formed thereon as a gate oxide film, and an interconnect line formed thereon as a gate electrode. The line capacitance between the interconnect line and the semiconductor substrate is 100 pF or above, whereby the decoupling device effectively decouples the electromagnetic noise wave generated by a switching device in a frequency range between 10 and 1000 GHz.

Abstract: A method of forming a capacitor includes, a) providing a node to which electrical connection to a first capacitor plate is to be made; b) then, providing a finned lower capacitor plate in ohmic electrical connection with the node using no more than one photomasking step; and c) providing a capacitor dielectric layer and a conductive second capacitor plate layer over the conductive layer.

Abstract: A semiconductor device includes a semiconductor bare chip and an electrically-insulative board member with a thin-film structure capacitor. The semiconductor bare chip has a power supply terminal and a grounding terminal on the back surface thereof. The semiconductor bare chip is mounted on a circuit board by flip-chip bonding. The board member includes a board and a thin-film structure capacitor provided on the board. The capacitor has terminals corresponding to the power supply terminal and the grounding terminal of the semiconductor bare chip thereon. The side of the board member where the capacitor is provided is bonded to the back surface of the semiconductor bare chip. The terminals of the capacitor are electrically connected to the power supply terminal and the grounding terminal of the semiconductor bare chip.

Abstract: A semiconductor integrated circuit device according to an embodiment of the present invention has an MIM structure capacitor connected between a power source potential electrode wiring and a ground potential electrode wiring each via at least one interlayer connection wiring.

Abstract: A layout and a method for generating a mask for a capacitor are provided. The layout and the mask allow for the formation of the capacitor or an array of capacitors without phase conflict when using phase shift masks in an optical lithography fabrication process.

Abstract: An interconnect module and a method of manufacturing the same is described comprising: a substrate, an interconnect section formed on the substrate, and a variable passive device section formed on the substrate located laterally adjacent to the interconnect section. The interconnect section has at least two metal interconnect layers separated by a dielectric layer and the variable passive device has at least one moveable element. The moveable element is formed from a metal layer which is formed from the same material and at the same time as one of the two interconnect layers. The moveable element is formed on the dielectric layer and is released by local removal of the dielectric layer. Additional interconnect layers and intermediate dielectric layers may be added.

Abstract: A method for manufacturing a trench capacitor includes the step of etching a shallow isolation trench in a two-step process flow. During a first etching step, an etch chemistry based on chlorine or bromine performs a highly selective etch for silicon. During a second step, the etch chemistry is based on SiF4 and O2 which rather equally etches polysilicon and the collar isolation. On top of the wafer, the deposition of silicon oxide on the hard mask predominates and avoids an erosion of the hard mask. On the bottom of the trench the conformal etching of polysilicon and collar isolation predominates. The method provides an economic process flow and is suitable for small feature sizes.

Abstract: A charge control circuit for controlling a micro-electromechanical device having a variable capacitance is disclosed. In one embodiment, a charge storage device is configured to store a charge amount. A switch circuit is configured to control the variable capacitance of the micro-electromechanical device by sharing the charge amount between the charge storage device and the micro-electromechanical device to equalize the charge storage device and the micro-electromechanical device to a same voltage.

Abstract: A semiconductor device and a method for preparing the same that can solve crack of a semiconductor film, capacitance electrodes and the like due to stress when forming a source electrode and a drain electrode in a semiconductor device having a thin film transistor and a holding capacitance with three or more capacitance electrodes is provided. Before forming the source electrode and the drain electrode, a crystalline silicon film for relaxing the stress is formed, then a contact hole connecting to the semiconductor film of the thin film transistor is opened, and a metal film to be the source electrode and the drain electrode is formed.

Abstract: Disclosed herein is a method of manufacturing a semiconductor capacitor. In the semiconductor capacitor manufacturing method, an amorphous film composed of non-doped silicon is formed. The amorphous film is changed to a lower film having projections and depressions defined in the surface thereof by heat treatment. An amorphous film composed of impurity-doped silicon is formed over the surface of the lower film. Further, the amorphous film composed of the impurity-doped silicon is changed to an upper film having projections and depressions defined in the surface thereof by heat treatment with the projections and depressions provided over the surface of the lower film as a basis. The semiconductor capacitor is equipped with an electrode having the lower film and the upper film.

Abstract: An electronic structure having a first conductive layer provided by a dual damascene fabrication process; an etch-stop layer provided by the fabrication process, and electrically coupled with the first conductive layer, the etch-stop layer having a preselected dielectric constant and a predetermined geometry; and a second conductive layer, electrically coupled with the etch-stop layer. The structure can be, for example, a metal-insulator-metal capacitor, an antifuse, and the like.

Abstract: Methods of forming a uniform cell nitride dielectric layer over varying substrate materials such as an insulation material and a conductive or semiconductive material, methods of forming capacitors having a uniform nitride dielectric layer deposited onto varying substrate materials such as an insulation layer and overlying conductive or semiconductive electrode, and capacitors formed from such methods are provided. In one embodiment of forming a uniform cell nitride layer in a capacitor construction, a surface-modifying agent is implanted into exposed surfaces of an insulation layer of a capacitor container by low angle implantation to alter the surface properties of the insulation layer for enhanced nucleation of the depositing cell nitride material, preferably while rotating the substrate for adequate implantation of the modifying substance along the top corner portion of the container.

Abstract: The present invention provides an varactor, a method of manufacture thereof. In an exemplary embodiment, the varactor includes a semiconductor substrate and well of a first and second conductivity type, respectively. A conductive region in the well has a same conductivity type as the well but a lower resistivity than the well. At least a portion of the well is between at least two sides of the conductive region and an area delineated by an outer perimeter of a conductive layer over the well. Such varactors have a lower series resistance and therefore have an increased quality factor.

Abstract: Substrates with embedded free space light guiding channels for optical interconnects, and methods for making such substrates are shown. The method comprising steps of a groove in a first generally planar body, and combining the first body with a second generally planar body to form the substrate, and providing input and output ports to enable light to travel into and out of the groove. The first and second bodies may be made of silicon, polymers or combinations of the two. Additional generally planar bodies may be incorporated to provide for complex, 3D optical signal routing within the substrate.

Abstract: An electronic structure having a first conductive layer provided by a dual damascene fabrication process; an etch-stop layer provided by the fabrication process, and electrically coupled with the first conductive layer, the etch-stop layer having a preselected dielectric constant and a predetermined geometry; and a second conductive layer, electrically coupled with the etch-stop layer. The structure can be, for example, a metal-insulator-metal capacitor, an antifuse, and the like.

Abstract: Adjacent ones of a plurality of fuse electrodes extending parallel to each other are cut off by a laser beam. Cutting positions on the adjacent fuse electrodes are set to positions which are different from each other in a direction in which the fuse electrodes extend. Since the cutting positions on the adjacent fuse electrodes are different from each other, the adjacent fuse electrodes are prevented from being short-circuited by fragments of components thereof that are scattered when the laser beam is applied to cut off the fuse electrodes.

Abstract: A capacitor structure having a first level of electrically conductive parallel lines and at least a second level of electrically conductive parallel lines disposed over the lines in the first level, the lines of the first and second levels being arranged in vertical rows. A dielectric layer is disposed between the first and second levels of conductive lines. One or more vias connect the first and second level lines in each of the rows, thereby forming a parallel array of vertical capacitor plates. Electrically opposing nodes form the terminals of the capacitor. The parallel array of vertical capacitor plates are electrically connected to the nodes in an alternating manner so that the plates have alternating electrical polarities.

Abstract: The present invention relates to a capacitor element and its manufacturing method. The invention presents a capacitor element comprising a lower electrode, a dielectric film, and an upper electrode, and its manufacturing method, in which the surface of at least one layer of the lower electrode in a single layer structure or laminated structure, for example, the surface of the lower electrode contacting with the dielectric film, is flattened by processing the material itself which composes this surface. For example, it is flattened by filling the recesses at the crystal grain boundary of the surface with the material itself shaved from the surface. As a result, undulations of the surface of the lower electrode of the capacitor element are lessened, and the film thickness of the dielectric film is made uniform, and capacity drop and increase of leak current can be prevented.

Abstract: A thin-film capacitor(2) in which a lower electrode(6), a dielectric thin-film(8), and an upper electrode(10) are formed in order on a substrate(4). The dielectric thin-film(8) is made of a composition for thin-film capacitance devices. The composition includes a bismuth layer-structured compound whose c-axis is oriented vertically to the substrate surface and which is expressed by a formula: (Bi2O2)2+(Am−1BmO3m+1)2−, or Bi2Am−1BmO3m+3 wherein “m” is an odd number, “A” is at least one element selected from Na, K, Pb, Ba, Sr, Ca and Bi, and “B” is at least one element selected from Fe, Co, Cr, Ga, Ti, Nb, Ta Sb, V, Mo and W. Even if the dielectric thin-film is made more thinner, the dielectric constant is relatively high, and the loss is small. The leak characteristics are excellent, the temperature characteristics of the dielectric constant are excellent, the break-down voltage is improved and the surface smoothness is excellent.

Abstract: Systems and devices are disclosed utilizing a silicon-containing barrier layer. A semiconductor device is disclosed and includes a substrate, a gate oxide, a silicon-containing barrier layer and a gate electrode. The gate oxide is formed over the substrate. The silicon-containing barrier layer is formed over the gate oxide by causing silicon atoms of a precursor layer react with a reactive agent. The gate electrode is formed over the silicon-containing barrier layer.

Abstract: There are provided a first insulating film over a semiconductor substrate, a capacitor formed on the first insulating film and having a lower electrode, a ferroelectric film, and an upper electrode, a capacitor-protection insulating film formed on the capacitor to apply a tensile stress of more than 2.0×109 dyn/cm2 to the capacitor, and a second insulating film formed on the capacitor-protection insulating film to apply a compressive stress of more than 2.6×109 dyn/cm2 to the capacitor.

Abstract: A semiconductor device having a capacitor formed in a multilayer wiring structure, the semiconductor device comprising a multilayer wiring structure including a plurality of wiring layers formed on a substrate, a capacitor arranged in a predetermined wiring layer in the multilayer wiring structure and having a lower electrode, a dielectric film, and an upper electrode, a first via formed in the predetermined wiring layer and connected to a top surface of the upper electrode of the capacitor, and a second via formed in an overlying wiring layer stacked on the predetermined wiring layer, the second via being formed on the first via.

Abstract: The invention includes a memory device having a capacitor in combination with a transistor. The memory device can be within a TFT construction. The capacitor is configured to provide both area and perimeter components of capacitance for capacitive enhancement. The capacitor includes a reference plate which splits into at least two prongs. Each of the prongs is surrounded by a lateral periphery. A dielectric material extends around the lateral peripheries of the prongs, and a storage node surrounds an entirety of the lateral peripheries of the prongs. The storage node is separated from the reference plate by at least the dielectric material. Also, the invention includes electronic systems comprising novel capacitor constructions.

Abstract: A test wafer is provided, in particular for use in monitoring inspection installations for semiconductor fabrication that are based on the analysis of scattered or reflected radiation. The test wafer is subdivided into a multiplicity of regularly disposed chip fields. The test wafer is characterized in that the test wafer has at least a first type of structures, which are disposed chip-field-periodically, and at least a second type of structures, which are disposed non-chip-field-periodically at predetermined locations on the test wafer.

Abstract: Semiconductor device structures and methods of making such structures that include one or more etched openings (e.g., capacitor containers and/or contact apertures) therein with increased height-to-width ratios are provided. The structures of the present invention are formed by successive layer deposition wherein conventional patterning techniques may be utilized in a stepwise fashion as the height of the structure is increased. Further provided is a self-aligning interconnection structure which may be used to substantially vertically align openings formed in successively deposited, vertically placed structural layers of a semiconductor device. The interconnection structure utilizes a cap-and-funnel model that self-aligns to the center plane of an opening in a first structural layer and also substantially prevents subsequently deposited material from entering the opening.

Abstract: Apparatus and method for providing high dielectric constant decoupling capacitors for semiconductor structures. The high dielectric constant decoupling capacitor can be fabricated by depositing high dielectric constant material between adjacent conductors on the same level, between conductors in successive levels, or both, to thereby provide very large capacitance value without any area or reliability penalty.

Abstract: A semiconductor device having a variable capacitance capacitor and a method of manufacturing the same are disclosed. An example semiconductor device includes a capacitor having a bottom electrode, a dielectric layer and an upper electrode, formed on a semiconductor substrate. The example semiconductor also includes a first insulating layer formed on the semiconductor substrate to cover the capacitor, a first contact plug formed in a first via hole of the first insulating layer and electrically connected to the bottom and upper electrodes, a first metal wiring formed on the first insulating layer and connected to the bottom electrode through the first contact plug, a second contact plug formed on the first insulating layer and connected to the upper electrode through the first contact plug, and a second insulating layer formed on the first insulating layer to cover the first metal wiring and the second contact plug.

Abstract: The present invention relates to an electrically conductive film stack for semiconductors and methods and apparatus for providing same. A film stack comprising a first layer of a platinum-rhodium alloy deposited by metal organic chemical vapor deposition (MOCVD) in the presence of a reducer, such as hydrogen (H2) gas, and a second layer of the platinum-rhodium alloy deposited in the presence of an oxidizing gas, such as ozone (O3), provides an electrical conductor that is also a relatively good barrier to oxygen. The platinum-rhodium film stack can be used as an electrode or capacitor plate for a capacitor with a high-k dielectric material. The electrode formed with alternating reducing and oxidizing agents produces a rough surface texture, which enhances the memory cell capacitance.

Abstract: Semiconductor device structures and methods of making such structures that include one or more etched openings (e.g., capacitor containers and/or contact apertures) therein with increased height-to-width ratios are provided. The structures of the present invention are formed by successive layer deposition wherein conventional patterning techniques may be utilized in a stepwise fashion as the height of the structure is increased. Further provided is a self-aligning interconnection structure which may be used to substantially vertically align openings formed in successively deposited, vertically placed structural layers of a semiconductor device. The interconnection structure utilizes a cap-and-funnel model that self-aligns to the center plane of an opening in a first structural layer and also substantially prevents subsequently deposited material from entering the opening.

Abstract: The invention is directed to unique high-surface area BEOL capacitor structures with high-k dielectric layers and methods for fabricating the same. These high-surface area BEOL capacitor structures may be used in analog and mixed signal applications. The capacitor is formed within a trench with pedestals within the trench to provide additional surface area. The top and bottom electrodes are created using damascene integration scheme. The dielectric layer is created as a multilayer dielectric film comprising for instance Al2O3, Al2O3/Ta2O5, Al2O3/Ta2O5/Al2O3 and the like. The dielectric layer may be deposited by methods like atomic layer deposition or chemical vapor deposition. The dielectric layer used in the capacitor may also be produced by anodic oxidation of a metallic precursor to yield a high dielectric constant oxide layer.

Abstract: An integrated capacitor including a semiconductor substrate is disclosed. An outer vertical plate is laid over the semiconductor substrate. The outer vertical plate of a plurality of first conductive slabs connected vertically using multiple first via plugs. The outer vertical plate defines a grid area. An inner vertical plate is laid over the semiconductor substrate in parallel with the outer vertical plate and is encompassed by the grid area defined by the outer vertical plate. The inner vertical plate consists of a plurality of second conductive slabs connected vertically using multiple second via plugs. A horizontal conductive plate is laid under the outer vertical plate and inner vertical plate over the semiconductor substrate for shielding the outer vertical plate from producing a plate-to-substrate parasitic capacitance thereof. The inner vertical plate is electrically connected with the horizontal conductive plate using at least one third via plug.

Abstract: A semiconductor device (10) is formed on a semiconductor substrate (12) whose surface (24) is formed with a trench (18). A capacitor (20) has a first plate (22) formed over the substrate surface with first and second portions lining first and second sidewalls (25) of the trench, respectively. A second plate (35, 38) is formed over the first plate and extends into the trench between the first and second portions.

Abstract: A semiconductor integrated circuit in which the storage capacitor has an increased capacitance and a decreased leakage current. The storage capacitor is formed by the steps of: forming a polysilicon bottom electrode having semispherical silicon crystals formed thereon; performing plasma nitriding on the surface of said bottom electrode at a temperature lower than 550° C., thereby forming a film of silicon nitride having a film thickness smaller than 1.5 nm; and depositing a film of amorphous tantalum pentoxide and then crystallizing said amorphous tantalum pentoxide. The silicon nitride film has improved resistance to oxidation and also has a reduced leakage current. As a result, the polysilicon bottom electrode becomes resistant to oxidation and the storage capacitor increases in capacitance and decreases in leakage current.

Abstract: A capacitor structure within a microelectronic product employs at least one of: (1) an oxidation barrier layer formed upon a second capacitor plate within the capacitor structure; and (2) a spacer formed adjoining a sidewall of the second capacitor plate, where the spacer is formed with an “L” shape. The foregoing features of the capacitor structure provide a capacitor formed therein with enhanced performance.

Abstract: A spiral inductor comprising: a substrate; a protruding portion which is formed on the top face of the substrate and the top of which serves as a dummy element for controlling a chemical mechanical polishing process; and a conductive layer which is formed on the substrate so as to have a spiral shape and which serves as an induction element, wherein the protruding portion is formed in a region other than a region directly below the conductive layer.

Abstract: An intermediate metal plug is used to raise the platform to which contact is to be made. In the illustrated process, a partial bit line plug is formed adjacent a stacked capacitor, and an interlevel dielectric formed over the capacitor. The bit line contact is completed by extending a via from the bit line, formed above the interlevel dielectric, down to the level of the intermediate plug, and the via is filled with metal. The height of the via to be filled is thus reduced by the height of the intermediate plug. In one embodiment, the intermediate plug is slightly shorter than an adjacent container-shaped capacitor. In another embodiment, the intermediate plug is about as high as an adjacent stud capacitor.

Abstract: A Metal-Insulator-Metal (MIM) capacitor structure and method of fabricating the same in an integrated circuit improve capacitance density in a MIM capacitor structure by utilizing a sidewall spacer extending along a channel defined between a pair of legs that define portions of the MIM capacitor structure. Each of the legs includes top and bottom electrodes and an insulator layer interposed therebetween, as well as a sidewall that faces the channel. The sidewall spacer incorporates a conductive layer and an insulator layer interposed between the conductive layer and the sidewall of one of the legs, and the conductive layer of the sidewall spacer is physically separated from the top electrode of the MIM capacitor structure. In addition, the bottom electrode of a MIM capacitor structure may be ammonia plasma treated prior to deposition of an insulator layer thereover to reduce oxidation of the electrode.

Abstract: The invention concerns a variable capacitance capacitor comprising a periodic structure of raised zones (5) separated by recesses (6) formed in a type N semiconductor substrate (1). The walls of the raised zones and the base of the recesses are coated with a conductive layer (9, 10). The substrate is connected to a first terminal (A) of the capacitor and the conductive layer to a second terminal (B) of the capacitor. At least the base of the recesses or the side of the raised zones comprises type P regions (8), the pitch of the raised parts being selected so that the space charging zones linked to the type P regions are joined when the voltage difference between said terminals exceeds a predetermined threshold. The zones not comprising type P regions are coated with an insulant (7) and a highly doped N region (10) is formed beneath the insulant.

Abstract: An integrated capacitor including a semiconductor substrate is disclosed. An outer vertical plate is laid over the semiconductor substrate. The outer vertical plate of a plurality of first conductive slabs connected vertically using multiple first via plugs. The outer vertical plate defines a grid area. An inner vertical plate is laid over the semiconductor substrate in parallel with the outer vertical plate and is encompassed by the grid area defined by the outer vertical plate. The inner vertical plate consists of a plurality of second conductive slabs connected vertically using multiple second via plugs. A horizontal conductive plate is laid under the outer vertical plate and inner vertical plate over the semiconductor substrate for shielding the outer vertical plate from producing a plate-to-substrate parasitic capacitance thereof. The inner vertical plate is electrically connected with the horizontal conductive plate using at least one third via plug.