Abstract: An electrical circuit for measuring threshold voltages and also a circuit for controlling threshold value variations, while avoiding a need to significantly modify or alter the circuit layout, are provided. A semiconductor device has a plurality of substrate conductor regions commonly shared by multiple metal insulator semiconductor field effect transistors (MISFETs) of the same conductivity type, wherein each of the plurality of substrate conductor regions is electrically separated or isolated from one another.

Abstract: An integrated circuit device is described which includes a voltage reduction circuit to reduce an externally supplied voltage using a transistor threshold drop. The transistor is fabricated in a well to isolate the transistor from the integrated circuit substrate. The transistor can be fabricated with a lower breakdown voltage level and still reduce a high voltage. The transistor can also be fabricated in the same manner as other transistors in the integrated circuit. A voltage regulator circuit is also described which incorporates the reduction circuit to allow the use of transistors which are not designed to handle an external voltage Vpp.

Abstract: In important applications of circuits comprising transistors of the lateral DMOST type, such as (half) bridges, the voltage on the output may become higher or lower than the supply voltage or earth in the case of an inductive load. The injection of charge carriers into the substrate can be prevented by screening the drain (18) of the Low-Side transistor from the substrate by means of a p-type buried layer (13) and an n-type buried layer (14) below said p-type buried layer. In order to avoid parasitic npn-action between the n-type buried layer (14) and the n-type drain (18), not only the back-gate regions (16a, 16c) at the edge of the transistor, but also the back-gate regions (16b) in the center of the transistor, are connected to the p-type buried layer, for example by means of a p-type well. As a result, throughout the relatively high-ohmic buried layer, the potential is well defined, so that said npn-action is prevented.

Abstract: A triple well charge pump comprises a first transistor connected in a diode configuration having a first channel terminal, nominally the source, coupled to a first node, and the second channel terminal, nominally the drain, coupled to its gate and to a second node. A first capacitor has a first terminal coupled to the first node of the charge pump, and a second terminal adapted to receive a first clock signal. A second transistor has a first channel terminal coupled to the second node of the charge pump, and a second channel terminal coupled to its gate and to a third node. A second capacitor has a first terminal coupled to the second node, and a second terminal adapted to receive a second clock signal.

Abstract: The present invention relates to a semiconducting structure constituting a protected rectifying bridge implemented in an N-type semiconductor substrate divided into first, second, and third wells by vertical P-type isolating walls, in which the rear surface of the substrate is coated with a first metallization and in which each of the first and second wells includes a vertical diode and a vertical Shockley diode. The third well includes a P-type isolating layer on its rear surface side in contact with the first metallization and, on its front surface side, two lateral diodes, each of which is formed between a P-type region and the substrate.

Abstract: A micromachined structure having electrically isolated components is formed by thermomigrating a dopant through a substrate to form a doped region within the substrate. The doped region separates two portions of the substrate. The dopant is selected such that the doped region electrically isolates the two portions of the substrate from each other via junction isolation.

Abstract: The present invention provides a layout structure of an interconnection which feeds a fixed voltage level to a sense amplifier provided in a cell array block of a semiconductor memory device, wherein the interconnection selectively extends only an inside of an outside edge of a second conductivity type outside well region provided along one peripheral side of a first conductivity type well region, in which the cell array block is provided.

Abstract: The present invention relates to an isolating wall for separating elementary components formed in different wells, a component located in at least one of the wells being capable of operating with a high current density. The isolating wall exhibits in its median portion a concentration of carriers higher than 1016 atoms/cm3. Preferably, the width of the openings from which the dopant diffusions are formed in the upper and lower surfaces of the substrate is higher than 1.3 times the half-thickness of the substrate.

Abstract: A semiconductor device of the type having an integrated circuit with connection terminals connected to metal pads by connecting wires is provided. The integrated circuit includes a semiconductor substrate having a lower portion on top of which there is an upper layer that is more heavily doped than the lower portion. A first block and a second block are produced in the upper part of the substrate, and decoupling means are arranged in the vicinity of the first block. The decoupling means include at least one decoupling circuit that is connected to the lower portion of the substrate and to a ground connection pad, and the decoupling circuit has a minimum impedance at a predetermined frequency. In one preferred embodiment, the decoupling circuit includes an inductive-capacitive resonant circuit having a resonant frequency substantially equal to the predetermined frequency.

Abstract: A semiconductor structure (10) having device isolation structures (43, 44) and shielding structures (39, 40). The shielding structures (39, 40) are formed in a semiconductor material (11) and the device isolation structures (43, 44) are formed within the corresponding shielding structures (39, 40). A noise generating device is formed within a first shielding structure (43) and a noise sensitive device is formed within a second shielding structure (44). The two shielding structures (39, 40) are grounded and prevent noise from the noise generating device from interfering with the noise sensitive device.

Abstract: According to a first aspect of the present invention, a plurality of PN junctions are formed at the surface of a semiconductor substrate under a belt-like conductive film having a spiral shape which constitutes an inductance device. A reverse bias voltage is applied to the PN junctions, and the surface of the substrate is completely depleted. Since the reverse bias voltage is applied to the PN junctions, even though the impurity density of the surface of the substrate is high and the adjacent PN junctions are separated to a degree, the extension of the depletion layers can be increased and complete depletion of the surface of the substrate can be achieved.

Abstract: An integrated circuit (13) includes a P-epi substrate (51) having first and second n+ isolation layers (53, 54) buried therein, the first and second isolation layers being respectively coupled to ground and to a supply voltage (VCC). A contact region (52) of the substrate is closely adjacent a first isolation layer, is spaced from the second isolation layer, and is coupled to ground. First and second P-epi portions (57, 58) of the substrate are disposed within the first and second isolation layers. The first portion includes an n+ source region (62) disposed in a p-well (61) which is closely adjacent the first isolation layer in the vicinity of the contact region, and includes an n+ drain region (68). The second portion includes an n+ source region (77) coupled to the drain region in the first portion, and an n+ drain region (82) coupled to the supply voltage.

Abstract: Disclosed is a semiconductor device, such as a semiconductor memory device, having structure wherein invasion of minority carriers from the semiconductor substrate into components of the device, formed on the substrate, can be avoided. The semiconductor memory device can be an SRAM or DRAM, for example, and includes a memory array and peripheral circuit on a substrate. In one aspect of the present invention, a buried layer of the same conductivity type as that of the substrate, but with a higher impurity concentration than that of the substrate, is provided beneath at least one of the peripheral circuit and memory array. A further region can extend from the buried layer, for example, to the surface of the semiconductor substrate, the buried layer and further region in combination acting as a shield to prevent minority carriers from penetrating to the device elements.

Abstract: A semiconductor device, for example an IC, having conductor tracks (3) of a metal (3) exhibiting a better conductance than aluminium, such as copper, silver, gold or an alloy thereof. The tracks are situated on an insulating layer (2) and are connected to a semiconductor region (1A) or to an aluminium conductor track by means of a metal plug (5), for example of tungsten, which is situated in an aperture (4) in the insulating layer (2). The bottom and walls of the aperture (4) are provided with an electroconductive material (6), such as titanium nitride, which forms a diffusion barrier for the metal (3). In accordance with the invention, the insulating layer (2) comprises a sub-layer (2A), which forms a diffusion barrier for the metal (3) and which extends, outside the aperture (4), throughout the surface of the semiconductor body (10). As a result, the conductor tracks (3) no longer have to be provided with a sheath serving as a diffusion barrier for the metal (3).

Abstract: A semiconductor circuit device having a triple-well structure wherein a predetermined potential level is supplied to a top well without a contact region formed in the top well is disclosed. In an N-type ion implantation step for forming an N-type well region (1) in a P-type semiconductor substrate (5), a mask of a predetermined configuration is used so that ions are not implanted into a region of a portion which is to serve as a bottom portion (1B) of the well region (1). Then, the N-type well region (1) is formed which is shaped such that a portion (6) having P-type properties remains partially in the bottom portion (1B). The P-type portion (6) establishes electrical connection between a P-type well region (2) and the semiconductor substrate (5) to permit the potential applied to a contact region (4) to be supplied to the well region (2) therethrough. The portion (6) may include a plurality of portions (6) which allow uniform potential supply.

Abstract: The invention relates to a half-bridge circuit comprising two series-connected n-channel DMOS transistors, in which the source of the one transistor, the low-side transistor T.sub.1, is connected to a low-voltage terminal V.sub.ss, and the drain of the other transistor, the high-side transistor T.sub.2, is connected to a high-voltage terminal V.sub.dd. The drain of the low-side transistor and the source of the high-side transistor are connected to the output terminal (4). The circuit is arranged in a semiconductor body having an n-type or p-type epitaxial layer (11) which is applied to a p-type substrate (10). In the epitaxial layer, two n-type regions are defined for the transistors, each of said regions forming a drift region of one of the transistors and being surrounded by a cup-shaped n-type zone in the semiconductor body. Within the n-type cup-shaped zone (12) of the low-side transistor T.sub.1, there is provided a p-type cup-shaped zone which isolates the drift region (15) of T.sub.

Abstract: A silicon layer provided in a silicon substrate through a buried oxide film includes a silicon island partitioned by a trench. A surface of the silicon island in the trench is covered with a side wall oxide film, and LDMOS transistors are formed in the trench. A first impurity-doped polysilicon layer for applying a substrate potential is disposed between the buried oxide film and the substrate, and a second impurity-doped polysilicon layer is buried in the trench to communicate with the first impurity-doped polysilicon layer. Further, electrodes for applying the substrate potential are disposed on the second impurity-doped polysilicon layer. Accordingly, the substrate potential can be readily applied from the surface of the silicon layer.

Abstract: A semiconductor device include: a substrate of a conductivity type; a first well provided in the substrate and of the same conductivity type as the conductivity type of the substrate; a second well provided in the substrate and of an opposite conductivity type to the conductivity type of the substrate; and a buried well provided at a deep position in the substrate and of the opposite conductivity type to the conductivity type of the substrate. A buried well of the same conductivity type as the conductivity type of the substrate is further provided so as to be in contact with at least a part of a bottom portion of the first well so that the first well is at least partially electrically connected to the substrate.

Abstract: An N.sup.- - region is formed by diffusion on a P- semiconductor substrate, and a P- region is formed in a surface portion of the N.sup.- - region. A P.sup.+ - region is formed in an outer peripheral portion of the N.sup.- - region, to suppress expansion of a depletion layer of the P- semiconductor substrate when a high voltage is applied. A gate oxide film is formed on the semiconductor substrate, and a gate electrode of polycrystalline silicon is formed on the gate oxide film, particularly on a channel region which is formed by the semiconductor substrate and the P.sup.+ - region, which is as a whole the same as a structure of a lateral N-channel MOSFET. Circuit elements are formed within the N.sup.- - region, and a high voltage is applied. Circuit portions are isolated as the gate electrode and a source region are grounded. This reduces the number of steps for manufacturing a high-insulation IC, increases a breakdown voltage, and integrates the circuit denser.

Abstract: A semiconductor device comprises a chip including a MISFET having a source and a drain, in which one of the source and the drain is connected to a second current supply node, an impedance element having a first terminal connected to the other of the source and the drain and a second terminal connected to a first current supply node, and a switching element, in which a well or a body electrode of the MISFET has an active state and a standby state, and is connected to a bias voltage generator for generating different voltages through the switching element, the threshold voltage V.sub.ths during standby state of the MISFET is higher than the threshold voltage V.sub.tha during active state of the MISFET, a voltage applied to a gate of the MISFET being able to take two stationary values, and the following relationship is satisfied V.sub.DD (1-V.sub.ths /V.sub.DD)<V.sub.ths -V.sub.tha, where V.sub.DD represents the higher voltage among the two stationary values.

Abstract: A semiconductor memory device laid out to have a deep well of a second conductivity type formed in a semiconductor substrate of a first conductivity type, a cell array well of the first conductivity type formed on said deep well, and an isolation well of the second conductivity type formed around said cell array well to reach said deep well so as to incorporate said cell array well, thereby isolating said cell array well from said semiconductor substrate through said isolation well, wherein a circuit element for driving said cell array is formed in said isolation well.

Abstract: An integrated circuit device is described which includes a voltage reduction circuit to reduce an externally supplied voltage using a transistor threshold drop. The transistor is fabricated in a well to isolate the transistor from the integrated circuit substrate. The transistor can be fabricated with a lower breakdown voltage level and still reduce a high voltage. The transistor can also be fabricated in the same manner as other transistors in the integrated circuit. A voltage regulator circuit is also described which incorporates the reduction circuit to allow the use of transistors which are not designed to handle an external voltage Vpp.

Abstract: Realizing a reduction of the layout surface area by rendering unnecessary the region used for well isolation. In this DRAM, a triple well construction is used, and all of the regions for the unit memory cell array MA, the word line driver bank WDB, the sense amplifier bank SAB, and the cross area CR are surrounded by a lower layer N-type deep (deep layer) well 12. A back bias VPP corresponding to the power supply voltage of the word line driver is applied to the N well 14, and a back bias VBB corresponding to the characteristics of the memory cell are applied to the P well 16. In the N well 14, in regard to the P-type MOS transistors of the sense amplifier that undergo the substrate bias effect due to the back bias VPP, the threshold voltage is set to a low value so as to cancel that bias effect.

Abstract: A monolithic component for protection against over-currents liable to occur on a line in series with which is connected a detection resistor, comprises a first cathode-gate thyristor associated with an avalanche diode and a second anode-gate thyristor of the gate triggering type or forward breakover type, its breakover voltage being substantially equal to the avalanche voltage of the avalanche diode.

Abstract: An integrated circuit has a pseudosubstrate 6060 with an isolation moat 9505. Substrate 6001 has one conductivity and a subcircuit region 6060 has an opposite conductivity. Digital CMOS devices are formed in the subcircuit over region 6060 and operate between zero to +5 volts. Analog devices are formed over the rest of the substrate and operate between plus and minus 5 volts. The moat 9505 isolates the digital CMOS devices from the analog devices.

Abstract: A high voltage integrated circuit is provided which includes a first conductivity type semiconductor substrate, a first conductivity type isolation region that extends continuously from the first conductivity type semiconductor substrate, a substrate electrode formed on a surface of the first conductivity type isolation region, a second conductivity type island-like region that is formed on the first conductivity type semiconductor substrate, such that the entire periphery of the island-like region is surrounded by the first conductity type isolation region, and a plurality of high voltage MOSFETs that are connected to a common power source and operate independently of each other.

Abstract: In a photodiode array suitable for use in an x-ray detector for computed tomography, the influences of direct conversion of x-rays into contributions to the electrical output signal and optical cross-talk between channels in the photodiode array are significantly reduced by integrating a number of extraction diodes into the photodiode array, with one extraction diode disposed between each two neighboring photodiodes. The anodes of all of the extraction diodes are connected together at a common anode contact, the common anode contact being connected to a voltage source which applies a voltage across all of the extraction diodes for operating the extraction diodes reverse biased, i.e. so as to block current flow.

Abstract: A vertical PNP transistor (11) and method for making it includes forming an N- region (19) in a P substrate (12), and forming an N+ region (26) in the substrate (12) laterally surrounding and partially extending into the N- region (19). A P region (30) is formed above the N- region (19), bounded laterally by the N+ region (26) to be horizontally and vertically isolated from the substrate (12) by the N- and N+ regions (19 and 26). A layer of semiconductor material (32) is formed overall, and an N well (35) and a surrounding P well (36) are formed, each extending to the P region (30). An isolating N+ well (38) is formed surrounding the P well (36), extending to the buried N+ region (26). A P emitter region (40) and an N base contact region (41) are formed at a surface of the N well (35), and a P collector contact region (44) is formed at a surface of the P well (36).

Abstract: An integrated circuit (10) provides analog and digital circuitry on a common substrate (12). A first digital circuit (14) operates in combination with an analog circuit (18) to perform a useful function. A second duplicate digital circuit (26) is disposed adjacent to the first digital circuit and operates out-of-phase with respect to the first digital circuit. The second duplicate digital circuit introduces voltage spikes equal and opposite to the voltage spikes introduced into the substrate by the first digital circuit. The equal and opposite voltage spikes tend to cancel and thereby minimize cross-talk between the digital and analog circuits. A guard ring (16,28) surrounds each of the first and second digital circuits and the analog circuit to reduce voltage spikes into the substrates. By minimizing cross-talk, the analog circuit operates without interference from the digital circuits.

Abstract: A semiconductor device includes a power transistor group and a signal circuit on the same substrate. The substrate is grounded at an isolation region at an end of the substrate adjacent to the power transistor group so that the grounded portion of the substrate is distant from the signal circuit.

Abstract: A micro semiconductor bridge rectifier comprises a first and a second diode chips. The first diode chip comprises an N-type substrate on which two P-type regions are formed. The second diode chip comprises a P-type substrate on which two N-type regions are formed. One P-type region of the first diode chip and one N-type region of the second diode chip are connected to one electrode of a first lead frame, the other P-type region of the first diode chip and the other N-type region of the second diode chip are connected to the other electrode of the first lead frame. The N-type substrate of the first diode chip and the P-type substrate of the second diode chip are connected to respective electrodes of a second lead frame.

Abstract: A semiconductor device has a p-n-p transistor structure having a collector implemented by a p.sup.- -substrate, a base formed as an n-diffused region in the surface region of the substrate, and an emitter formed as a p.sup.+ -diffused region in the first n-diffused layer. The p.sup.- -substrate and the n-base are maintained at a ground level, while the p.sup.+ -collector is maintained at a positive potential for biasing the p-n junction formed between the emitter and the base. The bias potential allows the p-n-p transistor structure to operate in its saturation region to activate the base region to define an enlarged carrier-incresed zone. An analog input pad is located within the carrier-increased zone and protected from a noise propagated from a digital circuit section located outside the carrier-increased zone.

Abstract: A high power MOSFET is disclosed in which two laterally spaced sources each supply current through respective channels in one surface of a semiconductor chip which are controlled by the same gate. The channels lead from the source electrodes to a relatively low resistivity epitaxially formed region which is deposited on a high conductivity substrate. The epitaxially deposited semiconductor material immediately adjacent and beneath the gate and in the path from the sources to the drain has a relatively high conductivity, thereby to substantially reduce the on-resistance of the device without effecting the breakdown voltage of the device. The breakdown voltage of the device is substantially increased by forming a relatively deep p-type diffusion with a large radius in the n-type epitaxial layer beneath each of the sources.

Abstract: A method for selectibly erasing one or more non-volatile programmable memory cells in an integrated circuit. The method is applicable to an array 1 of memory cells 10 fabricated in a semiconductor substrate 30 of a first conductivity type semiconductor material, each cell having a floating gate 14 for programming the cell and a control gate 11 for reading the cell, the array having a plurality of row lines 15, a plurality of column lines 25 and a plurality of output lines 18. The cells should be formed in a first well 33 of said first conductivity type semiconductor material, the first wells being formed in second wells 31 of a second conductivity type semiconductor material, the first wells including cells in groups of one or more. The method involves the steps of applying a high voltage source to a selected one or more column lines, applying a zero voltage source to a selected one or more row lines; and applying the high voltage source to non-selected row lines.

Abstract: A semiconductor device having the grounds of element regions are provided in a semiconductor substrate. The device comprises a semiconductor substrate of a first conductivity type, at least two element regions of a second conductivity type, provided in a semiconductor substrate and having grounds connected to said semiconductor substrate when said semiconductor substrate is set at a fixed potential and at least one ground-isolating well region of the second conductivity type, provided between said at least two element regions to electrically isolate said at least two element regions by forming a depletion layer between said at least two element regions when applied with a reverse bias voltage.

Abstract: An output driver is implemented by a complementary inverter circuit responsive to an output data signal for selectively charging and discharging an external capacitive load, and the complementary inverter circuit has a p-channel enhancement type field effect transistor formed in an n-type well defined in a p-type silicon substrate reversely biased and an n-channel enhancement type field effect transistor formed in a p-type well nested with a reversely biased n-type well defined in the p-type silicon substrate in spacing relation to the n-type well assigned to the p-channel enhancement type field effect transistor, thereby perfectly isolating the p-channel enhancement type field effect transistor from a noise propagated from a ground voltage line to the p-type well assigned to the n-channel enhancement type field effect transistor.

Abstract: An N.sup.- -type epitaxial layer is formed on a P-type semiconductor substrate. A P-type region is formed in the N.sup.- -type epitaxial layer. First and second N.sup.- -type layer islands, isolated by the P-type region, are formed in the N.sup.- -type epitaxial layer. An N.sup.+ +-type contact region is formed in a surface region of the first N.sup.- -type layer island. A pad electrode is formed above the first N.sup.- -type layer island with an oxide film interposed therebetween. A polysilicon layer serving as a resistor is formed above the second N.sup.- -type layer island with the oxide film interposed therebetween. A first conductive layer for electrically connecting the polysilicon layer with the N.sup.+ -type contact region is formed on the polysilicon layer, the N.sup.+ -type contact region and the oxide film. A second conductive layer for electrically connecting the polysilicon layer with a stable high-potential power source is formed on the oxide film and the polysilicon layer.

Abstract: A diffused resistor capable of suppressing variation of characteristics caused by leakage of current occurring under high-temperature conditions. An N-type layer is epitaxially grown on a P-type substrate, and an N-type resistor island isolated by a P-type isolation region is formed. A P-type diffused resistor is formed in the island. An N-type region of high impurity concentration is disposed in close proximity to the high-potential end of the P-type diffused resistor. An electrode is brought into contact with not only the high-potential end but also the N-type high-impurity concentration region through the same contact hole. Thus, a parasitic transistor, which is formed from the P-type diffused resistor, the N-type resistor island and the P-type substrate (P-type isolation region), can be prevented from turning on with a minimal increase of the element area.

Abstract: Disclosed is an integrated circuit having at least two active components, such as transistors, having the following features:a highly conductive substrate is provided which is connected to one pole of a voltage supply source,a semiconductor layer, which is electrically isolated from the substrate and divided into individual sections by lateral isolation regions, is disposed on a main surface of the substrate,placed in each section is at least one active component, e.g., a transistor of any type performance, andlateral deep diffusion regions which are accommodated in the semiconductor layer create a conductive connection between the highly conductive substrate and the corresponding regions of the active components.

Abstract: An improved isolation structure for a semiconductor device includes a p-type semiconductor substrate (12) with a p-type well (28) disposed in the substrate (12). A continuous plurality of n-type regions (14, 16, 26) is disposed around the p-type well (28), and the continuous plurality of n-type regions (14, 16, 26) fully isolates the p-type well (28) from the substrate (12) except that the continuous plurality of regions (14, 16, 26) comprises one or more p-type gaps (18) that electrically connect the p-type well (28) to the p-type substrate (12). The use of the gap (18) improves cross-talk suppression in mixed-mode integrated circuits at higher frequencies, for example greater than 50 MHz.

Abstract: An active pixel image sensor in accordance with the present invention utilizes guard rings, protective diffusions, and/or a combination of these two techniques to prevent electrons generated at the periphery of the active area from impacting upon the image sensor array. For example, an n+ guard ring connected to V.sub.cc can be imposed in the p-epi layer between the active area edge and the array, making it difficult for edge-generated electrons to penetrate the p+ epi in the array; this approach requires the use of annular MOS devices in the array. Alternatively, the gates of the n-channel devices in the array can be built to overlap heavily doped p+ bands, forcing current flow between the source/drain regions. As stated above, combinations of these two techniques are also contemplated. Elimination of the active area edge leakage component from the array can increase the dynamic range of the image sensor by 6 bits.

Abstract: An integrated circuit containing both power and small-signal NPN bipolar devices. The small-signal devices use lateral current flow, and are completely surrounded (laterally and vertically) by an N-type well region. The N-type well region itself is completely surrounded (laterally and vertically) by a P-type isolation region. This double isolation provides improved protection against turn-on of parasitic devices, which can cause leakage problems in the conventional device structures. Optionally a self-aligned process step is used to provide a graded base doping profile in the small-signal devices.

Abstract: A semiconductor integrated circuit has a P-type substrate and a plurality of PN-junction isolated islands of N-type, a first one of the islands may contain a power device which during certain periods of operation causes the first island to become forward biassed and to inject electrons into the substrate. Collection of these injected charges by a second island at one side of the injecting island is reduced by a separate protective bipolar transistor formed in a third N-type island. The third island is preferably interposed between the injecting island and the islands to be protected, but may be located anywhere with respect to the injecting transistor. The emitter of the protective transistor is electrically connected to an N-type portion of the first island. The collector of the protective transistor is connected to the P-type isolation-wall portion of the substrate located between the injecting transistor and the small islands to be protected.

Abstract: A substrate insulation device includes power supply terminals which are connected to a terminal of an active integrated element which has, with respect to a substrate on which it is defined, at least one reverse-biased junction.

Abstract: A semiconductor device includes a semiconductor body (1, 2) with an island-shaped region (3) adjoining the surface, in which a contact pad (6) is provided above the island-shaped region (3) and separated therefrom by an insulating layer (5). The island-shaped region (3) forms a pn-junction (34) with an adjoining isolating region (4). According to the invention, the device is provided with regions (40, 41) for increasing the breakdown voltage of the pn-junction (34).

Abstract: An isolation structure is provided to give improved protection from below ground current injection. A first epitaxial region is provided between a power field effect device and nearby control circuitry. The first epitaxial region is tied to the substrate, and the ties are located between the first epitaxial region and the power field effect device. On the opposite side of the power device, preferably adjacent an edge of the integrated circuit chip, a second epitaxial region is formed. This epitaxial region is connected to the first epitaxial region, preferably by a metal interconnect line. A second set of substrate contacts is located between the power device and the second epitaxial region, and is tied to ground. The second epitaxial region encourages injection of current at a location spaced away from the control circuitry.

Abstract: A complementary field effect element develops an intensified latch-up preventive property even if the distance between the emitters of parasitic transistors is short, and a method of producing the same are disclosed. The complementary field effect element includes a high concentration impurity layer (16) formed by ion implantation in the boundary region between a P-well (2) and an N-well (3) which are formed adjacent each other on the main surface of a semiconductor substrate (1). Therefore, carriers passing through the boundary region between the P-well (2) and the N-well (3) are decreased, so that even if the distance between the emitters (4, 5) of parasitic transistors is short, there is obtained an intensified latch-up preventive property.

Abstract: A semiconductor device includes a p-type silicon substrate, a first well of p-type formed in a major surface of the silicon substrate, and a second well of n-type formed close to the first well in the major surface of the silicon substrate. A third well of p-type is formed inside the second well and, furthermore, a conductive layer including p-type impurities of higher concentration than that of the first well is formed as extending immediately below both the first well and the second well. In accordance with this structure, even if minority carriers are injected, they recombine and disappear in the conductive layer, so that the implantation of the carriers into the first well is prevented. As a result, various disadvantageous phenomena due to the injection of the minority carriers are prevented and a semiconductor device having a stable device characteristic and high integration density is provided.

Abstract: In a semiconductor device, a FET and an isolation are provided on a semiconductor substrate and a channel stop region is provided under the isolation. At least a region to which a high voltage is applied of a source region and a drain region of the FET is separated from the channel stop region, and a first buffer region doped with an impurity for adjusting the threshold level is provided therebetween. A region under a gate electrode and adjacent to the isolation serves as a second buffer region to which an impurity for adjusting the threshold level is doped. With the first buffer region, a depletion region at a boundary of the drain region and the channel stop region is ensured, obtaining a superior durability to high voltage of the source/drain region. With the second buffer region, leakage current between the source region and the drain region is prevented.

Abstract: A high density, mixed technology integrated circuit comprises CMOS structures and bipolar lateral transistors, the electrical efficiency and Early voltage of which are maintained high by forming "well" regions through the collector area. The operation determines the formation of a "collector extension region" extending relatively deep within the epitaxial layer so as to intercept the emitter current and gather it to the collector, subtracting it from dispersion toward the substrate through the adjacent isolation junctions surrounding the region of the lateral bipolar transistor. Under comparable conditions, the ratio between IcIsubstrate is incremented from about 8 to about 300 and the Early voltage from about 20V to about 100V. The V.sub.CEO, BV.sub.CBO and BV.sub.CES voltages are also advantageously increased by the presence of said "well" region formed in the collector zone.