Amorphous Semiconductor Is Alloy Or Contains Material To Change Band Gap (e.g., Si X Ge 1-x , Sin Y ) Patents (Class 257/55)
  • Patent number: 10559593
    Abstract: Structures for a field-effect transistor and methods of forming a structure for a field-effect transistor. A first channel region containing a first semiconductor material and a second channel region containing a second semiconductor material are formed over a buried insulating layer of a silicon-on-insulator substrate. A first gate electrode of a first field-effect transistor is formed over the first channel region. A second gate electrode of a second field-effect transistor is formed over the second channel region. The first semiconductor material of the first channel region has a first germanium concentration. The second semiconductor material of the second channel region has a second germanium concentration that is greater than the first germanium concentration in the first semiconductor material of the first channel region.
    Type: Grant
    Filed: August 13, 2018
    Date of Patent: February 11, 2020
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Carsten Metze, Berthold Reimer, Simeon Morvan
  • Patent number: 10304682
    Abstract: An array substrate, a fabricating method thereof, and a related display device are provided. The method for forming an array substrate can comprises: forming a plurality of signal lines over a base substrate; forming a conductive line over the base substrate, the conductive line connecting at least two of the plurality of signal lines; forming an insulating layer over the base substrate, the plurality of signal lines, and the conductive line; forming a via hole through the insulating layer at a position over the conductive line and between the at least two of the plurality of signal lines; and removing a portion of the conductive line through the via hole to disconnect the conductive line.
    Type: Grant
    Filed: May 26, 2017
    Date of Patent: May 28, 2019
    Assignees: BOE TECHNOLOGY GROUP CO., LTD., BEIJING BOE OPTOELECTRONICS TECHNOLOGY CO., LTD.
    Inventor: Jingang Hao
  • Patent number: 10193089
    Abstract: A display device, an array substrate, and a manufacturing method for the array substrate are disclosed. The array substrate includes a substrate base, and two gates, a source, a drain, an active layer, and a pixel electrode on the substrate base. The drain and the pixel electrode are connected together. The source and the drain contact the active layer, respectively. The two gates control the conduction and cut off of the active layer, which in turn controls the conduction and cut off between the source and the drain. Through the present disclosure, the variation of threshold voltage is effectively prevented.
    Type: Grant
    Filed: July 6, 2016
    Date of Patent: January 29, 2019
    Assignee: Shenzhen China Star Optoelectronics Technology Co., Ltd
    Inventors: Zhichao Zhou, Hui Xia
  • Patent number: 10019955
    Abstract: The invention discloses an array substrate, a display panel and a display device, and belongs to the field of array substrate test technology, which can solve the problem that the performance of the thin film transistor at the display region of the array substrate in an ADS mode cannot be accurately tested. The array substrate in the invention comprises a plurality of pixel units, each of which comprises a pixel electrode, an insulating layer above the pixel electrode, and a common electrode above the insulating layer, wherein at least one of the pixel units is a test pixel unit, wherein an opening is provided in the insulating layer of the test pixel unit to be above the pixel electrode and separated from the common electrode. The display panel and the display device in the invention comprise the above array substrate.
    Type: Grant
    Filed: December 12, 2014
    Date of Patent: July 10, 2018
    Assignees: BOE TECHNOLOGY GROUP CO., LTD., BEIJING BOE OPTOELECTRONICS TECHNOLOGY CO., LTD.
    Inventors: Ziwei Cui, Hongjun Yu, Hong Zhu, Hao Wu
  • Patent number: 9887216
    Abstract: The present disclosure provides a poly-silicon TFT, its manufacturing method, an array substrate and its manufacturing method. The method for manufacturing the poly-silicon TFT includes a step of, subsequent to the formation of an amorphous-silicon active layer and a source electrode of the TFT, applying an electrical signal to the source electrode, so as to maintain the source electrode at a predetermined temperature for a predetermined time period, thereby to crystallize the amorphous active layer into a poly-silicon active layer due to heat generated by the source electrode and transferred to the amorphous active layer.
    Type: Grant
    Filed: May 10, 2016
    Date of Patent: February 6, 2018
    Assignees: BOE TECHNOLOGY GROUP CO., LTD., HEFEI BOE OPTOELECTRONICS TECHNOLOGY CO., LTD.
    Inventors: Tianzhen Liu, Chengcheng Wang, Xianxue Duan
  • Patent number: 9874796
    Abstract: The present invention provides a BOA liquid crystal panel. Both the color resist layer and the black matrix are located on the second substrate, the borders of the two adjacent color resist blocks in the color resist layer overlap to act the effect of light shielding and on this basis, a layer of black matrix is covered to achieve the double layer shielding, which effectively prevents the light leakage due to the exposure of the gap between the data line and the light shielding line when the BOA liquid crystal panel is applied for curve display and meanwhile, shortens the width of the light shielding line. The aperture ratio of the BOA liquid crystal panel is raised to reduce the cost of the backlight.
    Type: Grant
    Filed: October 12, 2015
    Date of Patent: January 23, 2018
    Assignee: SHENZHEN CHINA STAR OPTOELECTRONICS TECHNOLOGY CO., LTD.
    Inventor: Chengliang Ye
  • Patent number: 9583523
    Abstract: A photoelectric conversion device includes a photoelectric conversion unit disposed above a substrate and a reading circuit. The photoelectric conversion unit includes a first electrode disposed above the substrate, a second electrode disposed above the first electrode, and a photoelectric conversion film disposed between the first electrode and the second electrode. The second electrode includes an opening, and is disposed in contact with the photoelectric conversion film at a boundary between adjacent photoelectric conversion units. An insulating film is disposed in contact with the second electrode.
    Type: Grant
    Filed: September 23, 2015
    Date of Patent: February 28, 2017
    Assignee: Canon Kabushiki Kaisha
    Inventor: Tatsuya Ryoki
  • Patent number: 9494815
    Abstract: A twisted nematic liquid crystal display device integrated with a touch control function is disclosed. The device includes an array substrate, a color film substrate disposed opposite the array substrate, and a liquid crystal layer disposed between the array substrate and the color film substrate. The device also includes a common electrode layer disposed on a surface of the color film substrate facing the liquid crystal layer. The common electrode layer includes a plurality of sensing electrodes, a plurality of driving electrodes, and a plurality of dummy electrodes located between the sensing electrodes and the driving electrodes. In addition, the sensing electrodes, the driving electrodes, and the dummy electrodes are insulated from one another.
    Type: Grant
    Filed: November 20, 2013
    Date of Patent: November 15, 2016
    Assignee: SHANGHAI TIANMA MICRO-ELECTRONICS CO., LTD.
    Inventors: Jun Ma, Lijun Zhao
  • Patent number: 9466574
    Abstract: Methods of forming a conductive metal layer over a dielectric layer using plasma enhanced atomic layer deposition (PEALD) are provided, along with related compositions and structures. A plasma barrier layer is deposited over the dielectric layer by a non-plasma atomic layer deposition (ALD) process prior to depositing the conductive layer by PEALD. The plasma barrier layer reduces or prevents deleterious effects of the plasma reactant in the PEALD process on the dielectric layer and can enhance adhesion. The same metal reactant can be used in both the non-plasma ALD process and the PEALD process.
    Type: Grant
    Filed: September 9, 2013
    Date of Patent: October 11, 2016
    Assignee: ASM AMERICA, INC.
    Inventors: Robert B. Milligan, Dong Li, Steven Marcus
  • Patent number: 9466742
    Abstract: A photoelectric conversion material is disclosed in the present invention and comprises at least a cone material. The cone material is composed of an isomer and comprises a plurality of grains. The sizes of the grains are arranged from smaller ones to larger ones along a direction. In the meantime, a method for fabricating the above photoelectric conversion material is also disclosed here. The method comprises the following steps. First, a precursor is provided. The precursor comprises at least a cone material and the cone material is a multilayer structured material, such as sodium titanate and potassium titanate, formed by stacking first materials and second materials. And then, the precursor is annealed to let the second materials leave from the cone material, and the cone material becomes the above photoelectric conversion material with a plurality of grains.
    Type: Grant
    Filed: November 16, 2015
    Date of Patent: October 11, 2016
    Assignee: NATIONAL TSING HUA UNIVERSITY
    Inventors: Chi-Young Lee, Hsin-Tien Chiu, Po-Chin Chen, Min-Chiao Tsai
  • Patent number: 9255960
    Abstract: The present invention discloses a testing structure and method for interface trap density of gate oxide, relating to the field of quality and reliability researches of MOS devices. The present invention makes the interface traps density tests for gate oxide layers of n-type and p-type MOS devices completed on a same testing structure, this does not only shorten the measurement period by half but also decrease the costs for testing instruments, because the present testing method is based on a simple current-voltage scanning test without using equipments such as pulse generator required in conventional method. The testing results obtained according to the present invention are featured with spectral peak, which facilitates the data analysis and computation.
    Type: Grant
    Filed: February 25, 2013
    Date of Patent: February 9, 2016
    Assignee: Peking University
    Inventors: Yandong He, Ganggang Zhang, Xiaoyan Liu, Xing Zhang
  • Patent number: 9240664
    Abstract: A method and system for performing injects of halogen gas into the chambers of a two chamber gas discharge laser such as a MOPA excimer laser for allowing operation of the laser within acceptable parameters and compensating for ageing effects without the necessity of performing refills is described. A parameter reflecting efficiency of the laser is measured, and the change in the parameter with respect to the length of laser operation is estimated. The change in the parameter with respect to the pressure in one of the chambers is also measured. At a given time, the total change in the value of the parameter is estimated, and from this change in pressure that is needed to reverse the change in the value of the parameter is calculated. The pressure in the chamber is then changed to correct for the amount of time that the laser has been in operation.
    Type: Grant
    Filed: December 28, 2011
    Date of Patent: January 19, 2016
    Assignee: Cymer, LLC
    Inventor: Daniel J. Riggs
  • Patent number: 8941107
    Abstract: With a non-linear element (e.g., a diode) with small reverse saturation current, a power diode or rectifier is provided. A non-linear element includes a first electrode provided over a substrate, an oxide semiconductor film provided on and in contact with the first electrode and having a concentration of hydrogen of 5×1019 atoms/cm3 or less, a second electrode provided on and in contact with the oxide semiconductor film, a gate insulating film covering the first electrode, the oxide semiconductor film, and the second electrode, and third electrodes provided in contact with the gate insulating film and facing each other with the first electrode, the oxide semiconductor film, and the second electrode interposed therebetween or a third electrode provided in contact with the gate insulating film and surrounding the second electrode. The third electrodes are connected to the first electrode or the second electrode. With the non-linear element, a power diode or a rectifier is formed.
    Type: Grant
    Filed: January 23, 2014
    Date of Patent: January 27, 2015
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Shunpei Yamazaki
  • Patent number: 8901691
    Abstract: A touch sensing substrate includes a substrate, a first light sensing element, a second light sensing element and a first bias line. The first light sensing element includes a first gate electrode, a first active pattern overlapping with the first gate electrode, a first source electrode partially overlapping with the first active pattern and a first drain electrode partially overlapping with the first active pattern. The second light sensing element includes a second gate electrode, a second active pattern overlapping with the second gate electrode, a second source electrode partially overlapping with the second active pattern and a second drain electrode partially overlapping with the second active pattern. The first bias line is connected to the first and second gate electrodes.
    Type: Grant
    Filed: September 23, 2011
    Date of Patent: December 2, 2014
    Assignee: Samsung Display Co., Ltd.
    Inventors: Yun-Jong Yeo, Byeong-Hoon Cho, Ki-Hun Jeong, Hong-Kee Chin, Jung-Suk Bang, Woong-Kwon Kim, Sung-Ryul Kim, Hee-Joon Kim, Dae-Cheol Kim, Kun-Wook Han
  • Publication number: 20140291682
    Abstract: Avalanche photodiodes (APDs) having at least one top stressor layer disposed on a germanium (Ge) absorption layer are described herein. The top stressor layer can increase the tensile strain of the Ge absorption layer, thus extending the absorption of APDs to longer wavelengths beyond 1550 nm. In one embodiment, the top stressor layer has a four-layer structure, including an amorphous silicon (Si) layer disposed on the Ge absorption layer; a first silicon dioxide (SiO2) layer disposed on the amorphous Si layer, a silicon nitride (SiN) layer disposed on the first SiO2 layer, and a second SiO2 layer disposed on the SiN layer. The Ge absorption layer can be further doped by p-type dopants. The doping concentration of p-type dopants is controlled such that a graded doping profile is formed within the Ge absorption layer to decrease the dark currents in APDs.
    Type: Application
    Filed: June 13, 2014
    Publication date: October 2, 2014
    Applicant: SIFOTONICS TECHNOLOGIES CO., LTD.
    Inventors: Mengyuan Huang, Pengfei Cai, Dong Pan, Liangbo Wang, Su Li, Tuo Shi, Tzung I Su, Wang Chen, Ching-yin Hong
  • Patent number: 8822992
    Abstract: With a non-linear element (e.g., a diode) with small reverse saturation current, a power diode or rectifier is provided. A non-linear element includes a first electrode provided over a substrate, an oxide semiconductor film provided on and in contact with the first electrode and having a concentration of hydrogen of 5×1019 atoms/cm3 or less, a second electrode provided on and in contact with the oxide semiconductor film, a gate insulating film covering the first electrode, the oxide semiconductor film, and the second electrode, and third electrodes provided in contact with the gate insulating film and facing each other with the first electrode, the oxide semiconductor film, and the second electrode interposed therebetween or a third electrode provided in contact with the gate insulating film and surrounding the second electrode. The third electrodes are connected to the first electrode or the second electrode. With the non-linear element, a power diode or a rectifier is formed.
    Type: Grant
    Filed: January 23, 2014
    Date of Patent: September 2, 2014
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Shunpei Yamazaki
  • Patent number: 8785932
    Abstract: An IR sensing transistor according to an exemplary embodiment of the present invention includes: a light blocking layer formed on a substrate; a gate insulating layer formed on the light blocking layer; a semiconductor formed on the gate insulating layer; a pair of ohmic contact members formed on the semiconductor; a source electrode and a drain electrode formed on respective ones of the ohmic contact members; a passivation layer formed on the source electrode and the drain electrode; and a gate electrode formed on the passivation layer, wherein substantially all of the gate insulating layer lies on the light blocking layer.
    Type: Grant
    Filed: July 13, 2011
    Date of Patent: July 22, 2014
    Assignee: Samsung Display Co., Ltd.
    Inventors: Suk Won Jung, Byeong Hoon Cho, Sung Hoon Yang, Woong Kwon Kim, Sang Youn Han, Dae Cheol Kim, Ki-Hun Jeong, Kyung-Sook Jeon, Seung Mi Seo, Jung-Suk Bang, Kun-Wook Han
  • Patent number: 8766236
    Abstract: A semiconductor device according to an embodiment includes: a substrate; a first semiconductor layer formed on the substrate and having a strain; a second and a third semiconductor layers formed at a distance from each other on the first semiconductor layer, and having a different lattice constant from a lattice constant of the first semiconductor layer; a gate insulating film formed on a first portion of the first semiconductor layer, the first portion being located between the second semiconductor layer and the third semiconductor layer; and a gate electrode formed on the gate insulating film.
    Type: Grant
    Filed: September 19, 2011
    Date of Patent: July 1, 2014
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Koji Usuda, Tsutomu Tezuka
  • Patent number: 8735893
    Abstract: A display device includes an infrared sensing transistor and a visible sensing transistor. The visible sensing transistor includes a semiconductor on a substrate; an ohmic contact on the semiconductor; an etch stopping layer on the ohmic contact; a source electrode and a drain electrode on the etch stopping layer; a passivation layer on the source electrode and the drain electrode; and a gate electrode on the passivation layer. The etch stopping layer may be composed of the same material as the source electrode and the drain electrode. The infrared sensing transistor is similar to the visible sensing transistor except the etch stopping layer is absent.
    Type: Grant
    Filed: April 29, 2013
    Date of Patent: May 27, 2014
    Assignee: Samsung Display Co., Ltd.
    Inventors: Dae-Cheol Kim, Sung-Ryul Kim, Yung-Jong Yeo, Hong-Kee Chin, Ki-Hun Jeong
  • Publication number: 20140138689
    Abstract: A photoelectric conversion material is disclosed in the present invention and comprises at least a cone material. The cone material is composed of an isomer and comprises a plurality of grains. The sizes of the grains are arranged from smaller ones to larger ones along a direction. In the meantime, a method for fabricating the above photoelectric conversion material is also disclosed here. The method comprises the following steps. First, a precursor is provided. The precursor comprises at least a cone material and the cone material is a multilayer structured material, such as sodium titanate and potassium titanate, formed by stacking first materials and second materials. And then, the precursor is annealed to let the second materials leave from the cone material, and the cone material becomes the above photoelectric conversion material with a plurality of grains.
    Type: Application
    Filed: March 7, 2013
    Publication date: May 22, 2014
    Applicant: NATIONAL TSING HUA UNIVERSITY
    Inventor: National Tsing Hua University
  • Patent number: 8704229
    Abstract: Semiconductor devices are formed without zipper defects or channeling and through-implantation and with different silicide thicknesses in the gates and source/drain regions, Embodiments include forming a gate on a substrate, forming a nitride cap on the gate, forming a source/drain region in the substrate on each side of the gate, forming a wet cap fill layer on the source/drain region on each side of the gate, removing the nitride cap from the gate, and forming an amorphized layer in a top portion of the gate. Embodiments include forming the amorphized layer by implanting low energy ions.
    Type: Grant
    Filed: July 26, 2011
    Date of Patent: April 22, 2014
    Assignee: GlobalFoundries Inc.
    Inventors: Peter Javorka, Glyn Braithwaite
  • Patent number: 8643085
    Abstract: A high-voltage-resistant semiconductor component (1) has vertically conductive semiconductor areas (17) and a trench structure (5). These vertically conductive semiconductor areas are formed from semiconductor body areas (10) of a first conductivity type and are surrounded by a trench structure (5) on the upper face (6) of the semiconductor component. For this purpose the trench structure has a base (7) and a wall area (8) and is filled with a material (9) with a relatively high dielectric constant (?r). The base area (7) of the trench structure (5) is provided with a heavily doped semiconductor material (11) of the same conductivity type as the lightly doped semiconductor body areas (17), and/or having a metallically conductive material (12).
    Type: Grant
    Filed: September 23, 2005
    Date of Patent: February 4, 2014
    Assignee: Infineon Technologies AG
    Inventor: Frank Pfirsch
  • Patent number: 8628995
    Abstract: A tandem thin-film silicon solar cell comprises a transparent substrate, a first unit cell positioned on the transparent substrate, the first unit cell comprising a p-type window layer, an i-type absorber layer and an n-type layer, an intermediate reflection layer positioned on the first unit cell, the intermediate reflection layer including a hydrogenated n-type microcrystalline silicon oxide of which the oxygen concentration is profiled to be gradually increased and a second unit cell positioned on the intermediate reflection layer, the second unit cell comprising a p-type window layer, an i-type absorber layer and an n-type layer.
    Type: Grant
    Filed: November 30, 2011
    Date of Patent: January 14, 2014
    Assignee: Intellectual Discovery Co., Ltd.
    Inventor: Seung-Yeop Myong
  • Patent number: 8617968
    Abstract: A method of forming a semiconductor device that includes providing a first strained layer of a first composition semiconductor material over a dielectric layer. A first portion of the layer of the first composition semiconductor material is etched or implanted to form relaxed islands of the first composition semiconductor material. A second composition semiconductor material is epitaxially formed over the relaxed island of the first composition semiconductor material. The second composition semiconductor material is intermixed with the relaxed islands of the first composition semiconductor material to provide a second strained layer having a different strain than the first strained layer.
    Type: Grant
    Filed: June 18, 2012
    Date of Patent: December 31, 2013
    Assignee: International Business Machines Corporation
    Inventors: Kangguo Cheng, Bruce B. Doris, Pouya Hashemi, Ali Khakifirooz
  • Publication number: 20130234142
    Abstract: A display device includes an infrared sensing transistor and a visible sensing transistor. The visible sensing transistor includes a semiconductor on a substrate; an ohmic contact on the semiconductor; an etch stopping layer on the ohmic contact; a source electrode and a drain electrode on the etch stopping layer; a passivation layer on the source electrode and the drain electrode; and a gate electrode on the passivation layer. The etch stopping layer may be composed of the same material as the source electrode and the drain electrode. The infrared sensing transistor is similar to the visible sensing transistor except the etch stopping layer is absent.
    Type: Application
    Filed: April 29, 2013
    Publication date: September 12, 2013
    Applicant: Samsung Display Co., Ltd.
    Inventors: Dae-Cheol KIM, Sung-Ryul KIM, Yung-Jong YEO, Hong-Kee CHIN, Ki-Hun JEONG
  • Patent number: 8507911
    Abstract: A thin film transistor (TFT) and an organic light emitting display apparatus are provided. The TFT includes: a substrate; a gate electrode on the substrate; an active layer insulated from the gate electrode; source/drain electrodes electrically connected to the active layer; a first insulating film on the source/drain electrodes; a light blocking layer on the first insulating film; and a second insulating film on the light blocking layer.
    Type: Grant
    Filed: November 10, 2010
    Date of Patent: August 13, 2013
    Assignee: Samsung Display Co., Ltd.
    Inventors: Eun-Hyun Kim, Jong-Han Jeong, Yeon-Gon Mo
  • Patent number: 8502065
    Abstract: Disclosed is a photovoltaic device. The photovoltaic device includes: a first electrode and a second electrode; a first unit cell and a second unit cell which are placed between the first electrode and the second electrode and include a first conductive semiconductor layer, an intrinsic semiconductor layer and a second conductive semiconductor layer; and an intermediate reflector which is placed between the first unit cell and the second unit cell, and includes a hydrogenated amorphous carbon layer.
    Type: Grant
    Filed: January 9, 2011
    Date of Patent: August 6, 2013
    Assignee: KISCO
    Inventor: Seung-Yeop Myong
  • Patent number: 8487307
    Abstract: A semiconductor arrangement is disclosed. One embodiment includes a first semiconductor layer including a first and second component zone that form a pn-junction or a Schottky-junction. A second semiconductor layer includes a drift control zone adjacent to the second component zone. A dielectric layer separates the first semiconductor layer from the second semiconductor layer. A rectifying element is coupled between the drift control zone and the second component zone.
    Type: Grant
    Filed: December 21, 2011
    Date of Patent: July 16, 2013
    Assignee: Infineon Technologies Austria AG
    Inventors: Joachim Weyers, Anton Mauder, Franz Hirler, Paul Kuepper
  • Patent number: 8470635
    Abstract: Subject matter disclosed herein relates to a method of manufacturing a semiconductor integrated circuit device, and more particularly to a method of fabricating a phase change memory device.
    Type: Grant
    Filed: November 30, 2009
    Date of Patent: June 25, 2013
    Assignee: Micron Technology, Inc.
    Inventors: Soonwoo Cha, Tim Minvielle, Jong Won Lee, Jinwook Lee
  • Patent number: 8461590
    Abstract: An adverse effect of parasitic capacitance on optical data output from a photodetector circuit is suppressed. A photodetector circuit includes a photoelectric conversion element; a first field-effect transistor; a second field-effect transistor; a first conductive layer functioning as a gate of the first field-effect transistor; an insulating layer provided over the first conductive layer; a semiconductor layer overlapping with the first conductive layer with the insulating layer interposed therebetween; a second conductive layer electrically connected to the semiconductor layer; and a third conductive layer electrically connected to the semiconductor layer, whose pair of side surfaces facing each other overlaps with at least one conductive layer including the first conductive layer with the insulating layer interposed therebetween, and which functions as the other of the source and the drain of the first field-effect transistor.
    Type: Grant
    Filed: December 7, 2011
    Date of Patent: June 11, 2013
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Hikaru Tamura, Yoshiyuki Kurokawa, Takayuki Ikeda
  • Patent number: 8431928
    Abstract: Provided herein are PIN structures including a layer of amorphous n-type silicon, a layer of intrinsic GaAs disposed over the layer of amorphous n-type silicon, and a layer of amorphous p-type silicon disposed over the layer of intrinsic GaAs. The layer of intrinsic GaAs may be engineered by the disclosed methods to exhibit a variety of structural properties that enhance light absorption and charge carrier mobility, including oriented polycrystalline intrinsic GaAs, embedded particles of intrinsic GaAs, and textured surfaces. Also provided are devices incorporating the PIN structures, including photovoltaic devices.
    Type: Grant
    Filed: December 15, 2011
    Date of Patent: April 30, 2013
    Assignee: The University of Utah Research Foundation
    Inventors: Ashutosh Tiwari, Makarand Karmarkar, Nathan Wheeler Gray
  • Patent number: 8415787
    Abstract: The present invention relates to a heat dissipator that includes a conductive substrate and a plurality of nanostructures supported by the conductive substrate. The nanostructures are at least partly embedded in an insulator. Each of the nanostructures includes a plurality of intermediate layers on the conductive substrate. At least two of the plurality of intermediate layers are interdiffused, and material of the at least two of the plurality of intermediate layers that are interdiffused is present in the nanostructure.
    Type: Grant
    Filed: May 21, 2012
    Date of Patent: April 9, 2013
    Assignee: Smoltek AB
    Inventor: Mohammad Shafiqul Kabir
  • Patent number: 8410480
    Abstract: The present invention discloses a CMOS-MEMS cantilever structure. The CMOS-MEMS cantilever structure includes a substrate, a circuit structure, and a cantilever beam. The substrate has a circuit area and a sensor unit area defined thereon. The circuit structure is formed in the circuit area. The cantilever beam is disposed in the sensor unit area with one end floating above the substrate and the other end connecting to the circuit structure. With the above arrangement, the manufacturing process of CMOS-MEMS cantilever structure of this invention can be simplified. Furthermore, the structure of the cantilever beam is thinned down and therefore has a higher sensitivity.
    Type: Grant
    Filed: February 19, 2010
    Date of Patent: April 2, 2013
    Assignee: National Chip Implementation Center National Applied Research Laboratories
    Inventors: Chin-Fong Chiu, Ying Zong Juang, Hann Huei Tsai, Sheng-Hsiang Tseng, Chen-Fu Lin
  • Patent number: 8386883
    Abstract: A phase-change memory (PCM) includes a matrix of storage cells, including at least a first group with at least one cell. Each cell includes a phase change material having at least a first resistance value and a second resistance value, such that the first group can have an identical message encoded therein in at least a first way and a second way. The memory also includes a controller configured to encode the identical message in the at least first group the first or second way, based on which way causes the least amount of writing cost, given current levels of the group. Another embodiment of memory includes a matrix of storage cells, including at least a first group with at least one cell. Each of the storage cells has at least two levels, such that each of the storage cells can have an identical message encoded therein in at least a first way and a second way (the cells can be PCM or another technology).
    Type: Grant
    Filed: February 24, 2009
    Date of Patent: February 26, 2013
    Assignee: International Business Machines Corporation
    Inventors: Michele Franceschini, John Peter Karidis, Luis A Lastras-Montano, Thomas Mittelholzer, Mark N Wegman
  • Patent number: 8362476
    Abstract: A cubic epitaxial article and electronic devices therefrom includes a single crystal cubic oxide substrate having a substrate band gap and a top surface. An epitaxial cubic oxide alloy layer that includes at least one transition metal or group IIA metal disposed on the top surface of the substrate. The epitaxial cubic oxide alloy layer has a band gap that is different than the substrate band gap and has a lattice that is lattice matched within 5% to a lattice of the single crystal cubic oxide substrate.
    Type: Grant
    Filed: March 18, 2010
    Date of Patent: January 29, 2013
    Assignee: University of Central Florida Research Foundation, Inc.
    Inventor: Winston V. Schoenfeld
  • Patent number: 8319299
    Abstract: A process for forming at least one transistor on a substrate is described. The substrate comprises a polyimide and a nanoscopic filler. The polyimide is derived substantially or wholly from rigid rod monomers and the nanoscopic filler has an aspect ratio of at least 3:1. The substrates of the present disclosure are particularly well suited for thin film transistor applications, due at least in part to high resistance to hygroscopic expansion and relatively high levels of thermal and dimensional stability.
    Type: Grant
    Filed: November 20, 2009
    Date of Patent: November 27, 2012
    Inventors: Brian C. Auman, Salah Boussaad, Thomas Edward Carney, Kostantinos Kourtakis
  • Patent number: 8283669
    Abstract: An object is to reduce the adverse influence which a portion of a gate insulating layer where the thickness has decreased, that is, a step portion, has on semiconductor element characteristics so that the reliability of the semiconductor element is improved. A semiconductor layer is formed over an insulating surface; a side surface of the semiconductor layer is oxidized using wet oxidation to form a first insulating layer; a second insulating layer is formed over the semiconductor layer and the first insulating layer; and a gate electrode is formed over the semiconductor layer and the first insulating layer with the second insulating layer interposed therebetween.
    Type: Grant
    Filed: December 9, 2010
    Date of Patent: October 9, 2012
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Hideto Ohnuma
  • Patent number: 8237161
    Abstract: Amorphous semiconductor films with enhanced charged carrier transport are disclosed. Also disclosed is a method for fabricating and treating the film to produce the enhanced transport. Also disclosed are semiconductor p-n junctions fabricated with the films which demonstrate the enhanced transport. The films are amorphous and include boron, carbon, and hydrogen.
    Type: Grant
    Filed: August 10, 2010
    Date of Patent: August 7, 2012
    Assignee: North Dakota State University Research Foundation
    Inventors: Anthony N. Caruso, Joseph A. Sandstrom, David A. Bunzow
  • Patent number: 8212252
    Abstract: An object of the present invention is to provide a new light-emitting device with the use of an amorphous oxide. The light-emitting device has a light-emitting layer existing between first and second electrodes and a field effect transistor, of which the active layer is an amorphous.
    Type: Grant
    Filed: September 15, 2010
    Date of Patent: July 3, 2012
    Assignees: Canon Kabushiki Kaisha, Tokyo Institute of Technology
    Inventors: Tohru Den, Tatsuya Iwasaki, Hideo Hosono, Toshio Kamiya, Kenji Nomura
  • Publication number: 20120138929
    Abstract: An IR sensing transistor according to an exemplary embodiment of the present invention includes: a light blocking layer formed on a substrate; a gate insulating layer formed on the light blocking layer; a semiconductor formed on the gate insulating layer; a pair of ohmic contact members formed on the semiconductor; a source electrode and a drain electrode formed on respective ones of the ohmic contact members; a passivation layer formed on the source electrode and the drain electrode; and a gate electrode formed on the passivation layer, wherein substantially all of the gate insulating layer lies on the light blocking layer.
    Type: Application
    Filed: July 13, 2011
    Publication date: June 7, 2012
    Inventors: Suk Won JUNG, Byeong Hoon CHO, Sung Hoon YANG, Woong Kwon KIM, Sang Youn HAN, Dae Cheol KIM, Ki-Hun JEONG, Kyung-Sook JEON, Seung Mi SEO, Jung-Suk BANG, Kun-Wook HAN
  • Patent number: 8189131
    Abstract: A thin-film transistor (TFT) includes a gate electrode, a semiconductor pattern, a source electrode, and a drain electrode. The semiconductor pattern includes an active layer being overlapped with the gate electrode and a low band gap portion having a lower energy band gap than the active layer. The source and drain electrodes are spaced apart from each other to be overlapped with the semiconductor pattern. Therefore, the semiconductor pattern includes a low band gap portion having a lower energy band gap than the active layer, so that electron mobility may be increased in a channel formed along the low band gap portion so that electric characteristics of the TFT may be enhanced.
    Type: Grant
    Filed: August 8, 2008
    Date of Patent: May 29, 2012
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Kap-Soo Yoon, Sung-Hoon Yang, Sung-Ryul Kim, Hwa-Yeul Oh, Jae-Ho Choi, Yong-Mo Choi
  • Patent number: 8183659
    Abstract: The present invention provides for nanostructures grown on a conducting or insulating substrate, and a method of making the same. The nanostructures grown according to the claimed method are suitable for interconnects and/or as heat dissipators in electronic devices.
    Type: Grant
    Filed: July 2, 2010
    Date of Patent: May 22, 2012
    Inventor: Mohammad Shafiqul Kabir
  • Patent number: 8164092
    Abstract: Provided herein are PIN structures including a layer of amorphous n-type silicon, a layer of intrinsic GaAs disposed over the layer of amorphous n-type silicon, and a layer of amorphous p-type silicon disposed over the layer of intrinsic GaAs. The layer of intrinsic GaAs may be engineered by the disclosed methods to exhibit a variety of structural properties that enhance light absorption and charge carrier mobility, including oriented polycrystalline intrinsic GaAs, embedded particles of intrinsic GaAs, and textured surfaces. Also provided are devices incorporating the PIN structures, including photovoltaic devices.
    Type: Grant
    Filed: January 12, 2011
    Date of Patent: April 24, 2012
    Assignee: The University of Utah Research Foundation
    Inventors: Ashutosh Tiwari, Makarand Karmarkar, Nathan Wheeler Gray
  • Patent number: 8154024
    Abstract: An amorphous oxide containing hydrogen (or deuterium) is applied to a channel layer of a transistor. Accordingly, a thin film transistor having superior TFT properties can be realized, the superior TFT properties including a small hysteresis, normally OFF operation, a high ON/OFF ratio, a high saturated current, and the like. Furthermore, as a method for manufacturing a channel layer made of an amorphous oxide, film formation is performed in an atmosphere containing a hydrogen gas and an oxygen gas, so that the carrier concentration of the amorphous oxide can be controlled.
    Type: Grant
    Filed: April 19, 2011
    Date of Patent: April 10, 2012
    Assignee: Canon Kabushiki Kaisha
    Inventor: Tatsuya Iwasaki
  • Publication number: 20120033161
    Abstract: A photosensor includes a substrate, a gate line, and a data line disposed on the substrate. A thin film transistor is connected to the gate line and the data line. A first photo-sensing member is disposed on the substrate, and a first electrode is connected to the thin film transistor and the first photo-sensing member. A second photo-sensing member is disposed on the first photo-sensing member, and a second electrode is connected to the first electrode and the second photo-sensing member.
    Type: Application
    Filed: December 3, 2010
    Publication date: February 9, 2012
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Sang-Youn HAN, Sung-Hoon YANG, Suk-Won JUNG, Kyung-Sook JEON, Seung Mi SEO, Mi-Seon SEO
  • Patent number: 8044445
    Abstract: A photoelectric conversion device includes a thin film transistor that is placed on a substrate, a photodiode that is connected to a drain electrode of the thin film transistor and includes an upper electrode, a lower electrode and a photoelectric conversion layer placed between the upper and lower electrodes, a first interlayer insulating film that covers at least the upper electrode, a second interlayer insulating film that is placed in an upper layer of the first interlayer insulating film and covers the thin film transistor and the photodiode, and a line that is connected to the upper electrode through a contact hole disposed in the first interlayer insulating film and the second interlayer insulating film.
    Type: Grant
    Filed: September 9, 2009
    Date of Patent: October 25, 2011
    Assignee: Mitsubishi Electric Corporation
    Inventors: Masami Hayashi, Takashi Miyayama
  • Patent number: 8026535
    Abstract: In a thin film transistor, a semiconductor layer containing Si and Ge is applied, a Ge concentration of this semiconductor layer is high at the side of the insulating substrate, and crystalline orientation of the semiconductor layer indicates a random orientation in a region of 20 nm from the side of the insulating substrate, and indicates a (111), (110) or (100) preferential orientation at the film surface side of the semiconductor layer.
    Type: Grant
    Filed: January 24, 2008
    Date of Patent: September 27, 2011
    Assignees: Hitachi, Ltd., Tokyo Institute of Technology
    Inventors: Masatoshi Wakagi, Junichi Hanna
  • Patent number: 8013424
    Abstract: A semiconductor device according to an embodiment includes: a semiconductor substrate; a gate electrode formed on the semiconductor substrate via a gate insulating film; a channel region formed in a region of the semiconductor substrate below the gate electrode; an epitaxial crystal layer containing a conductive impurity, which is formed sandwiching the channel region and has a function as a source region and a drain region, and formed on a recess in the semiconductor substrate; and a growth suppressing portion formed on the recess in the semiconductor substrate, and configured to suppress an epitaxial growth of a crystal in the epitaxial layer from the semiconductor substrate.
    Type: Grant
    Filed: August 19, 2008
    Date of Patent: September 6, 2011
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Hiroki Okamoto
  • Patent number: RE46515
    Abstract: A solar cell is discussed. The solar cell includes a substrate of a first conductive type, an emitter region of a second conductive type opposite the first conductive type that is positioned on the substrate, a first field region of the first conductive type that is positioned on the substrate to be separated from the emitter region, a first electrode electrically connected to the emitter region, a second electrode electrically connected to the first field region, and an insulating region positioned on at least one of the emitter region and the first field region.
    Type: Grant
    Filed: September 2, 2015
    Date of Patent: August 15, 2017
    Assignee: LG ELECTRONICS INC.
    Inventors: Kwangsun Ji, Heonmin Lee, Hojung Syn, Wonseok Choi, Junghoon Choi, Hyunjin Yang
  • Patent number: RE47484
    Abstract: A solar cell is discussed. The solar cell includes a substrate of a first conductive type, an emitter region of a second conductive type opposite the first conductive type that is positioned on the substrate, a first field region of the first conductive type that is positioned on the substrate to be separated from the emitter region, a first electrode electrically connected to the emitter region, a second electrode electrically connected to the first field region, and an insulating region positioned on at least one of the emitter region and the first field region.
    Type: Grant
    Filed: July 3, 2017
    Date of Patent: July 2, 2019
    Assignee: LG ELECTRONICS INC.
    Inventors: Kwangsun Ji, Heonmin Lee, Hojung Syn, Wonseok Choi, Junghoon Choi, Hyunjin Yang