Amorphous Semiconductor Is Alloy Or Contains Material To Change Band Gap (e.g., Si X Ge 1-x , Sin Y ) Patents (Class 257/55)
  • Publication number: 20020113240
    Abstract: A semiconductor device includes a SiC substrate and an ohmic electrode, a semiconductor member including a SiC member and a SiGe member being formed between the SiC substrate and the ohmic electrode, wherein the semiconductor member is composed of a SiGe member formed on a SiC member, and the ohmic electrode is formed on the SiGe member, whereby the ohmic electrode with a low resistance can be formed on the SiC substrate without conducting a heat treatment at a high temperature.
    Type: Application
    Filed: February 19, 2002
    Publication date: August 22, 2002
    Applicant: Matsushita Electric Industrial Co., Ltd.
    Inventor: Yorito Ota
  • Publication number: 20020104993
    Abstract: A semiconductor structure including a relaxed Si1−xGex layer on a substrate, a strained channel layer on said relaxed Si1−xGex layer, and a sacrificial Si1−yGey layer. The sacrificial Si1−yGey layer is removed before providing a dielectric layer. The dielectric layer includes a gate dielectric of a MISFET. In alternative embodiments, the structure includes a Si1−yGey spacer layer and a Si layer.
    Type: Application
    Filed: August 6, 2001
    Publication date: August 8, 2002
    Inventors: Eugene A. Fitzgerald, Richard Hammond, Matthew Currie
  • Patent number: 6384319
    Abstract: The film thickness of a p-type semiconductor was adjusted in order to achieve 0.85-0.99 times the maximum pre-irradiation open-circuit voltage. In order to achieve 0.85-0.99 times the maximum pre-irradiation open-circuit voltage, it was also shown to be favorable to control acceptor impurity levels in p-type semiconductors. Irradiation conditions of more than 10 hours at 1 SUN or (light intensity [SUN])2×10 or more (time [h])>10 were utilized.
    Type: Grant
    Filed: March 15, 2000
    Date of Patent: May 7, 2002
    Assignee: Fuji Electric & Co., Ltd.
    Inventors: Toshiaki Sasaki, Shinji Fujikake
  • Publication number: 20020036289
    Abstract: Disclosed is a polysilicon film having high crystal orientation, low in nonuniformity in the crystal grain sizes, having the surface protrusion suppressed and, thus, adapted for use in a liquid crystal display. For manufacturing such an excellent polysilicon film, a native oxide layer formed on a surface of the amorphous silicon film is completely removed by using a hydrofluoric acid solution, followed by immersing the amorphous silicon film in an H2O2 solution for a short time so as to newly form an extremely thin oxide layer on the surface of the amorphous silicon film, prior to a crystallizing processing performed by a laser beam irradiation.
    Type: Application
    Filed: February 28, 2001
    Publication date: March 28, 2002
    Inventors: Takuo Tamura, Kiyoshi Ogata, Yoichi Takahara, Hironaru Yamaguchi, Yoshinobu Kimura
  • Patent number: 6359290
    Abstract: A method of making a diode and the diode wherein there is provided a substrate of p-type group II-VI semiconductor material and an electrically conductive material capable of forming an ohmic contact with the substrate is forced into the lattice of the substrate to create an n-type region in the substrate in contact with the material and forming an electrical contact to the p-type region of said substrate. The substrate is preferably HgCdTe and the electrically conductive material is preferably tungsten or tin coated tungsten or tungsten coated with a mercury amalgam.
    Type: Grant
    Filed: February 6, 1996
    Date of Patent: March 19, 2002
    Assignee: Raytheon Company
    Inventor: John C. Ehmke
  • Patent number: 6346716
    Abstract: A photoelectric conversion device has a non-single-crystal semiconductor laminate member formed on a substrate having a conductive surface, and a conductive layer formed on the non-single-crystal semiconductor laminate member. The non-single-crystal semiconductor laminate member has such a structure that a first non-single-crystal semiconductor layer having a P or N first conductivity type, an I-type second non-single-crystal semiconductor layer and a third non-single-crystal semiconductor layer having a second conductivity type opposite the first conductivity type are laminated in this order. The first (or third) non-single-crystal semiconductor layer is disposed on the side on which light is incident, and is P-type. The I-type non-single-crystal semiconductor layer has introduced thereinto a P-type impurity, such as boron which is distributed so that its concentration decreases towards the third (or first) non-single-crystal semiconductor layer in the thickwise direction of the I-type layer.
    Type: Grant
    Filed: December 19, 1997
    Date of Patent: February 12, 2002
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Shunpei Yamazaki
  • Publication number: 20010050363
    Abstract: In the case where a Ta2O5 thin film having double bond Ta═O is employed for a capacitative insulating film, Rapid Thermal Anneal in oxygen and UV/O3 treatment are executed at suitable temperature and in suitable time. Whether or not absorption peak which appears in 2340 cm−1 exists and whether it is large or small are monitored by measuring a transmission infrared absorption spectrum of a Ta2O5 thin film with Fourier Transform Infrared Spectroscopy. In the case where a Ta2O5 thin film, in which an abundance ratio of oxygen in a three coordinate bonding state is large, is employed for a capacitative insulating film, an intensity ratio of each double peak which appears in 510 cm−1 and 570 cm−1 is measured as well, so that the film whose ratio (510/570) is larger than another one is used as an character to improve quality of a film.
    Type: Application
    Filed: June 6, 2001
    Publication date: December 13, 2001
    Applicant: NEC Corporation
    Inventor: Haruhiko Ono
  • Patent number: 6326667
    Abstract: The invention is intended to form, on an insulating layer, a thin SiGe layer serving as an underlying layer for obtaining a strained silicon layer, and to provide a satisfactory strained Si layer. A SiGe layer 13 is formed on a Si substrate 11 and an oxygen ion implantation is effected with ensuring the detainment within the layer thickness of the SiGe layer 13. The SiGe layer 13 is lattice-relaxed by a heat treatment and a buried insulating layer 15 is formed simultaneously in the SiGe layer 13. A strained Si layer 17 is re-grown on the lattice-relaxed SiGe layer 13.
    Type: Grant
    Filed: September 8, 2000
    Date of Patent: December 4, 2001
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Naoharu Sugiyama, Tomohisa Mizuno, Shinichi Takagi, Atsushi Kurobe
  • Patent number: 6310363
    Abstract: In those thin-film transistors (TFTs) employing as its active layer a silicon film crystallized using a metal element, the objective is to eliminate bad affection of such metal element to the TFT characteristics. To this end, in a TFT having as its active layer a crystalline silicon film that was crystallized using nickel (Ni), those regions corresponding to the source/drain thereof are doped with phosphorus; thereafter, thermal processing is performed. During this process, nickel residing in a channel formation region is “gettered” into previously phosphorus-doped regions. With such an arrangement, it becomes possible to reduce the Ni concentration in certain regions in which lightly-doped impurity regions will be formed later, which in turn enables suppression of affection to TFT characteristics.
    Type: Grant
    Filed: February 29, 2000
    Date of Patent: October 30, 2001
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Hideto Ohnuma, Shunpei Yamazaki
  • Patent number: 6297080
    Abstract: A method of crystallizing a silicon film and a method of manufacturing a liquid crystal display apparatus which uses the Joule heat of a heat generating conductive layer to increase the temperature of a silicon film for expediting silicon crystallization includes forming an amorphous silicon film on an insulating substrate, forming a heat generating conductive layer over the amorphous silicon film, and applying a voltage to the heat generating conductive layer wherein electric current flows through the heat generating conductive layer.
    Type: Grant
    Filed: November 8, 1999
    Date of Patent: October 2, 2001
    Assignee: LG. Philips LCD Co. Ltd.
    Inventors: Kyung-Eon Lee, Jae-Beom Choi
  • Patent number: 6288325
    Abstract: High performance photovoltaic modules are produced with improved interconnects by a special process. Advantageously, the photovoltaic modules have a dual layer back (rear) contact and a front contact with at least one layer. The front contact and the inner layer of the back contact can comprise a transparent conductive oxide. The outer layer of the back contact can comprise a metal or metal oxide. The front contact can also have a dielectric layer. In one form, the dual layer back contact comprises a zinc oxide inner layer and an aluminum outer layer and the front contact comprises a tin oxide inner layer and a silicon dioxide dielectric outer layer. One or more amorphous silicon-containing thin film semiconductors can be deposited between the front and back contacts. The contacts can be positioned between a substrate and an optional superstrate.
    Type: Grant
    Filed: May 4, 2000
    Date of Patent: September 11, 2001
    Assignee: BP Corporation North America Inc.
    Inventors: Kai W. Jansen, Nagi Maley
  • Patent number: 6259116
    Abstract: A semiconductor memory device using silicon-rich amorphous silicon alloy material memory elements that are electrically programmable by means of current induced conductivity comprises a layer (10) of the alloy material on opposing sides of which sets of input and output contacts (16, 18) are provided, and discrete conductive elements (20) within the layer which serve as nodes and define programmable conductive paths between input and output contacts to create a three dimensional memory network. The conductive elements can be arranged at one or more levels within the thickness of the alloy layer and preferably are of defined shape forming a predetermined 2D array at each level.
    Type: Grant
    Filed: October 22, 1998
    Date of Patent: July 10, 2001
    Assignee: U.S. Philips Corporation
    Inventor: John M. Shannon
  • Patent number: 6251751
    Abstract: A method for forming buried oxide regions below a single crystal semiconductor layer incorporating the steps of forming epitaxial layers having different rates of oxidation with the lower layer having a faster rate of oxidation and oxidizing the layers through an opening in a mask. A plurality of oxide isolated FET's may be formed. The invention reduces the problem of source/drain parasitic capacitance and short channel effects while isolating FET's and eliminating floating body effects of an FET by selectively oxidizing semiconductor layers.
    Type: Grant
    Filed: April 13, 1999
    Date of Patent: June 26, 2001
    Assignee: International Business Machines Corporation
    Inventors: Jack Oon Chu, Khalid Ezzeldin Ismail, Kim Yang Lee, John Albrecht Ott
  • Patent number: 6242686
    Abstract: A photovoltaic device have a pin junction of a p-layer, an i-layer and an n-layer, wherein the p-layer includes a first p-layer and a second p-layer thereover, the first p-layer having a thickness of 5 nm or less and being uniformly doped with a p-type impurity, and the second p-layer being formed by decomposition of a gas which does not positively incorporate a p-type impurity.
    Type: Grant
    Filed: June 11, 1999
    Date of Patent: June 5, 2001
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Katsushi Kishimoto, Takanori Nakano, Hitoshi Sannomiya, Katsuhiko Nomoto
  • Patent number: 6215154
    Abstract: A thin film transistor (TFT) which may be used as a pixel drive element in an active matrix LCD display includes a pair of side wall spacers adjacent to the opposing side walls of its gate electrode. The side wall spacers provide the gate electrode with a substantially rectangular cross section, such that the gate electrode has a substantially constant thermal conductivity over its area. The TFT has a uniform device characteristic.
    Type: Grant
    Filed: February 13, 1998
    Date of Patent: April 10, 2001
    Assignees: Sanyo Electric co., Ltd., Sony Corporation
    Inventors: Satoshi Ishida, Yasuo Nakahara, Hiroyuki Kuriyama, Tsutomu Yamada, Kiyoshi Yoneda, Yasushi Shimogaichi
  • Patent number: 6184541
    Abstract: On the polycrystal semiconductor film 3 formed on the insulating substrate 1, the source 6 and drain 7 in LDD structure having a low concentration region 4 and a high concentration region 5 are formed. The region 4 has a low impurity concentration, and the region 5 has a high impurity concentration. The length of the low concentration region 4 measured from the edge of gate insulating film 9 is not smaller than the average grain size of the polycrystal semiconductor film 3. The LCD device employing the TFT thus constructed is free from white spots (micro brighter spots) in a high temperature atmosphere.
    Type: Grant
    Filed: December 3, 1998
    Date of Patent: February 6, 2001
    Assignee: Matsushita Electronics Corporation
    Inventors: Hitoshi Oka, Yutaka Ito
  • Patent number: 6180982
    Abstract: To provide a thin film transistor having a low OFF characteristic and to provide P-channel type and N-channel type thin film transistors where a difference in characteristics of the P-channel type and the N-channel type thin film transistors is corrected, a region 145 having a P-type behavior more potential than that of a drain region 146 is arranged between a channel forming region 134 and the drain region 146 in the P-channel type thin film transistor whereby the P-channel type thin film transistor having the low OFF characteristic can be provided and a low concentration impurity region 136 is arranged between a channel forming region 137 and a drain region 127 in the N-channel type thin film transistor whereby the N-channel type thin film transistor having the low OFF characteristic and where deterioration is restrained can be provided.
    Type: Grant
    Filed: March 20, 1997
    Date of Patent: January 30, 2001
    Assignee: Semiconductor Energy Laboratory Co, Ltd
    Inventors: Hongyong Zhang, Satoshi Teramoto
  • Patent number: 6166395
    Abstract: In one aspect, the invention includes a semiconductor processing method comprising depositing a silicon layer over a substrate at different deposition temperatures which at least include increasing the deposition temperature through a range of from about 550.degree. C. to about 560.degree. C.
    Type: Grant
    Filed: March 1, 1999
    Date of Patent: December 26, 2000
    Assignee: Micron Technology, Inc.
    Inventors: Keith Smith, Phillip G. Wald
  • Patent number: 6140671
    Abstract: A capacitor in a semiconductor device having a dielectric film formed of high dielectric material and a manufacturing method therefor are provided. The capacitor consists of electrodes including a dielectric film and an amorphous SiC layer. Thus, the diffusion of oxygen atoms through a grain boundary into an underlayer and the formation of an oxide layer on the surface of the SiC layer can both be prevented, providing for a highly reliable capacitor electrode and an equivalent oxide thickness which is no thicker than required.
    Type: Grant
    Filed: September 21, 1998
    Date of Patent: October 31, 2000
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Sang-in Lee
  • Patent number: 6133620
    Abstract: A semiconductor device comprising a thin film transistor, and a process for fabricating the same, the process comprising: a first step of forming an island-like semiconductor layer, a gate insulating film covering the semiconductor layer, and a gate electrode comprising a material containing aluminum as the principal component formed on the gate insulating film; a second step of introducing impurities into the semiconductor layer in a self-aligned manner by using the gate electrode as the mask; a third step of forming an interlayer dielectric to cover the gate electrode, and forming a contact hole in at least one of source and drain; a fourth step of forming over the entire surface, a film containing aluminum as the principal component, and then forming an anodic oxide film by anodically oxidizing the film containing aluminum as the principal component; a fifth step of etching the film containing aluminum as the principal component and the anodic oxide film, thereby forming a second layer interconnection cont
    Type: Grant
    Filed: December 29, 1998
    Date of Patent: October 17, 2000
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Hideki Uochi
  • Patent number: 6107639
    Abstract: An insulating film 103 for making an under insulating layer 104 is formed on a quartz or semiconductor substrate 100. Recesses 105a to 105d corresponding to recesses 101a to 101d of the substrate 100 are formed on the surface of the insulating film 103. The surface of this insulating film 103 is flattened to form the under insulating layer 104. By this flattening process, the distance L1, L2, . . . , Ln between the recesses 106a, 106b, 106d of the under insulating layer 104 is made 0.3 .mu.m or more, and the depth of the respective recesses is made 10 nm or less. The root-mean-square surface roughness of the surface of the under insulating film 104 is made 0.3 nm or less. By this, in the recesses 106a, 106b, 106d, it can be avoided to block crystal growth of the semiconductor thin film, and crystal grain boundaries can be substantially disappeared.
    Type: Grant
    Filed: August 25, 1998
    Date of Patent: August 22, 2000
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Akiharu Miyanaga, Toru Mitsuki, Hisashi Ohtani
  • Patent number: 6100466
    Abstract: Provided is a method of forming a microcrystalline silicon film by a plasma CVD, which comprises introducing a high frequency electromagnetic wave into a film forming space through an electrode to induce a plasma thereby forming a deposited film on a substrate, wherein the relation of 400<Q<10000 is satisfied when Q is defined as Q=P.multidot.f.sup.2 /d where d (cm) is the distance between the substrate and the electrode, P (Torr) is the pressure of the film forming space during formation of the deposited film, and f (MHz) is the frequency of the high frequency electromagnetic wave-forming method of microcrystalline silicon film for forming a microcrystalline silicon film by plasma CVD, wherein Q defined as Q=P.multidot.f.sup.
    Type: Grant
    Filed: November 23, 1998
    Date of Patent: August 8, 2000
    Assignee: Canon Kabushiki Kaisha
    Inventor: Tomonori Nishimoto
  • Patent number: 6097037
    Abstract: A transistor includes an MILC (metal-induced lateral crystallization) region formed on a substrate with a semiconductor material and including a channel region, and a plurality of MIC (metal-induced crystallization) regions formed on the sides of the MILC region with a semiconductor material, wherein at least one boundary between the MILC region and one of the MIC regions is located outside the channel region. A method of fabricating a transistor includes the steps of forming an MILC (metal-induced lateral crystallization) region on a substrate using a semiconductor material, the MILC region including a channel region, and forming a plurality of MIC (metal-induced crystallization) regions formed on sides of the MILC region using a semiconductor material, wherein at least one boundary between the MILC region and one of the MIC regions is located outside the channel region.
    Type: Grant
    Filed: May 8, 1998
    Date of Patent: August 1, 2000
    Inventors: Seung-ki Joo, Tae-Hyung Ihn
  • Patent number: 6093936
    Abstract: A silicon semiconductor integrated circuit includes an insulative field oxidation layer which substantially does not encroach under active circuit elements of the integrated circuit. The field oxidation layer is formed of oxidized amorphous silicon created by bombardment of a silicon substrate with noble gas ions. The amorphous silicon oxidizes at a rate much faster than crystalline silicon so that when the field oxidation layer is formed crystalline silicon foundations for the active circuit elements are left substantially intact. The crystalline silicon foundations are formed by using appropriate shield elements during the noble gas ion bombardment. This noble gas ion bombardment also has the advantage of eliminating dislocation defects which may be present in the field oxidation area so that these defects do not propagate into the crystal lattice of the silicon during subsequent heating and cooling cycles.
    Type: Grant
    Filed: August 19, 1997
    Date of Patent: July 25, 2000
    Assignee: LSI Logic Corporation
    Inventors: Abraham Yee, Sheldon Aronowitz, Yu-Lam Ho
  • Patent number: 6091081
    Abstract: A structure and manufacturing process of a low dielectric constant interlayer insulating film used between wiring layers and semiconductor devices using such film are disclosed. The insulating film which can withstand in an actual process comprises an amorphous carbon fluoride film. A diamond like carbon film and a silicon excess layer are disposed on both sides of the amorphous carbon fluoride film to be inserted between the wiring layers, whereby adhesion to wiring and another insulating film contacting it is significantly enhanced. In addition, a silicon based insulating film is disposed and flattened on a multilayer film containing an amorphous carbon fluoride film buried with a wiring layer, and is used as a hard mask for anisotropically etching the diamond like carbon film and the amorphous carbon fluoride film with oxygen plasma to form a via hole.
    Type: Grant
    Filed: December 2, 1997
    Date of Patent: July 18, 2000
    Assignee: NEC Corporation
    Inventors: Yoshihisa Matsubara, Ko Noguchi, Shinya Ito, Noriaki Oda, Akira Matsumoto, Takashi Ishigami, Masahiko Nakamae, Tadahiko Horiuchi, Kazuhiko Endo, Toru Tatsumi, Yoshishige Matsumoto
  • Patent number: 6080998
    Abstract: An amorphous silicon germanium thin film is disclosed which contains hydrogen and germanium in concentrations of 5-10 atomic percent and 40-55 atomic percent, respectively for exhibiting the optical gap in the range of 1.30-1.40 eV. Also disclosed is a photovoltaic element incorporating the amorphous silicon germanium thin film.
    Type: Grant
    Filed: February 25, 1998
    Date of Patent: June 27, 2000
    Assignee: Sanyo Electric Co., Ltd.
    Inventors: Masaki Shima, Toshihiro Kinoshita, Masao Isomura
  • Patent number: 6072201
    Abstract: An amorphous silicon based hole-injection type "Separate Absorption and Multiplication Avalanche Photodiode" ("SAMAPD") has been invented. The device was made by separating an absorption layer and an avalanche layer from a conventional APD (Avalanche Photodiode). This will make a majority of an voltage bias to go across on the avalanche layer (i.e., a high energy bandgap material) and to enlarge an avalanche multiplication effect (i.e., increasing optical gains). In addition, the voltage bias goes across on the absorption layer will be sufficiently small to reduce a dark current. Using an i-a-Si:H material as the avalanche layer material and an i-a-Si.sub.1-x :Ge.sub.x :H material as the absorption layer material, the hole-injection type SAMPAD yields a very high gain, i.e., 686, at a reverse bias of 16V under an incident light power of P.sub.in =1 .mu.w. The product of this invention is very suitable for use in a long distance optical communication.
    Type: Grant
    Filed: January 6, 1999
    Date of Patent: June 6, 2000
    Assignee: National Science Counsel
    Inventors: Yeau-Kuen Fang, Kuen-Hsien Lee, Gun-Yuan Lee
  • Patent number: 6064091
    Abstract: A thin film transistor (10) in an electronic device such as an active matrix display panel having an intrinsic amorphous silicon semiconductor layer (22) providing a channel region (23) between source and drain electrodes (14, 16) includes directly adjacent to the side of the semiconductor layer (22) remote from the gate electrode (25) at the channel region (23) a layer (20) of amorphous semiconductor material which has a high defect density and low conductivity that serves to provide recombination centres for photogenerated carriers. Leakage problems due to the photoconductive properties of the intrinsic semiconductor material are then reduced. Conveniently, an hydrogenated silicon rich amorphous silicon alloy (e.g. nitride etc) can be used for the recombination centre layer (20).
    Type: Grant
    Filed: December 10, 1998
    Date of Patent: May 16, 2000
    Assignee: U.S. Philips Corporation
    Inventors: Steven C. Deane, John M. Shannon
  • Patent number: 6028264
    Abstract: Non-single-crystalline semiconductor material or device containing carbon impurity in a concentration less than 4.times.10.sup.18 atoms/cm.sup.3.
    Type: Grant
    Filed: July 25, 1997
    Date of Patent: February 22, 2000
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Shunpei Yamazaki
  • Patent number: 5998806
    Abstract: A pin or nip layer sequence, especially for use as a color sensor in electrooptical components. The bond gap of a first intrinsic (i) layer closer to the light input side is greater than the bond gap of a second i layer adjacent to the first and further removed from the light input side. The new .mu..tau. product for the i layer furthest distant from the layer is greater than the .mu..tau. product of an i layer closer is the n layer.
    Type: Grant
    Filed: September 25, 1998
    Date of Patent: December 7, 1999
    Assignee: Forschungszentrum Julich GmbH
    Inventors: Helmut Stiebig, Joachim Folsch, Dietmar Knipp
  • Patent number: 5942049
    Abstract: High quality, stable photovoltaic and electronic amorphous silicon devices which effectively resist light-induced degradation and current-induced degradation, are produced by a special plasma deposition process. Powerful, efficient single and multi-junction solar cells with high open circuit voltages and fill factors and with wider bandgaps, can be economically fabricated by the special plasma deposition process. The preferred process includes relatively low temperature, high pressure, glow discharge of silane in the presence of a high concentration of hydrogen gas.
    Type: Grant
    Filed: March 12, 1997
    Date of Patent: August 24, 1999
    Assignee: Amoco/Enron Solar
    Inventors: Yaun-Min Li, Murray S. Bennett, Liyou Yang
  • Patent number: 5923049
    Abstract: The invention relates to a photo sensitive electronic component based on amorphous silicon and its alloys, comprising two, in respect to each other antiserially arranged, p-i-n or n-i-p or Schottky-contact structures, in which in each case the active layers are arranged in the normal way in the direction of light incidence, whereby in the area of the first structure in the direction of light incidence, the charge carriers generated by blue light are collected for a first (V1) voltage; and in the area of the second structure in the direction of light incidence, the charge carriers generated by red or green light are collected for a second (V2) or a third (V3) voltage, and whereby at least one of the two intrinsically conducting layers is constructed from two partial layers. The object of creating better spectral selectivity is achieved in that in the partial layer (I) which is in front in the direction of light incidence, a higher product from charge carrier mobility and life-time (.mu.
    Type: Grant
    Filed: May 15, 1997
    Date of Patent: July 13, 1999
    Assignee: Cohausz & Florack
    Inventors: Markus Bohm, Helmut Stiebig
  • Patent number: 5909059
    Abstract: On a main surface of a silicon substrate of one conductivity type, a diffusion layer of the opposite conductivity type is formed, and the main surface of the silicon substrate is covered by an insulator film. The insulator film is formed with a contact hole which extends to reach the diffusion layer of the opposite conductivity type. A contact plug is provided in the contact hole. The contact plug fills the contact hole and comprises a first silicon layer of the opposite conductivity type directly connected to the diffusion layer of the opposite conductivity type, a silicon-germanium alloy layer of the opposite conductivity type directly contact to the first silicon layer, and a second silicon layer of the opposite conductivity type directly contact to the silicon-germanium alloy layer. Wiring is provided on the surface of the insulator film in direct contact to the contact plug.
    Type: Grant
    Filed: December 3, 1997
    Date of Patent: June 1, 1999
    Assignee: NEC Corporation
    Inventors: Hiromitsu Hada, Toru Tatsumi, Naoki Kasai, Hidemitsu Mori
  • Patent number: 5883398
    Abstract: A device having a switch comprises a chromium layer and an adjacent semiconductor layer. The fraction of voids in the chromium layer is less than 10%, preferably less than 2%. The chromium layer in the device comprises traces of neon with a concentration of less than 0.1 at. %. Chromium layers are deposited on a substrate by means of a sputter deposition process. By using neon as the working gas at pressures of less than 1 Pa, preferably in the range from 0.2 Pa to 0.5 Pa, the sputter-deposited chromium layers are substantially free of internal stress and have a density which is approximately equal to that of bulk chromium.
    Type: Grant
    Filed: November 25, 1997
    Date of Patent: March 16, 1999
    Assignee: U.S. Philips Corporation
    Inventors: Teunis J. Vink, Willem Walrave
  • Patent number: 5869851
    Abstract: A photoelectric conversion device wherein, in order to realize a photoelectric conversion device with high multiplication factors and excellent response speeds even under the application of low voltage by eliminating spike and notch in the hetero junction, a light absorbing layer (404) and a carrier multiplication layer (403) are made of non-single crystalline materials, said carrier multiplication layer (403) being comprised of a plurality of layers (411 to 414) with the forbidden band width changed continuously, and wherein the difference between the Fermi level and the vacuum energy level of said carrier multiplication layer (403) in the neighborhood of hetero junction is made substantially constant.
    Type: Grant
    Filed: June 3, 1997
    Date of Patent: February 9, 1999
    Assignee: Canon Kabushiki Kaisha
    Inventor: Shigetoshi Sugawa
  • Patent number: 5828084
    Abstract: The present invention pertains to a high-performance thin film transistor having a gate and an active region, whose active region comprises a poly-Si.sub.1 -.sub.x Ge.sub.x alloy material and a channel layer of silicon, in which the channel layer of silicon is interposed between the poly-Si.sub.1-x Ge.sub.x alloy material and the gate, and a method for fabricating such a high-performance thin film transistor.
    Type: Grant
    Filed: March 27, 1995
    Date of Patent: October 27, 1998
    Assignees: Sony Corporation, Massachusetts Institute of Technology
    Inventors: Takashi Noguchi, Rafael Reif, Julie Tsai, Andrew J. Tang
  • Patent number: 5818071
    Abstract: Disclosed is the use of silicon carbide as a barrier layer to prevent the diffusion of metal atoms between adjacent conductors separated by a dielectric material. This advancement allows for the use of low resistivity metals and low dielectric constant dielectric layers in integrated circuits and wiring boards.
    Type: Grant
    Filed: February 2, 1995
    Date of Patent: October 6, 1998
    Assignee: Dow Corning Corporation
    Inventors: Mark Jon Loboda, Keith Winton Michael
  • Patent number: 5793057
    Abstract: A preferred embodiment of this invention comprises an oxidizable layer (e.g. TiN 50), an amorphous nitride barrier layer (e.g. Ti--Si--N 34) overlying the oxidizable layer, an oxygen stable layer (e.g. platinum 36) overlying the amorphous nitride layer, and a high-dielectric-constant material layer (e.g. barium strontium titanate 38) overlying the oxygen stable layer. The amorphous nitride barrier layer substantially inhibits diffusion of oxygen to the oxidizable layer, thus minimizing deleterious oxidation of the oxidizable layer.
    Type: Grant
    Filed: June 7, 1995
    Date of Patent: August 11, 1998
    Assignee: Texas Instruments Incorporated
    Inventor: Scott R. Summerfelt
  • Patent number: 5783839
    Abstract: Disclosed is a semiconductor device, which is used as an optical detector and has: a photodiode section which has a first silicon layer, a light-absorbing layer and a second silicon layer which are in turn layered on a silicon substrate; wherein the light-absorbing layer is formed as a single silicon-germanium epitaxial layer and the single silicon-germanium epitaxial layer has a germanium concentration distribution which provides germanium concentrations of zero at its interfaces to the first silicon layer and the second silicon layer and provides a triangle-shaped concentration profile that a peak concentration value is provided in the middle of the single silicon-germanium epitaxial layer.
    Type: Grant
    Filed: March 21, 1997
    Date of Patent: July 21, 1998
    Assignee: NEC Corporation
    Inventors: Takenori Morikawa, Tsutomu Tashiro
  • Patent number: 5753936
    Abstract: An image-forming member for electro-photography has a photoconductive layer comprising a hydrogenated amorphous semiconductor composed of silicon and/or germanium as a matrix and at least one chemical modifier such as carbon, nitrogen and oxygen contained in the matrix.
    Type: Grant
    Filed: June 7, 1995
    Date of Patent: May 19, 1998
    Assignee: Canon Kabushiki Kaisha
    Inventors: Toshiyuki Komatsu, Yutaka Hirai, Katsumi Nakagawa, Tadaji Fukuda
  • Patent number: 5744849
    Abstract: A photoelectric converting device has a photoelectric converting part which consists of a light absorbing layer of a predetermined forbidden band width Eg1 and a carrier multiplying layer, positioned in laminate structure between charge injection blocking layers. The multiplying layer is composed of a layer or plural layers with a stepback structure of the forbidden band width having a minimum width Eg2 and a maximum width Eg3 in alternate manner and showing a continuous variation therebetween in each layer. The charge injection blocking layers, light absorbing layer and carrier multiplying layer are composed of non-monocrystalline semiconductors and at least having the minimum forbidden band width Eg2 and/or the maximum forbidden band width Eg3 contain a microcrystalline structure.
    Type: Grant
    Filed: July 26, 1994
    Date of Patent: April 28, 1998
    Assignee: Canon Kabushiki Kaisha
    Inventor: Shigetoshi Sugawa
  • Patent number: 5731613
    Abstract: Regions 106 which can be regarded as being monocrystalline are formed locally by irradiating with laser light, and at least the channel-forming region 112 is constructed using these regions. With thin-film transistors which have such a construction it is possible to obtain characteristics which are similar to those which employ monocrystals. Further, by connecting in parallel a plurality of such thin-film transistors it is possible to obtain characteristics which are effectively equivalent to those of a monocrystalline thin-film transistor in which the channel width has been increased.
    Type: Grant
    Filed: August 9, 1995
    Date of Patent: March 24, 1998
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Satoshi Teramoto
  • Patent number: 5726459
    Abstract: A Ge--Si MOS transistor for high speed, high density applications in which a thin layer of silicon (Si) is doped to have a concentration of germanium (Ge) ions which is preferably between 10 and 30%. The germanium doped silicon is formed on a layer or substrate of insulator. Optional silicidation of the drain and source regions improves conductivity therein and the use of shallow SIMOX processing technologies results in a more cost-effective and rapid fabrication process.
    Type: Grant
    Filed: June 10, 1994
    Date of Patent: March 10, 1998
    Assignees: Sharp Microelectronics Technology, Inc., Sharp Kabushiki Kaisha
    Inventors: Sheng Teng Hsu, Tatsuo Nakato
  • Patent number: 5716480
    Abstract: A photovoltaic device having a pin type semiconductor junction in which a p-type semiconductor layer and an n-type semiconductor layer are laminated with an interposed i-type semiconductor layer, comprises at least one doped layer of a non-monocrystal semiconductor disposed under and/or over the i-type semiconductor layer, wherein the at least one doped layer has a surface exposed to a plasma containing a band gap increasing element.
    Type: Grant
    Filed: July 11, 1996
    Date of Patent: February 10, 1998
    Assignee: Canon Kabushiki Kaisha
    Inventors: Jinsho Matsuyama, Ryo Hayashi
  • Patent number: 5700467
    Abstract: In the present invention, the optical band gap Eg (eV) of an amorphous silicon carbide film has the following relationship with the content of hydrogen C.sub.H (at. %) and the content of carbon C.sub.C (at. %) in the film:Eg=a+bC.sub.H /100+cC.sub.C /100,where a, b, and c are respectively in the ranges of 1.54.ltoreq.a.ltoreq.1.60, 0.55.ltoreq.b.ltoreq.0.65, and -0.65.ltoreq.c.ltoreq.-0.55, whereby the defect density in the amorphous silicon carbide film can be significantly reduced.
    Type: Grant
    Filed: March 21, 1996
    Date of Patent: December 23, 1997
    Assignee: Sanyo Electric Co. Ltd.
    Inventors: Masaki Shima, Norihiro Terada
  • Patent number: 5686734
    Abstract: A high performance thin film semiconductor device having a heterojunction such as a photoelectric conversion device is disclosed. In accordance with the present invention, the thin film semiconductor device comprises a thin semiconductor layer which forms a heterojunction with a non-single crystal silicon layer or non-single crystal silicon-germanium layer, wherein the valence band discontinuity at the heterointerface arising from the difference in optical energy bandgap is as small as 0.3 eV or less and wherein the thin semiconductor layer has an optical energy bandgap greater than 2.8 eV, so that hole transport performance may not be degraded. Such a thin semiconductor layer may be formed by using silane gas and methane gas with a flow rate ratio greater than 30 at a deposition rate less than 0.5 .ANG./sec.
    Type: Grant
    Filed: July 14, 1995
    Date of Patent: November 11, 1997
    Assignee: Canon Kabushiki Kaisha
    Inventors: Yoshihiro Hamakawa, Shigetoshi Sugawa, Tadashi Atoji, Hiroaki Okamoto
  • Patent number: 5682037
    Abstract: Thin film detector of ultraviolet radiation with high spectral selectivity option, and a structure placed between two electrodes, formed by the superposition of semiconductor thin films such as hydrogenated amorphous silicon and its alloys with carbon. The device is able to absorb a large quantity of UV radiation and to convert it into electric current being transparent to photons of longer wavelengths. Its deposition technique allows fabrication on substrates of glass, plastic, metal, ceramic types of materials (also opaque, also flexible), on which a conductor material film has been predeposited. It can be fabricated on substrates of any size.
    Type: Grant
    Filed: January 18, 1996
    Date of Patent: October 28, 1997
    Assignee: Universita Degli Studi Di Roma "La Sapienza"
    Inventors: Giampiero de Cesare, Fernanda Irrera, Fabrizio Palma
  • Patent number: 5680229
    Abstract: There is disclosed a photoelectric conversion element having a photoelectric conversion portion, at least comprising an insulating layer, a photoconductive semiconductor layer provided in contact with said insulating layer, and made of a non-single crystal material containing hydrogen atoms with the base of silicon, first and second electrodes provided in contact with the photoconductive semiconductor layer, and a third electrode provided in contact with the insulating layer. The amount of hydrogen atoms contained in said photoconductive semiconductor layer is made nonuniform in a thickness direction of said layer so that an energy band gap width of said layer changes.
    Type: Grant
    Filed: November 26, 1993
    Date of Patent: October 21, 1997
    Assignee: Canon Kabushiki Kaisha
    Inventors: Masato Yamanobe, Shinichi Takeda, Takayuki Ishii, Toshihiro Saika, Isao Kobayashi
  • Patent number: 5676765
    Abstract: A photovoltaic element comprising a substrate and a multi-layered semiconductor active layer having a pin junction structure disposed on said substrate, said multi-layered semiconductor layer comprising a non-single crystal semiconductor layer of n- or p-type, a non-single crystal i-type semiconductor layer and a non-single crystal semiconductor layer of p- or n-type being stacked in this order from the substrate side, characterized in that said i-type semiconductor layer comprises a three-layered structure comprising a non-single crystal layer (b) formed by means of a microwave plasma CVD process interposed between a pair of non-single crystal layers (a) and (c) each formed by means of a RF plasma CVD process, and said i-type layer (b) is a non-single crystal i-type layer formed by means of the microwave plasma process from a mixture of a silane series gas not containing chlorine atom(s), a chlorine-containing raw material gas in an amount of 10% or less of the total amount of the chlorine-free silane series
    Type: Grant
    Filed: March 27, 1995
    Date of Patent: October 14, 1997
    Assignee: Canon Kabushiki Kaisha
    Inventors: Keishi Saito, Koichi Matsuda, Hiroshi Shimoda, Yusuke Miyamoto
  • Patent number: RE37441
    Abstract: A photoelectric conversion device has a non-single-crystal semiconductor laminate member formed on a substrate having a conductive surface, and a conductive layer formed on the non-single-crystal semiconductor laminate member. The non-single-crystal semiconductor laminate member has such a structure that a first non-single-crystal semiconductor layer having a P or N first conductivity type, an I-type second non-single-crystal semiconductor layer and a third non-single-crystal semiconductor layer having a second conductivity type opposite the first conductivity type are laminated in this order. The first (or third) non-single-crystal semiconductor layer is disposed on the side on which light is incident, and is P-type. The I-type non-single-crystal semiconductor layer has introduced thereinto a P-type impurity, such as boron which is distributed so that its concentration decreases towards the third (or first) non-single-crystal semiconductor layer in the thickness direction of the I-type layer.
    Type: Grant
    Filed: October 8, 1997
    Date of Patent: November 13, 2001
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Shunpei Yamazaki