Amorphous Semiconductor Is Alloy Or Contains Material To Change Band Gap (e.g., Si X Ge 1-x , Sin Y ) Patents (Class 257/55)
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Patent number: 7115925Abstract: An active pixel includes a a photosensitive element formed in a semiconductor substrate. A transfer transistor is formed between the photosensitive element and a floating diffusion and selectively operative to transfer a signal from the photosensitive element to the floating diffusion. The floating diffusion is formed from an n-type implant with a dosage in the range of 5e13 to 5e14 ions/cm2. Finally, an amplification transistor is controlled by the floating diffusion.Type: GrantFiled: January 14, 2005Date of Patent: October 3, 2006Assignee: OmniVision Technologies, Inc.Inventor: Howard E. Rhodes
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Patent number: 7102185Abstract: An interline transfer type image sensing device that can be operated at high speed and with low image smear is described. The device incorporates a refractory metal layer which is used for both a light shield over the vertical charge transfer region and as a wiring layer for low resistance strapping of poly crystalline silicon (polysilicon) gate electrodes for the vertical charge transfer region. Plugs provided by a separate metallization layer connect the refractory light shield to the polysilicon gate electrode. These plugs allow high temperature processing after refractory light shield patterning for improved sensor performance without degradation of the polysilicon gate electrode or the refractory lightshield layer.Type: GrantFiled: June 21, 2004Date of Patent: September 5, 2006Assignee: Eastman Kodak CompanyInventors: David N. Nichols, David L. Losee, Christopher Parks
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Patent number: 7015507Abstract: Provided is a non-single-crystal germanium thin film transistor having a gate insulating film capable of reducing the interface state density between an active layer and the gate insulating film. This thin film transistor has an active layer made of a non-single-crystal germanium film, and a gate oxide film substantially made of zirconium oxide or hafnium oxide.Type: GrantFiled: May 28, 2004Date of Patent: March 21, 2006Assignee: Canon Kabushiki KaishaInventors: Takao Yonehara, Tetsuya Shimada
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Patent number: 6984847Abstract: An organic electroluminescent device includes first and second substrates facing and spaced apart from each other; a gate line on an inner surface of the first substrate; a semiconductor layer over the gate line, the semiconductor layer overlying a surface of the first substrate; a data line crossing the gate line; a data ohmic contact layer under the data line, the data ohmic contact layer having the same shape as the data line; a power line parallel to, or substantially parallel to, and spaced apart from the data line, the power line including the same material as the gate line; a switching thin film transistor connected to the gate line and the data line, the switching thin film transistor using the semiconductor layer as a switching active layer; a driving thin film transistor connected to the switching thin film transistor and the power line, the driving thin film transistor using the semiconductor layer as a driving active layer; a connection pattern connected to the driving thin film transistor, the coType: GrantFiled: December 22, 2003Date of Patent: January 10, 2006Assignee: LG.Philips LCD Co., Ltd.Inventors: Jae-Yong Park, Kwang-Jo Hwang
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Patent number: 6960789Abstract: A transistor that at least has one of the following characteristics: First, the gate electrode is located outside the gate line, such that the whole transistor is located outside the gate line. Second, the projection of the semiconductor layer on the substrate is totally located inside the projection of the gate electrode on the substrate. Third, the drain cross the gate electrode, such that the projection of the cross-section is totally located inside the projection of the gate electrode. Final, the separated distance between the gate line, the gate electrode, the drain and the source is adjusted to let the variation of each of Cgd and Cds be not obviously affected by the alignment deviation.Type: GrantFiled: November 24, 2003Date of Patent: November 1, 2005Assignee: Chunghwa Picture Tubes, Ltd.Inventor: Ming-Hsuan Chang
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Patent number: 6940089Abstract: A method of fabricating a semiconductor structure. According to one aspect of the invention, on a first semiconductor substrate, a first compositionally graded Si1-xGex buffer is deposited where the Ge composition x is increasing from about zero to a value less than about 20%. Then a first etch-stop Si1-yGey layer is deposited where the Ge composition y is larger than about 20% so that the layer is an effective etch-stop. A second etch-stop layer of strained Si is then grown. The deposited layer is bonded to a second substrate. After that the first substrate is removed to release said first etch-stop Si1-yGey layer. The remaining structure is then removed in another step to release the second etch-stop layer. According to another aspect of the invention, a semiconductor structure is provided. The structure has a layer in which semiconductor devices are to be formed.Type: GrantFiled: April 4, 2002Date of Patent: September 6, 2005Assignee: Massachusetts Institute of TechnologyInventors: Zhiyuan Cheng, Eugene A. Fitzgerald, Dimitri A. Antoniadis
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Patent number: 6930326Abstract: According to the invention, a plurality of semiconductor devices which are required to have conformance are formed from crystalline semiconductor films having uniform crystallinity on the same line, and a semiconductor circuit in which variation between semiconductor devices is small can be provided, and a semiconductor integrated circuit having high conformance can be provided. The invention is characterized in that, in a part or whole of thin film transistors which configure an analog circuit such as a current mirror circuit, a differential amplifier circuit, or an operational amplifier, in which high conformance is required for semiconductor devices included therein, channel forming regions have crystalline semiconductor films on the same line. High conformance can be expected for an analog circuit which has the crystalline semiconductor films on the same line formed using the invention as the channel forming regions of the thin film transistors.Type: GrantFiled: March 25, 2003Date of Patent: August 16, 2005Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Kiyoshi Kato, Tomoaki Atsumi, Atsuo Isobe
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Patent number: 6927417Abstract: In a back-surface electrode type photoelectric conversion element having electrodes and semiconductor layers for collecting carriers disposed only on a back surface side of a semiconductor substrate, a semiconductor thin film that is larger in band gap than the semiconductor substrate and that contains an element causing a conductivity identical to or different from a conductivity of the semiconductor substrate is provided on a light-receiving surface side of the semiconductor substrate, and a diffusion layer is formed on a surface of the semiconductor substrate.Type: GrantFiled: November 12, 2002Date of Patent: August 9, 2005Assignee: Toyota Jidosha Kabushiki KaishaInventors: Tomonori Nagashima, Kenichi Okumura
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Patent number: 6921914Abstract: A process for producing monocrystalline semiconductor layers. In an exemplary embodiment, a graded Si1-xGex (x increases from 0 to y) is deposited on a first silicon substrate, followed by deposition of a relaxed Si1-yGey layer, a thin strained Si1-zGez layer and another relaxed Si1-yGey layer. Hydrogen ions are then introduced into the strained SizGez layer. The relaxed Si1-yGey layer is bonded to a second oxidized substrate. An annealing treatment splits the bonded pair at the strained Si layer, such that the second relaxed Si1-yGey layer remains on the second substrate. In another exemplary embodiment, a graded Si1-xGex is deposited on a first silicon substrate, where the Ge concentration x is increased from 0 to 1. Then a relaxed GaAs layer is deposited on the relaxed Ge buffer. As the lattice constant of GaAs is close to that of Ge, GaAs has high quality with limited dislocation defects. Hydrogen ions are introduced into the relaxed GaAs layer at the selected depth.Type: GrantFiled: March 17, 2004Date of Patent: July 26, 2005Assignee: Massachusetts Institute of TechnologyInventors: Zhi-Yuan Cheng, Eugene A. Fitzgerald, Dimitri A. Antoniadis, Judy L. Hoyt
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Patent number: 6903372Abstract: To provide TFT of improved low-temperature polycrystalline layer that has higher electron mobility and assures less fluctuation in manufacture in view of realizing a liquid-crystal display device having a large display area by utilizing a glass substrate. A TFT having higher electron mobility can be realized within the predetermined range of characteristic fluctuation by utilizing the semiconductor thin-film (called quasi single crystal thin-film) formed of poly-crystal grain joined with the {111} twin-boundary of Diamond structure as the channel region (namely, active region) of TFT.Type: GrantFiled: October 30, 2000Date of Patent: June 7, 2005Assignee: Hitachi, Ltd.Inventors: Shinya Yamaguchi, Masanobu Miyao, Nobuyuki Sugii, Seang-kee Park, Kiyokazu Nakagawa
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Patent number: 6872972Abstract: Roughly described, a silicon layer transitions from polysilicon at one surface to amorphous silicon at the opposite surface. The transition can be monotonic, and can be either continuous or it can change abruptly from polysilicon to amorphous silicon. If such a layer is formed as the floating gate of a floating gate transistor structure, the larger grain structure adjacent to the tunnel dielectric layer reduces the formation of a tip (protrusion) and thus reduces leakage. On the other hand, the smaller grain structure adjacent to the gate dielectric layer produces a smooth, more uniform gate dielectric layer. The polysilicon-to-amorphous silicon transistor can be fabricated with a temperature profile that favors polysilicon formation at the start of floating gate deposition, and transitions during deposition to a temperature that favors amorphous silicon deposition at the end of floating gate deposition.Type: GrantFiled: July 16, 2003Date of Patent: March 29, 2005Assignee: Macronix International Co., Ltd.Inventors: Chih Yuan Huang, Jonason Chen
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Patent number: 6856002Abstract: The present invention provides a design for a PCRAM element which incorporates multiple metal-containing germanium-selenide glass layers of diverse stoichiometries. The present invention also provides a method of fabricating the disclosed PCRAM structure.Type: GrantFiled: August 29, 2002Date of Patent: February 15, 2005Assignee: Micron Technology, Inc.Inventors: John T. Moore, Terry L. Gilton, Kristy A. Campbell
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Patent number: 6838695Abstract: A semiconductor device structure includes a substrate, a dielectric layer disposed on the substrate, first and second stacks disposed on the dielectric layer. The first stack includes a first silicon layer disposed on the dielectric layer, a silicon germanium layer disposed on the first silicon layer, a second silicon layer disposed on the silicon germanium layer, and a third silicon layer disposed on the second silicon layer. The second stack includes a first silicon layer disposed on the dielectric layer, and a second silicon layer disposed on the first silicon layer. Alternatively, the silicon germanium layer includes Boron.Type: GrantFiled: November 25, 2002Date of Patent: January 4, 2005Assignee: International Business Machines CorporationInventors: Bruce B. Doris, Ashima B. Chakravarti, Kevin K. Chan, Daniel A. Uriarte
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Patent number: 6838713Abstract: A standard cell architecture with a basic cell that spans multiple rows of the standard cell. This multi-row basic cell may be a dual-height cell that spans two rows, or it may span more than two rows. The multi-row basic cell may be intermixed in a standard cell design with smaller, single-height cells for high-density applications. The single-height cells may be used where possible and higher-drive dual-height basic cells where larger transistors are desired. Other multiple height cells may also be included if even more current is desirable. The power rail may include conductors of varying width.Type: GrantFiled: July 12, 1999Date of Patent: January 4, 2005Assignee: Virage Logic CorporationInventors: Tushar R. Gheewala, Michael J. Colwell, Henry H. Yang, Duane G. Breid
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Patent number: 6831333Abstract: To provide a thin film transistor having a low OFF characteristic and to provide P-channel type and N-channel type thin film transistors where a difference in characteristics of the P-channel type and the N-channel type thin film transistors is corrected, a region 145 having a P-type behavior more potential than that of a drain region 146 is arranged between a channel forming region 134 and the drain region 146 in the P-channel type thin film transistor whereby the P-channel type thin film transistor having the low OFF characteristic can be provided and a low concentration impurity region 136 is arranged between a channel forming region 137 and a drain region 127 in the N-channel type thin film transistor whereby the N-channel type thin film transistor having the low OFF characteristic and where deterioration is restrained can be provided.Type: GrantFiled: December 3, 2002Date of Patent: December 14, 2004Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Hongyong Zhang, Satoshi Teramoto
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Patent number: 6815802Abstract: A SiGe bipolar transistor containing substantially no dislocation defects present between the emitter and collector region and a method of forming the same are provided. The SiGe bipolar transistor includes a collector region of a first conductivity type; a SiGe base region formed on a portion of said collector region; and an emitter region of said first conductivity type formed over a portion of said base region, wherein said collector region and said base region include carbon continuously therein. The SiGe base region is further doped with boron.Type: GrantFiled: April 15, 2002Date of Patent: November 9, 2004Assignee: International Business Machines CorporationInventors: Jack Oon Chu, Douglass Duane Coolbaugh, James Stuart Dunn, David R. Greenberg, David L. Harame, Basanth Jagannathan, Robb Allen Johnson, Louis D. Lanzerotti, Kathryn Turner Schonenberg, Ryan Wayne Wuthrich
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Patent number: 6787793Abstract: A semiconductor device comprises a first Si1−&agr;Ge&agr; film, a first cap film, a second Si1−&bgr;Ge&bgr; film (&bgr;<&agr;≦1) and a second cap film formed in this order on a substrate whose surface is formed of silicon, wherein the first Si1−&agr;Ge&agr; film is relaxed to have substantially the same lattice constant as that of the second Si1−&bgr;Ge&bgr; film in a horizontal plane.Type: GrantFiled: November 19, 2002Date of Patent: September 7, 2004Assignee: Sharp Kabushiki KaishaInventor: Akira Yoshida
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Patent number: 6770912Abstract: A semiconductor device includes a SiC substrate and an ohmic electrode, a semiconductor member including a SiC member and a SiGe member being formed between the SiC substrate and the ohmic electrode, wherein the semiconductor member is composed of a SiGe member formed on a SiC member, and the ohmic electrode is formed on the SiGe member, whereby the ohmic electrode with a low resistance can be formed on the SiC substrate without conducting a heat treatment at a high temperature.Type: GrantFiled: February 19, 2002Date of Patent: August 3, 2004Assignee: Matsushita Electric Industrial Co., Ltd.Inventor: Yorito Ota
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Patent number: 6759712Abstract: The invention includes SOI thin film transistor constructions, memory devices, computer systems, and methods of forming various structures, devices and systems. The structures typically comprise a thin crystalline layer of silicon/germanium formed over a wide range of suitable substrates. The crystalline properties of the silicon/germanium can be controlled during formation of the silicon/germanium so that the material has a relaxed crystalline lattice and large crystalline grain sizes. The crystalline grain sizes can be sufficiently large so that transistor devices formed in association with the thin crystalline material have active regions utilizing only a single grain of the silicon/germanium material.Type: GrantFiled: September 12, 2002Date of Patent: July 6, 2004Assignee: Micron Technology, Inc.Inventor: Arup Bhattacharyya
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Patent number: 6750394Abstract: A thin-film solar cell comprises a set of a transparent conductive layer and a photoelectric conversion layer laminated in this order on a substrate, wherein the photoelectric conversion layer is made of a p-i-n junction, the i-layer is made of a crystalline layer and the transparent conductive layer is provided with a plurality of holes at its surface of the side of the photoelectric conversion layer, each of said holes having irregularities formed on its surface.Type: GrantFiled: January 10, 2002Date of Patent: June 15, 2004Assignee: Sharp Kabushiki KaishaInventors: Hiroshi Yamamoto, Kenji Wada
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Publication number: 20040099860Abstract: A semiconductor device structure includes a substrate, a dielectric layer disposed on the substrate, first and second stacks disposed on the dielectric layer. The first stack includes a first silicon layer disposed on the dielectric layer, a silicon germanium layer disposed on the first silicon layer, a second silicon layer disposed on the silicon germanium layer, and a third silicon layer disposed on the second silicon layer. The second stack includes a first silicon layer disposed on the dielectric layer, and a second silicon layer disposed on the first silicon layer. Alternatively, the silicon germanium layer includes Boron.Type: ApplicationFiled: November 25, 2002Publication date: May 27, 2004Applicant: International Business Machines CorporationInventors: Bruce B. Doris, Ashima B. Chakravarti, Kevin K. Chan, Daniel A. Uriarte
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Publication number: 20040094763Abstract: Thermal mixing methods of forming a substantially relaxed and low-defect SGOI substrate material are provided. The methods include a patterning step which is used to form a structure containing at least SiGe islands formed atop a Ge resistant diffusion barrier layer. Patterning of the SiGe layer into islands changes the local forces acting at each of the island edges in such a way so that the relaxation force is greater than the forces that oppose relaxation. The absence of restoring forces at the edges of the patterned layers allows the final SiGe film to relax further than it would if the film was continuous.Type: ApplicationFiled: November 20, 2002Publication date: May 20, 2004Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Paul D. Agnello, Stephen W. Bedell, Robert H. Dennard, Anthony G. Domenicucci, Keith E. Fogel, Devendra K. Sadana
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Patent number: 6734455Abstract: A method for fabricating chalcogenide materials on substrates, which reduces and/or eliminates agglomeration of materials on the chalcogenide materials; and system and devices for performing the method, semiconductor devices so produced, and machine readable media containing the method. One method disclosed includes forming a first layer, forming a second layer on the first layer, forming a third layer on the second layer, wherein the third layer is essentially transparent to irradiation, and irradiating the second layer through the third layer to cause the second layer to diffuse into the first layer thereby creating an integral layer of materials from the first and second layers.Type: GrantFiled: March 15, 2001Date of Patent: May 11, 2004Assignee: Micron Technology, Inc.Inventor: Jiutao Li
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Patent number: 6734499Abstract: An insulated gate field effect transistor comprises a non-single-crystalline semiconductor layer formed on a substrate, a gate electrode is formed on a portion of the surface of said semiconductor layer, and a gate insulating film is disposed between said gate electrode and said semiconductor layer. A non-single-crystalline channel region is defined within said semiconductor layer just below said gate electrode. A source region and a drain region are transformed from and defined within said semiconductor layer immediately adjacent to said channel region in an opposed relation, said source and drain regions being crystallized to a higher degree than that of said channel region by selectively irradiating portions of said semiconductor layer using said gate electrode as a mask.Type: GrantFiled: September 28, 1999Date of Patent: May 11, 2004Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventor: Shunpei Yamazaki
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Patent number: 6720583Abstract: The present invention provides an optical device and a surface emitting type device which have high efficiency and a stable operation and are manufactured at high manufacturing yield. The optical device and the surface emitting type device are characterized in that they have a distributed Bragg reflector (DBR) including a plurality of semiconductor layers made of a nitride semiconductor with substantially same gaps therbetween. Further, the optical device and the surface emitting type device are characterized in that they have a distributed Bragg reflector (DBR) in which a plurality of semiconductor layers made of nitride semiconductor and a plurality of organic layers made of organic material are alternately laminated.Type: GrantFiled: September 20, 2001Date of Patent: April 13, 2004Assignee: Kabushiki Kaisha ToshibaInventors: Shin-Ya Nunoue, Masayuki Ishikawa
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Patent number: 6710382Abstract: A silicon germanium layer is deposited over a semiconductor substrate with a gate insulating film interposed between the substrate and the silicon germanium layer. Then, an upper silicon layer in an amorphous state is deposited on the silicon germanium layer. Thereafter, a gate electrode is formed by patterning the silicon germanium layer and the upper silicon layer.Type: GrantFiled: May 5, 2003Date of Patent: March 23, 2004Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Hiroko Kubo, Kenji Yoneda
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Patent number: 6690026Abstract: An apparatus comprising control circuitry formed on a substrate, and a plurality of active media coupled to the control circuitry and formed in a plurality of planes over the substrate. A method comprising forming a pair of junction regions on a substrate separated by a channel length; and forming a channel material overlying and coupled to the pair of junction regions having a dimension at least equal to the channel length. An apparatus comprising a contact formed in a first plane over a device structure; and a device coupled to the contact and formed in a second plane a greater distance from the substrate than the first plane.Type: GrantFiled: September 28, 2001Date of Patent: February 10, 2004Assignee: Intel CorporationInventor: Jeff J. Peterson
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Patent number: 6690072Abstract: A method (and structure) of forming a vertically-self-aligned silicide contact to an underlying SiGe layer, includes forming a layer of silicon of a first predetermined thickness on the SiGe layer and forming a layer of metal on the silicon layer, where the metal layer has a second predetermined thickness. A thermal annealing process at a predetermined temperature then forms a silicide of the silicon and metal, where the predetermined temperature is chosen to substantially preclude penetration of the silicide into the underlying SiGe layer.Type: GrantFiled: May 24, 2002Date of Patent: February 10, 2004Assignee: International Business Machines CorporationInventors: Cyril Cabral, Jr., Roy A. Carruthers, Kevin K. Chan, Jack O. Chu, Guy Moshe Cohen, Steven J. Koester, Christian Lavoie, Ronnen A. Roy
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Patent number: 6670638Abstract: Disclosed is a polysilicon film adapted for use in a liquid crystal display, and method of manufacturing such film. In manufacturing the film, a native oxide layer formed on a surface of an amorphous silicon film is completely removed by a hydrofluoric acid solution, followed by immersing in an H2O2 solution to newly form an extremely thin oxide layer, prior to a crystallizing processing performed by a laser beam irradiation. The crystallizing processing forms a polysilicon film formed of crystal grains Preferentially oriented on the (111) plane in a direction parallel to the substrate surface, an average crystal grain size being not larger than 300 nm, the standard deviation of the grain sizes being not larger than 30% of the average grain size, and the standard deviation of the roughness being not larger than 10% of the average grain size.Type: GrantFiled: February 28, 2001Date of Patent: December 30, 2003Assignee: Hitachi, Ltd.Inventors: Takuo Tamura, Kiyoshi Ogata, Yoichi Takahara, Hironaru Yamaguchi, Yoshinobu Kimura, Makoto Ohkura, Hironobu Abe, Shigeo Shimomura, Masakazu Saitou, Michiko Takahashi
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Patent number: 6670657Abstract: An integrated circuit is provided that includes a substrate incorporating a semiconductor photodiode device having a p-n junction. The photodiode device includes at least one capacitive trench buried in the substrate and connected in parallel with the junction. In a preferred embodiment, the substrate is formed from silicon, and the capacitive trench includes an internal doped silicon region partially enveloped by an insulating wall that laterally separates the internal region from the substrate. Also provided is a method for fabricating an integrated circuit including a substrate that incorporates a semiconductor photodiode device having a p-n junction.Type: GrantFiled: January 11, 2002Date of Patent: December 30, 2003Assignee: STMicroelectronics S.A.Inventors: Olivier Menut, Yvon Gris
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Patent number: 6670687Abstract: A semiconductor device having a silicon carbide layer of a singular conductivity type. The silicon carbide layer includes a surface having a first region, a second region, and a third region sandwiched between the first region and the second region. An anode electrode having a Schottky contact with the first region, a cathode electrode having an ohmic contact with the second region, and a control electrode having a Schottky contact with the third region are included in the semiconductor device.Type: GrantFiled: October 15, 2001Date of Patent: December 30, 2003Assignee: Mitsubishi Denki Kabushiki KaishaInventors: Katsumi Satoh, Shinichi Ishizawa
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Patent number: 6667240Abstract: A method for forming a deposited film, comprising generating plasma in a plurality of successive vacuum containers and continuously forming a deposited film on a belt-like substrate while continuously moving the substrate in its longitudinal direction, wherein an opening of a discharge container is adjusted with an opening adjusting plate having a shape set so as to reduce ununiformity of a deposited film thickness in a width direction of the substrate on the basis of a measurement of a deposition rate distribution. Accordingly, there is provided a method and an apparatus for forming a deposited film which are capable of producing a photovoltaic element without ununiformity in characteristics by depositing semiconductor layers without ununiformity in thickness and quality.Type: GrantFiled: March 8, 2001Date of Patent: December 23, 2003Assignee: Canon Kabushiki KaishaInventors: Hiroyuki Ozaki, Masahiro Kanai, Naoto Okada, Koichiro Moriyama, Hiroshi Shimoda
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Patent number: 6664566Abstract: A photoelectric conversion device has a non-single-crystal semiconductor laminate member formed on a substrate having a conductive surface, and a conductive layer formed on the non-single-crystal semiconductor laminate member. The non-single-crystal semiconductor laminate member has such a structure that a first non-single-crystal semiconductor layer having a P or N first conductivity type, an I-type second non-single-crystal semiconductor layer and a third non-single-crystal semiconductor layer having a second conductivity type opposite the first conductivity type are laminated in this order. The first (or third) non-single-crystal semiconductor layer is disposed on the side on which light is incident, and is P-type. The I-type non-single-crystal semiconductor layer has introduced thereinto a P-type impurity, such as boron which is distributed so that its concentration decreases towards the third (or first) non-single-crystal semiconductor layer in the thickwise direction of the I-type layer.Type: GrantFiled: January 30, 2001Date of Patent: December 16, 2003Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventor: Shunpei Yamazaki
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Publication number: 20030183819Abstract: An Si/SiGe layer including an Si buffer layer, an SiGe spacer layer, a graded SiGe layer and an Si cap layer is epitaxially grown in a region corresponding to a collector opening while a polycrystalline layer is deposited on the upper surface of a nitride film, and side surfaces of an oxide film and the nitride film. In this case, the Si buffer layer is formed first and then other layers such as the SiGe spacer layer are formed, thereby ensuring non-selective epitaxial growth. Then, a polycrystalline layer is deposited over the nitride film.Type: ApplicationFiled: December 23, 2002Publication date: October 2, 2003Applicant: Matsushita Electric Industrial Co., Ltd.Inventors: Shigetaka Aoki, Tohru Saitoh, Katsuya Nozawa
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Patent number: 6621131Abstract: A process is described for manufacturing an improved PMOS semiconductor transistor. Recesses are etched into a layer of epitaxial silicon. Source and drain films are deposited in the recesses. The source and drain films are made of an alloy of silicon and germanium. The alloy is epitaxially deposited on the layer of silicon. The alloy thus has a lattice having the same structure as the structure of the lattice of the layer of silicon. However, due to the inclusion of the germanium, the lattice of the alloy has a larger spacing than the spacing of the lattice of the layer of silicon. The larger spacing creates a stress in a channel of the transistor between the source and drain films. The stress increases IDSAT and IDLIN of the transistor. An NMOS transistor can be manufactured in a similar manner by including carbon instead of germanium, thereby creating a tensile stress.Type: GrantFiled: November 1, 2001Date of Patent: September 16, 2003Assignee: Intel CorporationInventors: Anand Murthy, Robert S. Chau, Tahir Ghani, Kaizad R. Mistry
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Publication number: 20030170960Abstract: A high performance SiGe HBT that has a SiGe layer with a peak Ge concentration of at least approximately 20% and a boron-doped base region formed therein having a thickness. The base region includes diffusion-limiting impurities substantially throughout its thickness, at a peak concentration below that of boron in the base region. Both the base region and the diffusion-limiting impurities are positioned relative to a peak concentration of Ge in the SiGe layer so as to optimize both performance and yield.Type: ApplicationFiled: March 8, 2002Publication date: September 11, 2003Applicant: International Business Machines CorporationInventors: Basanth Jagannathan, Alvin J. Joseph, Xuefeng Liu, Kathryn T. Schonenberg, Ryan W. Wuthrich
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Publication number: 20030160300Abstract: A semiconductor substrate comprising a silicon substrate with an oxide film on its surface, on which a silicon layer, a warp-relieved SiGe layer and a warped cap layer are formed in this order, a semiconductor device comprising a transistor, a diode, a capacitor and/or a bipolar transistor formed solely or in combination on the above semiconductor substrate and a method of manufacturing the above semiconductor substrate.Type: ApplicationFiled: February 24, 2003Publication date: August 28, 2003Inventors: Masahiro Takenaka, Katsumasa Fujii
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Publication number: 20030127646Abstract: A method of fabricating relaxed SiGe buffer layers with low threading dislocation densities on silicon-on-insulator (SOI) substrates is provided. The relaxed SiGe buffer layers are fabricated by the epitaxial deposition of a defect-free Stranski-Krastanov Ge or SiGe islands on a surface of the SOI substrate; the capping and planarizing of the islands with a Si or Si-rich SiGe layer, and the annealing of the structure at elevated temperatures until intermixing and thereby formation of a relaxed SiGe layer on the insulating layer (i.e., buried oxide layer) of the initial SOI wafer is achieved. The present invention is also directed to semiconductor structures, devices and integrated circuits which include at least the relaxed SiGe buffer layer mentioned above.Type: ApplicationFiled: December 18, 2002Publication date: July 10, 2003Applicant: International Business Machines CorporationInventors: Silke H. Christiansen, Alfred Grill, Patricia M. Mooney
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Publication number: 20030089906Abstract: A spacer layer is formed on a single-crystal substrate and an epitaxially grown layer composed of a group III-V compound semiconductor layer containing a nitride or the like is further formed on the spacer layer. The epitaxially grown layer is adhered to a recipient substrate. The back surface of the single-crystal substrate is irradiated with a light beam such as a laser beam or a bright line spectrum from a mercury vapor lamp such that the epitaxially grown layer and the single-crystal substrate are separated from each other. Since the forbidden band of the spacer layer is smaller than that of the single-crystal substrate, it is possible to separate the thin semiconductor layer from the substrate by decomposing or fusing the spacer layer, while suppressing the occurrence of a crystal defect or a crack in the epitaxially grown layer.Type: ApplicationFiled: November 13, 2002Publication date: May 15, 2003Applicant: MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.Inventor: Tetsuzo Ueda
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Patent number: 6562703Abstract: A method is provided for forming a relaxed silicon germanium layer with a high germanium content on a silicon substrate. The method comprises: depositing a single-crystal silicon (Si) buffer layer overlying the silicon substrate; depositing a layer of single-crystal silicon germanium (Si1−xGex) overlying the Si buffer layer having a thickness of 1000 to 5000 Å; implanting the Si1−xGex layer with ionized molecular hydrogen (H2+) a projected range of approximately 100 to 300 Å into the underlying Si buffer layer; optionally, implanting the Si1−xGex layer with a species selected such as boron, He, or Si; annealing; and, in response to the annealing, converting the Si1−xGex layer to a relaxed Si1−xGex layer. Optionally, after annealing, an additional layer of single-crystal Si1−xGex having a thickness of greater than 1000 Å can be deposited overlying the relaxed layer of Si1−xGex.Type: GrantFiled: March 13, 2002Date of Patent: May 13, 2003Assignee: Sharp Laboratories of America, Inc.Inventors: Jer-Shen Maa, Douglas J. Tweet, Sheng Teng Hsu, Jong-Jan Lee
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Patent number: 6545299Abstract: One embodiment of the present invention provides a process that uses selective etching to form a structure on a silicon substrate. The process starts by receiving the silicon substrate with a first layer composed of a first material, which includes voids created by a first etching operation. The process then forms a second layer composed of a second material over the first layer, so that the second layer fills in portions of voids in the first layer created by the first etching operation. Next, the process performs a chemo-mechanical polishing operation on the second layer down to the first layer so that only remaining portions of the second layer, within the voids created by the first etching operation, remain.Type: GrantFiled: June 18, 2002Date of Patent: April 8, 2003Assignee: The Regents of the University of CaliforniaInventors: Jeffrey J. Peterson, Charles E. Hunt
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Publication number: 20030034491Abstract: High quality epitaxial layers of monocrystalline materials can be grown overlying monocrystalline substrates such as large silicon wafers by forming a compliant substrate for growing the monocrystalline layers. An accommodating buffer layer comprises a layer of monocrystalline oxide spaced apart from a silicon wafer by an amorphous interface layer of silicon oxide. The amorphous interface layer dissipates strain and permits the growth of a high quality monocrystalline oxide accommodating buffer layer. The accommodating buffer layer is lattice matched to both the underlying silicon wafer and the overlying monocrystalline material layer. Any lattice mismatch between the accommodating buffer layer and the underlying silicon substrate is taken care of by the amorphous interface layer. In addition, formation of a compliant substrate may include utilizing surfactant enhanced epitaxy, epitaxial growth of single crystal silicon onto single crystal oxide, and epitaxial growth of Zintl phase materials.Type: ApplicationFiled: August 14, 2001Publication date: February 20, 2003Applicant: Motorola, Inc.Inventors: Robert Lempkowski, Marc Chason
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Publication number: 20030025113Abstract: The performance of nitride based diodes is currently limited by the resistivity of the ohmic contacts to the p-type GaN. The large value of the contact resistance contributes to a large voltage for device operation. This in turn causes device heating, making cw operation difficult and limiting the device lifetime. A layer of GaP or GaNP alloy between the GaN and the metal contact layer serves to bridge the energetic barrier between the GaN valence band and the metal Fermi level, thus enhancing the hole injection and reducing the contact resistance.Type: ApplicationFiled: July 31, 2001Publication date: February 6, 2003Inventor: Christian G. Van De Walle
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Patent number: 6515299Abstract: An insulating film 103 for making an under insulating layer 104 is formed on a quartz or semiconductor substrate 100. Recesses 105a to 105d corresponding to recesses 101a to 101d of the substrate 100 are formed on the surface of the insulating film 103. The surface of this insulating film 103 is flattened to form the under insulating layer 104. By this flattening process, the distance L1, L2, . . . , Ln between the recesses 106a, 106b, 106d of the under insulating layer 104 is made 0.3 &mgr;m or more, and the depth of the respective recesses is made 10 nm or less. The root-mean-square surface roughness of the surface of the under insulating film 104 is made 0.3 nm or less. By this, in the recesses 106a, 106b, 106d, it can be avoided to block crystal growth of the semiconductor thin film, and crystal grain boundaries can be substantially disappeared.Type: GrantFiled: June 16, 2000Date of Patent: February 4, 2003Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Shunpei Yamazaki, Akiharu Miyanaga, Toru Mitsuki, Hisashi Ohtani
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Patent number: 6507091Abstract: An indium-implanted transistor is provided. The transistor has a silicon channel region that includes a buried layer of an Si1−xGex alloy into which indium is implanted, with 10−5≦x≦4×10−1. A first method for fabricating an indium-implanted transistor is also provided. A multilayer composite film is produced on at least one region of a surface of a silicon substrate where a channel region of the transistor is to be formed. The multilayer composite film includes at least one Si1−xGex alloy layer, in which 10−5≦x≦4×10−1, and an external silicon layer. Indium is implanted into the Si1−xGex alloy layer, and fabrication of the transistor is completed so as to produce the transistor with a channel region that includes a buried Si1−xGex alloy layer. Additionally, a second method for fabricating an indium-implanted transistor is provided.Type: GrantFiled: February 29, 2000Date of Patent: January 14, 2003Assignee: STMicroelectronics S.A.Inventors: Thomas Skotnicki, Jérôme Alieu
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Patent number: 6503771Abstract: A semiconductor device including a conductive substrate or a first conductive layer formed on the substrate, a non-single-crystal semiconductor layer member is disposed on the conductive substrate or the conductive layer, the non-single-crystal semiconductor layer member having at least one intrinsic, non-single-crystal semiconductor layer, and a second conductive layer disposed on the non-single-crystal semiconductor layer. The intrinsic non-single-crystal semiconductor layer contains sodium and oxygen in very low concentrations where each concentration is 5×1018 atoms/cm3 or less.Type: GrantFiled: October 26, 1999Date of Patent: January 7, 2003Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventor: Shunpei Yamazaki
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Publication number: 20020195602Abstract: High quality epitaxial layers of monocrystalline materials are grown overlying multiple sides of a monocrystalline substrate such as large silicon wafers by forming a compliant substrate for growing the monocrystalline layers. An accommodating buffer layers comprises layers of monocrystalline oxide spaced apart from the silicon wafer by amorphous interface layers of silicon oxide. The amorphous interface layers dissipate strain and permit the growth of high quality monocrystalline oxide accommodating buffer layers. The accommodating buffer layers are lattice matched to both the underlying silicon wafer and the overlying monocrystalline material layers. Any lattice mismatch between the accommodating buffer layers and the underlying silicon substrate is taken care of by the amorphous interface layers.Type: ApplicationFiled: June 21, 2001Publication date: December 26, 2002Applicant: MOTOROLA, INC.Inventor: Tomasz Klosowiak
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Patent number: 6492659Abstract: To fabricate a crystalline semiconductor film with controlled locations and sizes of the crystal grains, and to utilize the crystalline semiconductor film in the channel-forming region of a TFT in order to realize a high-speed operable TFT. A translucent insulating thermal conductive layer 2 is provided in close contact with the main surface of a substrate 1, and an insular or striped first insulating layer 3 is formed in selected regions on the thermal conductive layer. A second insulating layer 4 and semiconductor film 5 are laminated thereover. The semiconductor film 5 is first formed with an amorphous semiconductor film, and then crystallized by laser annealing. The first insulating layer 3 has the function of controlling the rate of heat flow to the thermal conductive layer 2, and the temperature distribution difference on the substrate 1 is utilized to form a single-crystal semiconductor film on the first insulating layer 3.Type: GrantFiled: May 12, 2000Date of Patent: December 10, 2002Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Shunpei Yamazaki, Yasuyuki Arai
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Publication number: 20020163042Abstract: There is provided a semiconductor device having a new structure which allows a high reliability and a high field effect mobility to be realized in the same time. In an insulated gate transistor having an SOI structure utilizing a mono-crystal semiconductor thin film on an insulating layer, pinning regions are formed at edge portions of a channel forming region. The pinning regions suppress a depletion layer from spreading from the drain side and prevent a short-channel effect. In the same time, they also function as a path for drawing out minority carriers generated by impact ionization to the outside and prevent a substrate floating effect from occurring.Type: ApplicationFiled: June 28, 2002Publication date: November 7, 2002Applicant: Semiconductor Energy Laboratory Co., Ltd., a Japanese corporationInventors: Shunpei Yamazaki, Takeshi Fukunaga
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Publication number: 20020125475Abstract: A method and a layered heterostructure for forming p-channel field effect transistors is described incorporating a plurality of semiconductor layers on a semiconductor substrate, a composite channel structure of a first epitaxial Ge layer and a second compressively strained SiGe layer having a higher barrier or a deeper confining quantum well and having extremely high hole mobility. The invention overcomes the problem of a limited hole mobility for a p-channel device with only a single compressively strained SiGe channel layer.Type: ApplicationFiled: November 20, 2001Publication date: September 12, 2002Inventors: Jack Oon Chu, Richard Hammond, Khalid Ezzeldin Ismail, Steven John Koester, Patricia May Mooney, John A. Ott