Abstract: The method and system for selenization in fabricating CIS and/or CIGS based thin film solar cell overlaying cylindrical glass substrates. The method includes providing a substrate, forming an electrode layer over the substrate and depositing a precursor layer of copper, indium, and/or gallium over the electrode layer. The method also includes disposing the substrate vertically in a furnace. Then a gas including a hydrogen species, a selenium species and a carrier gas are introduced into the furnace and heated to between about 350° C. and about 450° C. to at least initiate formation of a copper indium diselenide film from the precursor layer.

Abstract: A transistor having a narrow bandgap semiconductor source/drain region is described. The transistor includes a gate electrode formed on a gate dielectric layer formed on a silicon layer. A pair of source/drain regions are formed on opposite sides of the gate electrode wherein said pair of source/drain regions comprise a narrow bandgap semiconductor film formed in the silicon layer on opposite sides of the gate electrode.

Abstract: Provided are a transistor, a method of manufacturing the transistor, and an electronic device including the transistor. The transistor may include a gate insulator of which at least one surface is treated with plasma. The surface of the gate insulator may be an interface that contacts a channel layer. The interface may be treated with plasma by using a fluorine (F)-containing gas, and thus may include fluorine (F). The interface treated with plasma may suppress the characteristic variations of the transistor due to light.

Abstract: A manufacturing method of nitride semiconductor light emitting elements, which can reliably form a mechanically stable wiring electrode leading from a light emitting element surface. A structure protective sacrifice layer is formed around a first electrode layer on a device structure layer beforehand, and after separation of the device structure layer into respective portions for the light emitting elements, the resultant is stuck to a support substrate. Subsequently, forward tapered grooves reaching the structure protective sacrifice layer are formed, and the inverse tapered portion formed outward of the forward tapered groove is lifted off in a lift-off step. Thus, an insulating layer is formed on the forward tapered side walls of the light emitting element, and a wiring electrode layer electrically connected to the second electrode layer on the principal surface of the light emitting element is formed on the insulating layer.

Abstract: A method for manufacturing a solar cell including a substrate, a first electrode layer, a semiconductor layer, and a second electrode layer, includes forming a first sacrificial layer on a portion of a surface of the substrate; forming the first electrode layer on the substrate and on the first sacrificial layer; and dividing the first electrode layer by removing the first sacrificial layer and a portion of the first electrode layer formed on the first sacrificial layer.

Abstract: This invention discloses a solution-based synthesis of cesium tin tri-iodide (CsSnI3) film. More specifically, the invention is directed to a solution-based drop-coating synthesis of cesium tin tri-iodide (CsSnI3) films. CsSnI3 films are ideally suited for a wide range of applications such as light emitting and photovoltaic devices.

Abstract: According to one embodiment, a semiconductor light emitting device includes a first semiconductor layer of a first conductivity type and having a major surface, a second semiconductor layer of a second conductivity type, and a light emitting layer provided between the first and second semiconductor layers. The major surface is opposite to the light emitting layer. The first semiconductor layer has structural bodies provided in the major surface. The structural bodies are recess or protrusion. A centroid of a first structural body aligns with a centroid of a second structural body nearest the first structural. hb, rb, and Rb satisfy rb/(2·hb)?0.7, and rb/Rb<1, where hb is a depth of the recess, rb is a width of a bottom portion of the recess, and Rb is a width of the protrusion.

Abstract: A precursor solution for producing a semiconductor includes at least one of an alkali metal or an alkali metal compound dissolved in a solvent, and a metal chalcogenide dissolved in the solvent. A method of producing a precursor solution for a semiconductor includes preparing a first precursor solution that has at least one of an alkali metal or an alkali metal compound dissolved in a first solvent, preparing a second precursor solution that has a metal chalcogenide dissolved in a second solvent, and combining the first and second precursor solutions to obtain the precursor solution for producing the semiconductor. A method of producing a semiconductor device includes providing a precursor solution for producing a semiconductor layer on a substructure, and forming a layer of the precursor solution on the substructure. The precursor solution includes at least one of an alkali metal or an alkali metal compound dissolved in a solvent, and a metal chalcogenide dissolved in the solvent.

Abstract: Dummy electrodes (15) are disposed on wiring connected to first electrodes (2) of the substrate (1), outside a junction region containing all of the first electrodes (2) and second electrodes (6) and in bonding resin (4), the dummy electrodes (15) not being involved in electrical connection between the substrate (1) and the component (5). When conductive particles (3) in the bonding resin (4) are melted by heating, molten solder self-assembles and solidifies between the first electrodes (2) and the second electrodes (6) and on the dummy electrodes (15). With this configuration, the solder self-assembles between the adjacent dummy electrodes (15) and causes a solder short circuit. Thus it is possible to eliminate excessive solder supply between the adjacent first electrodes (2) and the adjacent second electrodes (6), thereby preventing short circuits between the adjacent first electrodes (2) and the adjacent second electrodes (6).

Abstract: A switching circuit includes a switching device including the first and second main electrodes and a control electrode; and a driver including: a first rectifying device having an anode terminal connected to the first main electrode of the switching device; a first driving device having a first main electrode connected to a cathode terminal of the first rectifying device and a second main electrode connected to the control electrode of the switching device; a second driving device having a first main electrode connected to the control electrode of the switching device and a second main electrode connected to the second main electrode of the switching device; and input terminals receiving control signals inputted to a control electrode of the first driving device and a control electrode of the second driving device.

Abstract: Self-aligning fabrication methods for forming memory access devices comprising a doped chalcogenide material. The methods may be used for forming three-dimensionally stacked cross point memory arrays. The method includes forming an insulating material over a first conductive electrode, patterning the insulating material to form vias that expose portions of the first conductive electrode, forming a memory access device within the vias of the insulating material and forming a memory element over the memory access device, wherein data stored in the memory element is accessible via the memory access device. The memory access device is formed of a doped chalcogenide material and formed using a self-aligned fabrication method.

Abstract: Provided is an oxynitride semiconductor comprising a metal oxynitride. The metal oxynitride contains Zn and In and at least one element selected from the group consisting of Ga, Sn, Mg, Si, Ge, Y, Ti, Mo, W, and Al. The metal oxynitride has an atomic composition ratio of N, N/(N+O), of 7 atomic percent or more to 80 atomic percent or less.

Abstract: A semiconductor device includes a nitride semiconductor stacked structure including a carrier transit layer and a carrier supply layer; a p-type nitride semiconductor layer provided over the nitride semiconductor stacked structure and including an active region and an inactive region; an n-type nitride semiconductor layer provided on the inactive region in the p-type nitride semiconductor layer; and a gate electrode provided over the active region in the p-type nitride semiconductor layer.

Abstract: A GaN based light emitting diode device which emits polarized light or light of various degrees of polarization for use in the creation of optical devices. The die are cut to different shapes, or contain some indicia that are used to represent the configuration of the weak dipole plane and the strong dipole plane. This allows for the more efficient manufacturing of such light emitting diode based optical devices.

Abstract: The present invention provides a thin film transistor substrate realizing reduced interlayer short-circuit defects in a capacitor, and a display device having the thin film transistor substrate. The thin film transistor substrate includes: a substrate; a thin film transistor having, over the substrate, a gate electrode, a gate insulating film, an oxide semiconductor layer, and a source-drain electrode in order; and a capacitor having, over the substrate, a bottom electrode, a capacitor insulating film, and a top electrode made of oxide semiconductor in order.

Abstract: An article of manufacture comprising a nanowire and methods of making the same. In one embodiment, the nanowire includes a Ga-doped trace formed on a surface of an indium oxide layer having a thickness in nano-scale, and wherein the Ga-doped trace is formed with a dimension that has a depth is less than a quarter of the thickness of the indium oxide layer. In one embodiment, the indium oxide layer, which is optically transparent and electrically insulating, comprises an In2O3 film, and the thickness of the indium oxide layer is about 40 nm, and the depth of the nanowire is less than 10 nm.

Abstract: A light emitting device includes a first semiconductor layer of a first conductivity type, an active layer adjacent to the first semiconductor layer, a second semiconductor layer of a second conductivity type and provided adjacent to the active layer, and a passivation layer provided on a side surface of the active layer. The passivation layer may be a semiconductor layer of one of the first conductivity type, the second conductivity type or a first undoped semiconductor layer. A first electrode may be coupled to the first semiconductor layer and a second electrode may be coupled to the second semiconductor layer.

Abstract: A light emitting apparatus may include a gate metal positioned between a p-type contact and an n-type contact, a gate oxide or other dielectric stack positioned below and attached to the gate metal, a Ge or Si1-zGez channel positioned below and attached to the gate dielectric stack, a buffer, and a silicon substrate positioned below and attached to the buffer. The light emitting apparatus may alternatively include a gate metal positioned between a p-type contact and an n-type contact, a wide bandgap semiconductor positioned below and attached to the gate metal, a Ge or Si1-zGez channel positioned below and attached to the wide bandgap semiconductor, a buffer, and a silicon substrate positioned below and attached to the buffer. Embodiments of the light emitting apparatus may be configured for use in current-injected on-chip lasers, light emitting diodes or other light emitting devices.

Abstract: A plurality of bit lines s arranged crossing a plurality of first word lines. A first diode is arranged at each cross point of the first word lines and the bit lines. A cathode of the first diode is connected to one of the first word lines. A first variable resistance film configuring the first diode is provided between the anodes of the first diodes and the bit lines, and configures a first memory cell together with each of the first diodes, and further, is used in common to the first diodes.

Abstract: A manufacturing method of a group III nitride semiconductor includes the steps of: depositing a metal layer on an AlN template substrate or an AlN single crystal substrate formed by depositing an AlN single crystal layer with a thickness of not less than 0.1 ?m nor more than 10 ?m on a substrate made of either one of sapphire, SiC, and Si; forming a metal nitride layer having a plurality of substantially triangular-pyramid-shaped or triangular-trapezoid-shaped microcrystals by performing a heating nitridation process on the metal layer under a mixed gas atmosphere of ammonia; and depositing a group III nitride semiconductor layer on the metal nitride layer.

Abstract: Methods and devices are provided for forming multi-nary semiconductor. In one embodiment, a method is provided comprising of depositing a precursor material onto a substrate, wherein the precursor material may include or may be used with an additive to minimize concentration of group IIIA material such as Ga in the back portion of the final semiconductor layer. The additive may be a non-copper Group IB additive in elemental or alloy form. Some embodiments may use both selenium and sulfur, forming a senary or higher semiconductor alloy.

Abstract: To provide a semiconductor substrate, a semiconductor device, a light emitting device and an electronic device which have a low price, a long lifetime, and a high luminescent efficiency, and moreover are capable of being bent. A graphite substrate having heat resistance and having flexibility with respect to external force, and a first semiconductor layer, provided on the graphite substrate, which is made of a nitride of the Group XIII are included, and a method such as pulse sputter deposition can be used in forming the first semiconductor layer on the graphite substrate, to thereby allow inexpensive manufacture to be possible. In addition, since the nitride of the Group XIII is an inorganic substance, it has a long lifetime, and thus a high luminescent efficiency can be obtained. Moreover, since the graphite substrate has flexibility with respect to external force, it can also be bent.

Abstract: To provide a p-type semiconductor material having a band matching with a hole injection layer and suitable for an anode electrode that can be formed on a glass substrate or a polymer substrate, and to provide a semiconductor device. In the p-type semiconductor material, 1×1018 to 5×1020 cm?3 of Ag is contained in a compound containing Zn and Se, and the semiconductor device includes a substrate and a p-type electrode layer arranged on this substrate and having the aforementioned p-type semiconductor material.

Abstract: A method for growing a semi-polar nitride semiconductor thin film via metalorganic chemical vapor deposition (MOCVD) on a substrate, wherein a nitride nucleation or buffer layer is grown on the substrate prior to the growth of the semi-polar nitride semiconductor thin film.

Abstract: Disclosed herein are processes for making quaternary chalcogenide wafers. The process comprises milling quaternary chalcogenide crystals to form milled particles, and then compressing the milled particles to form a quaternary chalcogenide wafer. The quaternary chalcogenide wafers are useful for forming solar cells.

Abstract: This invention describes a semiconductor material of general formula (I) Me12Me21-xMe3xMe4(C11-yC2y)4, in which x stands for a numeric value from 0 to 1, and y stands for a numeric value of 0 to 1, as well as its use as an absorber material in a solar cell. The metal Mel is a metal which is selected from the metals in group 11 of the periodic table of the elements (Cu, Ag or Au). The metals Me2 and Me3 are selected from the elements of the 12th group of the periodic table of elements (Zn, Cd & Hg). The metal Me4 is a metal which is selected from the 4th main group of the periodic table of elements (C, Si, Ge, Sn and Pb). The non-metals C1 and C2 are selected from the group of chalcogenides (S, Se and Te).

Abstract: Material layer structures that have high mobility, a high conduction band barrier and materials that can be implanted to enable higher performance FET device. The structures contain a quantum well layer disposed between two barriers and disposed above a buffer layer and a substrate.

Abstract: Thin film photovoltaic devices are provided that generally include a transparent conductive oxide layer on the glass, a multi-layer n-type stack on the transparent conductive oxide layer, and a cadmium telluride layer on the multi-layer n-type stack. The multi-layer n-type stack generally includes a first layer and a second layer, where the first layer comprises cadmium and sulfur and the second layer comprises cadmium and oxygen. The multi-layer n-type stack can, in certain embodiments, include additional layers (e.g., a third layer, a fourth layer, etc.). Methods are also generally provided for manufacturing such thin film photovoltaic devices.

Abstract: A nitride semiconductor wafer is planar-processed by grinding a bottom surface of the wafer, etching the bottom surface by, e.g., KOH for removing a bottom process-induced degradation layer, chamfering by a rubber whetstone bonded with 100 wt %-60 wt % #3000-#600 diamond granules and 0 wt %-40 wt % oxide granules, grinding and polishing a top surface of the wafer, etching the top surface for eliminating a top process-induced degradation layer and maintaining a 0.5 ?m-10 ?m thick edge process-induced degradation layer.

Abstract: An optoelectronic semiconductor chip is specified, which has an active zone (20) containing a multi quantum well structure provided for generating electromagnetic radiation, which comprises a plurality of successive quantum well layers (210, 220, 230). The multi quantum well structure comprises at least one first quantum well layer (210), which is n-conductively doped and which is arranged between two n-conductively doped barrier layers (250) adjoining the first quantum well layer. It comprises a second quantum well layer (220), which is undoped and is arranged between two barrier layers (250, 260) adjoining the second quantum well layer, of which one is n-conductively doped and the other is undoped. In addition, the multi quantum well structure comprises at least one third quantum well layer (230), which is undoped and which is arranged between two undoped barrier layers (260) adjoining the third quantum well layer.

Abstract: In one aspect, a device includes a gallium nitride (GaN) layer, a first diamond layer disposed on the GaN layer, a gate structure disposed in contact with the GaN layer and the first diamond layer, and a second diamond layer having a first thermal conductivity and disposed on a second surface of the GaN layer. The gate and the first diamond layer are disposed on a first surface of the GaN layer opposite the second surface of the GaN layer.

Abstract: A system is provided for the manufacture of carbon based electrical components including, an ultraviolet light source; a substrate receiving unit whereby a substrate bearing a first layer of carbon based semiconductor is received and disposed beneath the ultraviolet light source; a mask disposed between the ultraviolet light source and the carbon based semiconductor layer; a doping agent precursor source; and environmental chemical controls, configured such that light from the ultraviolet light source irradiates a doping agent precursor and the first carbon layer.

Abstract: The semiconductor of the present invention has iron sulfide and a forbidden band control element contained in the iron sulfide. The forbidden band control element has a property capable of controlling the forbidden band of iron sulfide on the basis of the number density of the forbidden band control element in the iron sulfide. An n-type semiconductor is manufactured by incorporating a group 13 element of the IUPAC system into iron sulfide. Moreover, a p-type semiconductor is manufactured by incorporating a group Ia element into iron sulfide. A semiconductor junction device or a photoelectric converter is manufactured by using the n-type semiconductor and the p-type semiconductor.

Abstract: A semiconductor device includes a substrate, a buffer layer on the substrate, and a plurality of nitride semiconductor layers on the buffer layer. The semiconductor device further includes at least one masking layer and at least one inter layer between the plurality of nitride semiconductor layers. The at least one inter layer is on the at least one masking layer.

Abstract: A graphene transparent electrode, which comprises: at least one graphene sheet; wherein the graphene sheets electrically connect with each other by overlapping with each other, each of the graphene sheets has a diameter from 10 ?m to 1 mm, the quantity of the graphene sheets in the graphene transparent electrode is from 1 to 1000, the electrical resistance of the graphene transparent electrode is 1 ?/cm or below, and the light transmittance of the graphene transparent electrode is 70% or above. A graphene light emitting diode (gLED) and a method of fabricating the same are also disclosed.

Abstract: A selenium/Group 3a ink, comprising (a) a selenium/Group 3a complex which comprises a combination of, as initial components: a selenium component comprising selenium; an organic chalcogenide component having a formula selected from RZ—Z?R? and R2—SH; wherein Z and Z? are each independently selected from sulfur, selenium and tellurium; wherein R is selected from H, C1-20 alkyl group, a C6-20 aryl group, a C1-20 hydroxyalkyl group, an arylether group and an alkylether group; wherein R? and R2 are selected from a C1-20 alkyl group, a C6-20 aryl group, a C1-20 hydroxyalkyl group, an arylether group and an alkylether group; and, a Group 3a complex, comprising at least one Group 3a material selected from aluminum, indium, gallium and thallium complexed with a multidentate ligand; and, (b) a liquid carrier; wherein the selenium/Group 3a complex is stably dispersed in the liquid carrier.

Abstract: According to one embodiment of the present invention, a solid state electrolyte memory cell includes a cathode, an anode and a solid state electrolyte. The anode includes an intercalating material and first metal species dispersed in the intercalating material.

Abstract: A method for patterning a semiconductor surface is specified. A photoresist is applied to an outer area of a second semiconductor wafer. A surface of the photoresist that is remote from the second semiconductor wafer is patterned by impressing a patterned surface of the first wafer into the photoresist. A patterning method is applied to the surface of the photoresist, wherein a structure applied on the photoresist is transferred at least in places to the outer area of the second semiconductor wafer.

Abstract: The present invention discloses structures to increase carrier mobility using engineered substrate technologies for a solid state device. Structures employing rare-earth compounds enable heteroepitaxy of different semiconductor materials of different orientations.

Abstract: Resistance-switching oxide films, and devices therewith, are disclosed. Resistance-switching oxide films, according to certain preferred aspects of the present invention, include at least about 75 atomic percent of an insulator oxide matrix having a conducting material dopant in an amount up to about 25 atomic percent. The matrix and dopant are preferably in solid solution. The insulator oxide matrix may also preferably include about 6 to about 12 atomic percent of a conducting material dopant. According to certain aspects of the present invention, the insulator oxide matrix, the conducting material dopant, or both, may have a perovskite crystal structure. The insulator oxide matrix may preferably include at least one of LaAlO3 and CaZrO3. Preferred conducting material dopants include SrRuO3, CaRuO3, or combinations thereof.

Abstract: The invented ink-jet printing method for the construction of thin film transistors using all SWNTs on flexible plastic films is a new process. This method is more practical than all of existing printing methods in the construction TFT and RFID tags because SWNTs have superior properties of both electrical and mechanical over organic conducting oligomers and polymers which are often used for TFT. Furthermore, this method can be applied on thin films such as paper and plastic films while silicon based techniques cannot be used on such flexible films. These are superior to the traditional conducting polymers used in printable devices since they need no dopant and they are more stable. They could be used in conjunction with conducting polymers, or as stand-alone inks.

Abstract: Compound semiconductor devices and methods of doping compound semiconductors are provided. Embodiments of the invention provide post-deposition (or post-growth) doping of compound semiconductors, enabling nanoscale compound semiconductor devices including diodes and transistors. In one method, a self-limiting monolayer technique with an annealing step is used to form shallow junctions. By forming a sulfur monolayer on a surface of an InAs substrate and performing a thermal annealing to drive the sulfur into the InAs substrate, n-type doping for InAs-based devices can be achieved. The monolayer can be formed by surface chemistry reactions or a gas phase deposition of the dopant. In another method, a gas-phase technique with surface diffusion is used to form doped regions. By performing gas-phase surface diffusion of Zn into InAs, p-type doping for InAs-based devices can be achieved.

Abstract: Provided are a compound semiconductor film which is manufactured at a low temperature and exhibits excellent p-type conductivity, and a light emitting film in which the compound semiconductor film and a light emitting material are laminated and with which high-intensity light emission can be realized. The compound semiconductor film has a composition represented by a Cu2—Zn—IV—S4 type, in which the IV is at least one of Ge and Si. The light emitting film includes the light emitting material and the compound semiconductor film laminated on a substrate in the stated order.

Abstract: The semiconductor of the present invention has iron sulfide and a forbidden band control element contained in the iron sulfide. The forbidden band control element has a property capable of controlling the forbidden band of iron sulfide on the basis of the number density of the forbidden band control element in the iron sulfide. An n-type semiconductor is manufactured by incorporating a group 13 element of the IUPAC system into iron sulfide. Moreover, a p-type semiconductor is manufactured by incorporating a group Ia element into iron sulfide. A semiconductor junction device or a photoelectric converter is manufactured by using the n-type semiconductor and the p-type semiconductor.

Abstract: Device and method of forming a device in which a substrate (10) is fabricated with at least part of an electronic circuit for processing signals. A bulk single crystal material (14) is formed on the substrate, either directly on the substrate (10) or with an intervening thin film layer or transition region (12). A particular application of the device is for a radiation detector.

Abstract: Device and method of forming a device in which a substrate (10) is fabricated with at least part of an electronic circuit for processing signals. A bulk single crystal material (14) is formed on the substrate, either directly on the substrate (10) or with an intervening thin film layer or transition region (12). A particular application of the device is for a radiation detector.

Abstract: In a thin film transistor (1), a gate insulating layer (4) is formed on a gate electrode (3) formed on an insulating substrate (2). Formed on the gate insulating layer (4) is a semiconductor layer (5). Formed on the semiconductor layer (5) are a source electrode (6) and a drain electrode (7). A protective layer (8) covers them, so that the semiconductor layer (5) is blocked from an atmosphere. The semiconductor layer (5) (active layer) is made of, e.g., a semiconductor containing polycrystalline ZnO to which, e.g., a group V element is added. This allows practical use of a semiconductor device which has an active layer made of zinc oxide and which includes an protective layer for blocking the active layer from an atmosphere.

Abstract: A nitride compound semiconductor element according to the present invention is a nitride compound semiconductor element including a substrate 1 having an upper face and a lower face and a semiconductor multilayer structure 40 supported by the upper face of the substrate 1, such that the substrate 1 and the semiconductor multilayer structure 40 have at least two cleavage planes. At least one cleavage inducing member 3 which is in contact with either one of the two cleavage planes is provided, and a size of the cleavage inducing member 3 along a direction parallel to the cleavage plane is smaller than a size of the upper face of the substrate 1 along the direction parallel to the cleavage plane.

Abstract: The present invention relates to devices, particularly photovoltaic devices, incorporating Group IIB/VA semiconductors such phosphides, arsenides, and/or antimonides of one or more of Zn and/or Cd. In particular, the present invention relates to methodologies, resultant products, and precursors thereof in which electronic performance of the semiconductor material is improved by causing the Group IIB/VA semiconductor material to react with at least one metal-containing species (hereinafter co-reactive species) that is sufficiently co-reactive with at least one Group VA species incorporated into the Group IIB/VA semiconductor as a lattice substituent (recognizing that the same and/or another Group VA species also optionally may be incorporated into the Group IIB/VA semiconductor in other ways, e.g., as a dopant or the like).

Abstract: A semiconductor component and a method for manufacturing such a semiconductor component which has a resistance behavior which depends heavily on the temperature. This resistance behavior is obtained by a special multi-layer structure of the semiconductor component, one layer being designed in such a way that, for example, multiple p-doped regions are present in an n-doped region, said regions being short-circuited on one side via a metal-plated layer. For example, the semiconductor component may be used for reducing current peaks, by being integrated into a conductor. In the cold state, the semiconductor component has a high resistance which becomes significantly lower when the semiconductor component is heated as a result of the flowing current.