Abstract: A gallium containing crystalline material. The material comprises a bulk semi-polar gallium indium containing crystalline material having a thickness of about 20 nanometers to about 1000 nanometers. The material includes a spatial width dimension of no greater than about 10 microns characterizing the thickness of the bulk semi-polar gallium indium containing crystalline material. The material includes a photoluminescent characteristic of the crystalline material having a first wavelength, which is at least five nanometers greater than a second wavelength, which is derived from an indium gallium containing crystalline material grown on a growth region of greater than about 15 microns.

Abstract: The present invention provides a phase change non-volatile memory material comprising a base material and at least one non-metallic light element selected from the group consisting of boron, carbon, nitrogen and oxygen, wherein the base material has a composition which corresponds to either that of congruent melting of the type with a minimum melting point or that of eutectic melting within the range of ±0.15 atomic fraction for each constituent element, thereby having a melting temperature of 600° C. or lower. The phase change non-volatile memory material according to the present invention may be utilized to reduce the electric power needed for reset/set operation and thermal interference between memory cells.

Abstract: The invention provides methods and devices for fabricating printable semiconductor elements and assembling printable semiconductor elements onto substrate surfaces. Methods, devices and device components of the present invention are capable of generating a wide range of flexible electronic and optoelectronic devices and arrays of devices on substrates comprising polymeric materials. The present invention also provides stretchable semiconductor structures and stretchable electronic devices capable of good performance in stretched configurations.

Abstract: A method of dividing single crystals, particularly of plates of parts thereof, is proposed, which can comprise: pre-adjusting the crystallographic cleavage plane (2?) relative to the cleavage device, setting a tensional intensity (K) by means of tensional fields (3?, 4?), determining an energy release rate G(?) in dependence from a possible deflection angle (?) from the cleavage plane (2?) upon crack propagation, controlling the tensional fields (3?, 4?) such that the crack further propagates in the single crystal, wherein G(0)?2?e(0) and simultaneously at least one of the following conditions is satisfied: ? ? G ? ? ? ? = 0 ? 2 ? ? e h ? ? if ? ? ? 2 ? G ? ? 2 ? 0 ? ? or ( 2.1 ) ? ? G ? ? ? ? 2 ? ? e h ? ? ? ? : ? ? 1 < ? < ? 2 , ( 2.

Abstract: It is an object to provide a p-type ZnS based semiconductor material having a low resistance which can easily form an ohmic contact to a metallic material. Moreover, the invention provides a semiconductor device and a semiconductor light emitting device which include an electrode having a low resistance on a substrate other than a single crystal substrate, for example, a glass substrate. The semiconductor material according to the invention is used as a hole injecting electrode layer of a light emitting device and has a transparent property in a visible region which is expressed in a composition formula of Zn(1-?-?-?)Cu?Mg?Cd?S(1-x-y)SexTey (0.004???0.4, ??0.2, ??0.2, 0?x?1, 0?y?0.2, and x+y?1).

Abstract: A system is provided for the manufacture of carbon based electrical components including, an ultraviolet light source; a substrate receiving unit whereby a substrate bearing a first layer of carbon based semiconductor is received and disposed beneath the ultraviolet light source; a mask disposed between the ultraviolet light source and the carbon based semiconductor layer; a doping agent precursor source; and environmental chemical controls, configured such that light from the ultraviolet light source irradiates a doping agent precursor and the first carbon layer.

Abstract: Gallium nitride material devices and related processes are described. In some embodiments, an N-face of the gallium nitride material region is exposed by removing an underlying region.

Abstract: A Schottky electrode including a WNx layer on an n-type GaN layer. A crystal plane of the n-type GaN layer is in contact with a crystal plane of the WNx layer. The crystal plane of the n-type GaN layer is a (0001)-plane, and the crystal plane of the WNx layer is (111)-oriented. The WNx layer may be an electrode layer having an NaCl-type structure including at least one metal selected from the group consisting of zirconium, hafnium, niobium, tantalum, molybdenum and tungsten, and at least one element selected from nitrogen and carbon. Further, the lattice constant of the electrode layer is preferably 0.95 to 1.05 times the a-axis lattice constant of the n-type GaN layer, multiplied by 2(1/2).

Abstract: The present invention discloses structures to increase carrier mobility using engineered substrate technologies for a solid state device. Structures employing rare-earth compounds enable heteroepitaxy of different semiconductor materials of different orientations.

Abstract: Thermal boundary resistances within nitride semiconductor LEDs are reduced or eliminated by forming a thick nitride epitaxial layer, which can be separated from a growth substrate, and by reducing the number of thermal boundary layers during laser lift-off. The thermal boundary resistances within nitride semiconductor LEDs can also be reduced or eliminated by forming a plurality of thin nitride epitaxial layers.

Abstract: Herein is described a method for identifying semiconductor radiation detector materials based on the mobility of internally generated electrons and holes. It was designed for the early stages of exploration, when samples are not available as single crystals, but as crystalline powders. Samples are confined under pressure in an electric field and the increase in current resulting from exposure to a high-intensity source of ionization current (e.g., 60Co gamma rays) is measured. A pressure cell device is described herein to carry out the method. For known semiconductors, the d.c. ionization current depends on voltage according to the Hecht equation, and for known insulators the d.c. ionization current is below detection limits. This shows that the method can identify semiconductors in spite of significant carrier trapping. Using this method and pressure cell, it was determined that new materials BiOI, PbIF, BiPbO2Cl, BiPbO2Br, BiPbO2I, Bi2GdO4Cl, Pb3O2I2, and Pb5O4I2 are semiconductors.

Abstract: A BST microwave device includes a single crystal oxide wafer. A silicon dioxide layer is formed on the single crystal oxide layer. A silicon substrate is bonded on the silicon dioxide layer. A BST layer is formed on the single crystal oxide layer.

Abstract: A semiconductor device includes a semiconductor layer, an electrode connected to the semiconductor layer, a sacrificial metal layer connected to the electrode and made of a metal having higher ionization tendency than the material of the semiconductor layer and the material of the electrode.

Abstract: A method for producing a semiconductor component, and a semiconductor component, having a metallic gate electrode deposited onto a semiconductor layer, with the gate electrode having a gate foot and a gate head. The component is produced by depositing a first layer of aluminum on the semiconductor layer, depositing a second layer of a second metal on the first layer, depositing at least one additional layer (G3) of an additional metal, different from the second metal, on the second layer, and carrying out a temperature treatment at elevated temperature.

Abstract: A method for forming an etch-stop layer and a resulting structure fabricated therefrom. The etch-stop layer has a semiconductor layer having a first surface and a boron layer formed below the first surface of the semiconductor layer. The boron layer has a full-width half-maximum (FWHM) thickness value of less than 100 nanometers. The boron layer is formed by a chemical vapor deposition (CVD) system.

Abstract: A nitride semiconductor device with a p electrode having no resistance between itself and other electrodes, and a method of manufacturing the same are provided. A p electrode is formed of a first Pd film, a Ta film, and a second Pd film, which is an antioxidant film for preventing oxidation of the Ta film, and on a p-type contact layer of a nitride semiconductor. On the second Pd film, a pad electrode is formed. The second Pd film as an antioxidant film is formed on the entire upper surface of the Ta film which forms the p electrode, to prevent oxidation of the Ta film. This inhibits the resistance between the p electrode and the pad electrode, thereby preventing a failure in contact between the p electrode and the pad electrode and providing the low-resistance p electrode.

Abstract: Semiconductor devices, in particular nitride semiconductor devices for use in the manufacture of laser diodes, prevent peeling-off of the electrode, and at the same time reduces the complexity of processes and a reduction in yield. A nitride semiconductor device according to the invention includes a P-type nitride semiconductor layer with a ridge on its surface, an SiO2 film covering at least the side face of the ridge, an adherence layer formed on a surface of the SiO2 film and composed mainly of silicon, and a P-type electrode formed on the upper surface of the ridge and on a surface of the adherence layer.

Abstract: The present invention includes a first step of forming a nitride semiconductor layer by metal organic chemical vapor deposition by using a first carrier gas containing a nitrogen carrier gas and a hydrogen carrier gas of a flow quantity larger than that of the nitrogen carrier gas to thereby supply a raw material containing Mg and a Group V raw material containing N, and a second step of lowering a temperature by using a second carrier gas to which a material containing N is added, and hence solves the problems.

Abstract: An aluminum nitride single-crystal multi-layered substrate comprising an aluminum nitride single-crystal layer formed by direct reduction nitridation on a single-crystal ?-alumina substrate such as a sapphire substrate and an edge-type dislocation layer having a thickness of 10 nm or less in the vicinity of the interface between the both crystals. Threading dislocation is rarely existent in the aluminum nitride single-crystal layer existent on the surface. It is useful as a semiconductor device substrate.

Abstract: A transparent semiconductor thin film 40 having low carrier concentration and a large energy band gap is produced by forming a thin film which contains indium oxide and an oxide of a positive divalent element, and then oxidizing or crystallizing the thin film.

Abstract: The present invention provides a process for forming a semiconductor film, comprising the steps of applying a semiconductor particle dispersion liquid to a substrate surface by spray coating in such a manner that the atomized droplets of the dispersion liquid discharged from the spray coater have a mean diameter of about 30 ?m or less, and drying the coating to form a porous semiconductor film; and use of the semiconductor film obtained by the process.

Abstract: A semiconductor optical device comprises a first conductive type III-V compound semiconductor layer, a second conductive type III-V compound semiconductor layer, and an active region. The first conductive type III-V compound semiconductor layer is provided on a substrate. The second conductive type III-V compound semiconductor layer is provided on the substrate. The active region is provided between the first conductive type III-V compound semiconductor layer and the second conductive type III-V compound semiconductor layer. The active region includes a III-V compound semiconductor layer. The III-V compound semiconductor layer contains nitrogen and arsenic as V-group element. The hydrogen concentration of the III-V compound semiconductor layer is greater than 6×1016 cm?3. The III-V compound semiconductor layer of the active region is doped with n-type dopant.

Abstract: A method and associated composition for chemical mechanical planarization of a chalcogenide-containing substrate (e.g., germanium/antimony/tellurium (GST)-containing substrate) are described. The composition and method afford low defect levels as well as low dishing and local erosion levels on the chalcogenide-containing substrate during CMP processing.

Abstract: A chalcogenide-based programmable conductor memory device and method of forming the device, wherein a nanoparticle is provided between an electrode and a chalcogenide glass region. The method of forming the nanoparticle utilizes a template over the electrode or random deposition of the nanoparticle.

Abstract: An article of manufacture having a substrate having a top surface and a first layer on the top surface. The top surface contains titanium carbide, vanadium carbide, zirconium carbide, niobium carbide, hafnium carbide, tantalum carbide, tungsten carbide, chromium nitride, molybdenum nitride, tungsten nitride, titanium nitride, vanadium nitride, zirconium nitride, or a combination thereof. The first layer contains one or more group III-V metal nitrides.

Abstract: The present invention discloses an anodically bonded vacuum cell structure with a glass substrate including a cavity, and a substrate deposited on the glass substrate, thereby enclosing the cavity to form a bonding interface. The bonding interface having silicon such that the substrate includes a layer of silicon or a secondary substrate with silicon layer bonded onto the secondary substrate.

Abstract: A semiconductor structure includes a first conductive layer coupled to a transistor. A first dielectric layer is over the first conductive layer. A second conductive layer is within the first dielectric layer, contacting a portion of a top surface of the first conductive layer. The second conductive layer includes a cap portion extending above a top surface of the first dielectric layer. A first dielectric spacer is between the first dielectric layer and the second conductive layer. A phase change material layer is above a top surface of the second conductive layer. A third conductive layer is over the phase change material layer. A second dielectric layer is over the first dielectric layer. A second dielectric spacer is on a sidewall of the cap portion, wherein a thermal conductivity of the second dielectric spacer is less than that of the first dielectric layer or that of the second dielectric layer.

Abstract: A porogen material for forming a dielectric porous film. The porogen material may include a silicon based dielectric precursor and a silicon containing porogen. The porous film may have a substantially uniform dielectric constant value throughout. Methods of forming the porous film as well as semiconductor devices employing circuit features isolated by the porous film are also present.

Abstract: Provided are a wafer with the characteristics of abrupt metal-insulator transition (MIT), and a heat treatment apparatus and method that make it possible to mass-produce a large-diameter wafer without directly attaching the wafer to a heater or a substrate holder. The heat treatment apparatus includes a heater applying heat to a wafer having the characteristics of abrupt MIT and one surface covered with a thermally opaque film, and a plurality of fixing units formed along an edge portion of a top surface of the heater to fix the wafer to the heater.

Abstract: A gallium nitride-based semiconductor device has a p-type layer that is a gallium nitride (GaN) compound semiconductor layer containing a p-type impurity and exhibiting p-type conduction. The p-type layer includes a top portion and an inner portion located under the top portion. The inner portion contains the p-type impurity and, in combination therewith, hydrogen. The top portion includes a region containing a Group III element and a Group V element at a non-stoichiometric atomic ratio.

Abstract: A self-supported nitride semiconductor substrate of 10 mm or more in diameter having an X-ray diffraction half width of 500 seconds or less in at least one of a {20-24} diffraction plane and a {11-24} diffraction plane.

Abstract: An integrated circuit structure comprising a boron etch-stop layer on a surface of the integrated circuit structure having a full-width half-maximum (FWHM) thickness value less than 100 nanometers, wherein the boron etch-stop layer is substantially free of germanium and carbon. In one embodiment, the boron etch-stop layer has a FWHM thickness value less than 20 nanometers and may contain added germanium or carbon. Systems and devices containing same are also disclosed. Chemical vapor deposition (CVD) may be used to form the boron etch-stop layer.

Abstract: A phase change memory cell is disclosed. The phase change memory cell includes a first thin film spacer and a second thin film spacer. The first thin film spacer defines a sub-lithographic dimension and is electrically coupled to a first electrode. The second thin film spacer defines a sub-lithographic dimension and is electrically coupled between a second electrode and the first thin film spacer. In this regard, the phase change memory cell is formed at a boundary where the first thin film spacer electrically contacts the second thin film spacer.

Abstract: A memory comprises a number of word lines in a first direction, a number of bit lines in a second direction, each coupled to at least one of the word lines, and a number of memory elements, each coupled to one of the word lines and one of the bit lines. Each memory element comprises a top electrode for connecting to a corresponding word line, a bottom electrode for connecting to a corresponding bit line, a resistive layer on the bottom electrode, and at least two separate liners, each liner having resistive materials on both ends of the liner and each liner coupled between the top electrode and the resistive layer.

Abstract: A method of forming a microelectronic device includes forming a groove structure having opposing sidewalls and a surface therebetween on a substrate to define a nano line arrangement region. The nano line arrangement region has a predetermined width and a predetermined length greater than the width. At least one nano line is formed in the nano line arrangement region extending substantially along the length thereof and coupled to the surface of the groove structure to define a nano line structure. Related devices are also discussed.

Abstract: A memory cell includes a substrate, a first electrode disposed over the substrate a resistance element disposed over the first electrode, a second electrode disposed over the resistance element, the second electrode comprising an alloy, the alloy being formed from a first metal layer deposited on the resistance element, a second metal layer deposited on the first metal layer and heating the first and second metal layers.

Abstract: Enhancement mode, field effect transistors wherein at least a portion of the transistor structure may be substantially transparent. One variant of the transistor includes a channel layer comprising a substantially insulating, substantially transparent, material selected from ZnO, SnO2, or In2O3. A gate insulator layer comprising a substantially transparent material is located adjacent to the channel layer so as to define a channel layer/gate insulator layer interface. A second variant of the transistor includes a channel layer comprising a substantially transparent material selected from substantially insulating ZnO, SnO2 or In2O3, the substantially insulating ZnO, SnO2, or In2O3 being produced by annealing. Devices that include the transistors and methods for making the transistors are also disclosed.

Abstract: Phase change memory devices and methods for fabricating the same. An exemplary phase change memory device comprises a conductive element formed in a dielectric layer. A phase change material layer is formed in the dielectric layer. A conductive layer extends in the dielectric layer to respectively electrically connect the phase change layer and a sidewall of the conductive element.

Abstract: According to one embodiment of the present invention, a solid state electrolyte memory cell includes a cathode, an anode and a solid state electrolyte. The anode includes an intercalating material and first metal species dispersed in the intercalating material.

Abstract: A buffer structure comprising a compositionally graded layer of a nitride alloy comprising two or more Group IIIB elements, for example La, Y, Sc or Ac, is used to modify a silicon substrate to produce a universal substrate on which a range of target materials, for example GaN, may be deposited to produce semiconductor devices for electronic and optical applications. The resulting lattice parameter L varies with thickness T through the structure.

Abstract: A semiconductor workpiece including a substrate, a relaxed buffer layer including a graded portion formed on the substrate, and at least one strained transitional layer within the graded portion of the relaxed buffer layer and method of manufacturing the same.

Abstract: A non-volatile memory device including a variable resistance material is provided. The non-volatile memory device may include a buffer layer, a variable resistance material layer and/or an upper electrode, for example, sequentially formed on a lower electrode. A schottky barrier may be formed on an interface between the buffer layer and the lower electrode. The variable resistance material layer may be formed with a variable resistance property.

Abstract: The invention provides a semiconductor device having a pn diode that includes a p-type SiGe layer and a n-type Si layer junctioned to the p-type SiGe layer. A built-in potential of the pn diode can be reduced, and thus obtaining a diode characteristics with lower impedance compared to the conventional scheme. Further, by forming a bridge-rectifier circuit with the pn diode or the like, alternating-current voltages can efficiently be converted into direct-current voltages. Accordingly, the invention provides a semiconductor device and method of manufacturing the same that can flow a larger electrical current in the forward direction of a diode by improving the voltage-current characteristics of the diode.

Abstract: A compound semiconductor wafer providing an InGaAs light receiving layer having superior crystal characteristic suitable for a near-infrared sensor includes an InAsxP1-x graded buffer layer consisting of a plurality of layers positioned on an InP substrate and an InAsyP1-y buffer layer positioned on the graded buffer layer, sandwiched between said InP substrate and the InGaAs layer, wherein maximum value of PL light emission intensity at an interface of each of the layers of the graded buffer layer and the buffer layer is, at every interface, smaller than 3/10 of the maximum PL light emission intensity of the buffer layer.

Abstract: A phase change memory cell is disclosed, including a first electrode and a second electrode, and a plurality of recording layers disposed between the first and second electrodes. The phase of an active region of each of the recording layers can be changed to a crystalline state or an amorphous state by current pulse control and hence respectively has crystalline resistance or amorphous resistance. At least two of the recording layers have different dimensions such that different combinations of the crystalline and amorphous resistance result in at least three different effective resistance values between the first and second electrodes. The phase change memory cell can be realized with the same material of the recording layers and thus can be fabricated with simple and currently developed CMOS fabrication process technologies. Furthermore, the phase change memory is easy to control due to large current programming intervals.

Abstract: Memory elements including a first electrode and a second electrode. A chalcogenide material layer is between the first and second electrodes and a tin-chalcogenide layer is between the chalcogenide material layer and the second electrode. A selenide layer is between the tin-chalcogenide layer and the chalcogenide material layer. Optionally, a metal layer, for example a silver layer, is between the tin-chalcogenide layer and the second electrode. Methods for forming the memory elements are also provided.

Abstract: A phase change memory cell includes an interlayer insulating layer formed on a semiconductor substrate, and a first electrode and a second electrode disposed in the interlayer insulating layer. A phase change material layer is disposed between the first and second electrodes. The phase change material layer may be an undoped GeBiTe layer, a doped GeBiTe layer containing an impurity or a doped GeTe layer containing an impurity. The undoped GeBiTe layer has a composition ratio within a range surrounded by four points (A1(Ge21.43, Bi16.67, Te61.9), A2(Ge44.51, Bi0.35, Te55.14), A3(Ge59.33, Bi0.5, Te40.17) and A4(Ge38.71, Bi16.13, Te45.16)) represented by coordinates on a triangular composition diagram having vertices of germanium (Ge), bismuth (Bi) and tellurium (Te).

Abstract: One exemplary embodiment includes a semiconductor device. The semiconductor device comprising a channel including one or more of a metal oxide including zinc-gallium, cadmium-gallium, cadmium-indium.

Abstract: A semiconductor device can include a channel including a first binary oxide and a second binary oxide.

Abstract: Methods and apparatus for providing a resistance variable memory device with agglomeration prevention and thermal stability. According to one embodiment, a resistance variable memory device is provided having at least one tin-chalcogenide layer proximate at least one chalcogenide glass layer. The invention also relates to methods of forming such a memory device.