Abstract: A lithographic material stack including a photo-resist and an organic planarizing layer is combined with an etch process that generates etch residues over a wide region from sidewalls of etched regions. By selecting the etch chemistry that produces deposition of etch residues from the organic planarizing layer over a wide region, the etch residue generated at the sidewalls of the wide trench is deposited over the entire bottom surface of the wide trench. An etch residue portion remains at the bottom surface of the wide trench when the organic planarizing layer is etched through in the first trench region. The etch residue portion is employed in the next step of the etch process to retard the etch rate in the wide trench, thereby producing the same depth for all trenches in the material layer into which the pattern of the lithographic material stack is transferred.

Abstract: A system, method, and apparatus for suppressing cracks in the wafer dicing process. A wafer includes a plurality of die attached to a frame and mounting tape, with the die separated by a plurality of scribe lanes. An existing die seal generally protects the boundary of the die but can still fail to fully protect the die from excessive cracks induced by dicing damage, particularly when dicing through brittle, low-k dielectrics. The system, method, and apparatus includes embedding a crack arrest structure (CAS) between adjacent scribe lanes. Upon a mechanical saw dicing the wafer, the CAS creates a moisture diffusion block, and can absorb or significantly diminish the energy of cracks propagating towards the individual die seals. Furthermore, the system, method, and apparatus can be implemented without the need to increase the width of the scribe lanes.

Abstract: A trigate device having an extended metal gate electrode comprises a semiconductor body having a top surface and opposing sidewalls formed on a substrate, an isolation layer formed on the substrate and around the semiconductor body, wherein a portion of the semiconductor body remains exposed above the isolation layer, and a gate stack formed on the top surface and opposing sidewalls of the semiconductor body, wherein the gate stack extends a depth into the isolation layer, thereby causing a bottom surface of the gate stack to be below a top surface of the isolation layer.

Abstract: The rollable device of the invention comprises a substrate of an insulating material with apertures extending from a first to a second side. On the first side switching elements are present, as well as interconnect lines and the like, covered by a coating of organic material. On the second side a functional layer is present. Examples of such functional layers include capacitors, antennas and particularly electro-optical layers. Thus, with a rollable display that may include an antenna and a driver circuit is obtained.

Abstract: A semiconductor device in which damages to an element such as a transistor are reduced even when external force such as bending is applied and stress is generated in the semiconductor device. The semiconductor device includes a first island-like reinforcement film over a substrate having flexibility; a semiconductor film including a channel formation region and an impurity region over the first island-like reinforcement film; a first conductive film over the channel formation region with a gate insulating film interposed therebetween; a second island-like reinforcement film covering the first conductive film and the gate insulating film.

Abstract: Vertical field effect transistor semiconductor structures and methods for fabrication of the vertical field effect transistor semiconductor structures provide an array of semiconductor pillars. Each vertical portion of each semiconductor pillar in the array of semiconductor pillars has a linewidth greater than a separation distance to an adjacent semiconductor pillar. Alternatively, the array may comprise semiconductor pillars with different linewidths, optionally within the context of the foregoing linewidth and separation distance limitations. A method for fabricating the array of semiconductor pillars uses a minimally photolithographically dimensioned pillar mask layer that is annularly augmented with at least one spacer layer prior to being used as an etch mask.

Abstract: A semiconductor device is described, which includes a substrate, a gate structure, doped regions and lightly doped regions. The substrate has a stepped upper surface, which includes a first surface, a second surface and a third surface. The second surface is lower than the first surface. The third surface connects the first surface and the second surface. The gate structure is disposed on the first surface. The doped regions are configured in the substrate at both sides of the gate structure and under the second surface. The lightly doped regions are configured in the substrate between the gate structure and the doped regions, respectively. Each lightly doped region includes a first part and a second part connecting with each other. The first part is disposed under the second surface, and the second part is disposed under the third surface.

Abstract: A semiconductor structure includes a Si substrate, a supporting layer and a blocking layer formed on the substrate and an epitaxy layer formed on the supporting layer. The supporting layer defines a plurality of grooves therein to receive the blocking layer. The epitaxy layer is grown from the supporting layer. A plurality of slots is defined in the epitaxy layer and over the blocking layer. The epitaxy layer includes an N-type semiconductor layer, a light-emitting layer and a P-type semiconductor layer. A method for manufacturing the semiconductor structure is also disclosed.

Abstract: An electrical contact device comprising a first contact assemblage having multiple contact pads disposed in a row which are allocated to different connection types, and having a second contact assemblage having multiple contact pads disposed in a row in accordance with a predetermined sequence, which are allocated to different connection types and having bonding wire connections that electrically connect at least some of the contact pads of the first contact assemblage to contact pads of the second contact assemblage.

Abstract: Novel etch techniques are provided for shaping silicon features below the photolithographic resolution limits. FinFET devices are defined by recessing oxide and exposing a silicon protrusion to an isotropic etch, at least in the channel region. In one implementation, the protrusion is contoured by a dry isotropic etch having excellent selectivity, using a downstream microwave plasma etch.

Abstract: A semiconductor device which forms a barrier layer formed of a doped polysilicon layer on a buried bit line to prevent the bit line conductive layer from being exposed during the etching process for forming a buried word line, thereby improving characteristics of the device, and a method of manufacturing the same, are provided. The semiconductor device includes a first pillar pattern and a second pillar pattern, including sidewall contacts, and a buried bit line including a bit line conductive layer disposed over a lower part of a trench between the first pillar pattern and the second pillar pattern, and a barrier layer stacked over the bit line conductive layer.

Abstract: A fin for a finFET is described. The fin is a portion of a layer of material, where, another portion of the layer of material resides on a sidewall.

Abstract: Methods for singulating a semiconductor wafer into a plurality of individual dies that contain lateral edges or sidewalls and the semiconductor dies formed from these methods are described. The dies are formed from methods that use a front to back photolithography alignment process to form a photo-resist mask and an anisoptropic wet etch in an HNA and/or a TMAH solution on the backside of the wafer through the photoresist mask to form sloped sidewalls and/or textures. The conditions of the TMAH etching process can be controlled to form any desired combination of rough or smooth sidewalls. Thus, the dies formed have a Si front side with an area larger than the Si backside area and sidewalls or lateral edges that are not perpendicular to the front or back surface of the die. Other embodiments are also described.

Abstract: The present invention relates to a method for the formation of an at least partially relaxed strained material layer, the method comprising the steps of providing a seed substrate; patterning the seed substrate; growing a strained material layer on the patterned seed substrate; transferring the strained material layer from the patterned seed substrate to an intermediate substrate; and at least partially relaxing the strained material layer by a heat treatment.

Abstract: A method far farming different active thicknesses on the same silicon layer includes masking the silicon layer and exposing selected regions of the silicon layer. The thickness of the silicon layer at the exposed regions is changed, either by adding silicon or subtracting silicon from the layer at the exposed regions. Once the mask is removed, the silicon layer has regions of different active thicknesses, respectively suitable for use in different types of devices, such as diodes and transistors.

Abstract: A method for manufacturing a nitride semiconductor laser element having a nitride semiconductor layer including at least an active layer provided on a substrate, a pair of cavity planes formed on the nitride semiconductor layer, and a protruding part where part of the substrate protrudes from said cavity plane, said method comprises: a step of forming the nitride semiconductor layer on the substrate; a first etching step of forming a first groove by etching at least the nitride semiconductor layer; and a second etching step of forming the cavity plane, in the second etching step, the inner wall of the first groove and part of the nitride semiconductor layer surface adjacent to the first groove are etched to form a second groove, and form the upper face of the protruding part.

Abstract: A semiconductor structure may include, but is not limited to: a semiconductor substrate; a first semiconductor structure extending upwardly over the semiconductor substrate; and a second semiconductor structure extending upwardly over the semiconductor substrate, the first and second semiconductor structures being aligned in a first <100> direction.

Abstract: A microminiature moving device has disposed on a single-crystal silicon substrate movable elements such as a movable rod and a movable comb electrode that are displaceable in parallel to the substrate surface and stationary parts that are fixedly secured to the single-crystal silicon substrate with an insulating layer sandwiched between. Depressions are formed in the surface regions of the single-crystal silicon substrate where no stationary parts are present and the movable parts are positioned above the depressions. The depressions form gaps large enough to prevent foreign bodies from causing shorts and malfunctioning of the movable parts.

Abstract: A semiconductor device has a semiconductor substrate, a semiconductor fin which is formed on the semiconductor substrate, which has a long side direction and a short side direction, and which has a carbon-containing silicon film including an impurity and a silicon film formed on the carbon-containing silicon film, a gate electrode which is formed to face both side surfaces of the semiconductor fin in the short side direction, source and drain regions which are respectively formed in the semiconductor fin located in the direction of both sides in the long side direction of the semiconductor fin so as to sandwich the gate electrode, and an element isolation insulating film which is formed on the side surface of the semiconductor fin and between the gate electrode and the semiconductor substrate.

Abstract: A semiconductor light-emitting device includes: a support; a semiconductor light-emitting element bonded to the support and comprising a first electrode, a second electrode, and a semiconductor layer including at least an active layer, at least one of the first and second electrodes overlying the semiconductor layer; and a wiring metal formed to extend from above a portion of an upper surface of the support not underlying the semiconductor light-emitting element to one said electrode overlying the semiconductor layer. The electrode is fed with power through the wiring metal.

Abstract: A transistor structure and a method of forming same. The transistor structure includes: a semiconductor substrate having a gate-side surface; a gate disposed on the gate-side surface, the gate extending above the gate-side surface by a first height; a semiconductor extension disposed on the gate-side surface and extending above the gate-side surface by a second height larger than the first height, the semiconductor extension including a diffusion region having a diffusion surface located at the second height; and a diffusion contact element electrically coupled to the diffusion surface.

Abstract: An optical semiconductor device includes: an optical semiconductor element including a light-emitting layer formed on a first principal surface, a first electrode formed on the light-emitting layer and having a smaller size than the first principal surface, and a second electrode formed on a second principal surface different from the first principal surface; a first lead portion including a bonding region to which the first electrode is bonded and which has a smaller size than the first principal surface, and a first groove portion formed on an outer peripheral region adjacent to the bonding region, the first lead portion being electrically connected to the first electrode bonded to the bonding region by use of a bonding member; and a second lead portion electrically connected to the second electrode by use of a connecting member.

Abstract: A semiconductor light-emitting device with a new layer structure is disclosed, where the current leaking path is not caused to enhance the current injection efficiency within the active layer. The device provides a mesa structure containing active layer and a p-type lower cladding layer on a p-type substrate and a burying layer doped with iron (Fe) to bury the mesa structure, where the burying layer shows a semi-insulating characteristic. The device also provides an n-type blocking layer arranged so as to cover at least a portion of the p-type buffer lower within the mesa structure. The n-type blocking layer prevents the current leaking from the burying layer to the p-type buffer layer, and the semi-insulating burying layer that covers the rest portion of the mesa structure not covered by the n-type blocking layer prevents the current leaking from the n-type blocking layer to the n-type cladding layer within the mesa structure.

Abstract: Provided is a semiconductor wafer with a scribe line region and a plurality of element forming regions partitioned by the scribe line region, the semiconductor wafer including: conductive patterns formed in the scribe line region; and an island-shaped passivation film formed above at least a conductive pattern, which is or may be exposed to a side surface of a semiconductor chip obtained by dicing the semiconductor wafer along the scribe line region, among the conductive patterns, so that the island-shaped passivation film is opposed to the conductive pattern.

Abstract: A vertical transistor of a semiconductor device and a method for forming the same are disclosed. The vertical transistor comprises a silicon fin disposed on a semiconductor substrate, a source region disposed in the semiconductor substrate below a lower portion of the silicon fin, a drain region disposed in an upper portion of the silicon fin, a channel region disposed in a sidewall of the silicon fin between the source region and the drain region, a gate oxide film disposed in a surface of the semiconductor substrate and the sidewall of the silicon fin, and a pair of gate electrodes disposed on the gate oxide films.

Abstract: A vertical semiconductor device with improved junction profile and a method of manufacturing the same are provided. The vertical semiconductor device includes a pillar vertically extended from a surface of a semiconductor substrate, a silicon layer formed in a bit line contact region of one sidewall of the pillar, and a junction region formed within a portion of the pillar contacting with the silicon layer.

Abstract: The present invention provides methods for forming at least partially relaxed strained material layers on a target substrate. The methods include forming islands of the strained material layer on an intermediate substrate, at least partially relaxing the strained material islands by a first heat treatment, and transferring the at least partially relaxed strained material islands to the target substrate. The at least partial relaxation is facilitated by the presence of low-viscosity or compliant layers adjacent to the strained material layer. The invention also provides semiconductor structures having an at least partially relaxed strained material layer, and semiconductor devices fabricated using an at least partially relaxed strained material layer.

Abstract: A method of forming an isolated tri-gate semiconductor body comprises patterning a bulk substrate to form a fin structure, depositing an insulating material around the fin structure, recessing the insulating material to expose a portion of the fin structure that will be used for the tri-gate semiconductor body, depositing a nitride cap over the exposed portion of the fin structure to protect the exposed portion of the fin structure, and carrying out a thermal oxidation process to oxidize an unprotected portion of the fin structure below the nitride cap. The oxidized portion of the fin isolates the semiconductor body that is being protected by the nitride cap. The nitride cap may then be removed. The thermal oxidation process may comprise annealing the substrate at a temperature between around 900° C. and around 1100° C. for a time duration between around 0.5 hours and around 3 hours.

Abstract: A single crystal silicon etching method includes providing a single crystal silicon substrate having at least one trench therein. The substrate is exposed to a buffered fluoride etch solution which undercuts the silicon to provide lateral shelves when patterned in the <100> direction. The resulting structure includes an undercut feature when patterned in the <100> direction.

Abstract: A nanometric device comprising a substrate; a plurality of conductive spacers of a conductive material, each conductive spacer being arranged on top of and transverse to the substrate, the conductive spacers including respective pairs of conductive spacers defining respective hosting seats each of less than 30 nm wide; and a plurality of nanometric elements respectively accommodated in the hosting seats.

Abstract: A light receiving element 1 has a semiconductor substrate 101; a first mesa 11 provided over the semiconductor substrate 101, and having an active region and a first electrode (p-side electrode 111) provided over the active region; a second mesa 12 provided over the semiconductor substrate 101, and having a semiconductor layer and a second electrode (n-side electrode 121) provided over the semiconductor layer; and a third mesa 13 provided over the semiconductor substrate 101, and having a semiconductor layer, wherein the third mesa 13 is arranged so as to surround the first mesa 11.

Abstract: A method for fabrication of features for an integrated circuit includes patterning a mandrel layer to include structures having at least one width on a surface of an integrated circuit device. Exposed sidewalls of the structures are reacted to integrally form a new compound in the sidewalls such that the new compound extends into the exposed sidewalls by a controlled amount to form pillars. One or more layers below the pillars are etched using the pillars as an etch mask to form features for an integrated circuit device.

Abstract: It is an object of the present invention to provide a nitride semiconductor device with low parasitic resistance by lowering barrier height to reduce contact resistance at an interface of semiconductor and metal. The nitride semiconductor device includes a GaN layer, a device isolation layer, an ohmic electrode, an n-type Al0.25Ga0.75N layer, a sapphire substrate, and a buffer layer. A main surface of the n-type Al0.25Ga0.75N layer is on (0 0 0 1) plane as a main surface, and concaves are arranged in a checkerboard pattern on the surface. The ohmic electrode contacts the sides of the concaves of the n-type Al0.25Ga0.75N layer, and the sides of the concaves are on non-polar surfaces such as (1 1 ?2 0) plane or (1 ?1 0 0) plane.

Abstract: Embodiments relate to a flash memory device and a method of manufacturing a flash memory device, which may increase a coupling coefficient between a control gate and a floating gate by increasing a surface area of floating gate. In embodiments, a flash memory device may be formed by forming a photoresist pattern for forming a floating gate on a semiconductor substrate including an oxide film, a floating gate poly film, and a BARC (Bottom AntiReflect Coating), performing a first etching process using the photoresist pattern as a mask, to etch the floating gate poly film to a predetermined depth, depositing and forming a polymer to cover the photoresist pattern, forming spacers of the polymer at both sidewalls of the photoresist pattern, forming a second etching process using the spacers as a mask, to expose the oxide film, and removing the BARC, the photoresist pattern and the spacers by ashing and stripping.

Abstract: A semiconductor wafer with rear side identification and to a method for producing the same is disclosed. In one embodiment, the rear side identification has a multiplicity of information regarding the monocrystalline and surface and also rear side constitution. A multiplicity of semiconductor device positions arranged in rows and columns are provided on the top side of the semiconductor wafer, an information chip being arranged at an exposed semiconductor device position, the information chip having at least the information of the rear side identification.

Abstract: A method for fabricating a liquid crystal display (LCD) device comprises forming an active pattern and a data line on a substrate, the active pattern including a source, a drain, and a channel regions; a first insulation film on a portion of the substrate; forming a gate electrode in a portion of the active pattern where the first insulation film is formed; a second insulation film on the substrate; forming a plurality of first contact holes exposing a portion of the source and drain regions and a second contact hole exposing a portion of the data line; forming a source electrode from a transparent conductive material connected to a source region within the respective first contact hole and a data line within the second contact hole; and forming a pixel and a drain electrodes from the transparent conductive material connected to a drain region within the respective first contact hole.

Abstract: Improved methods and articles providing conformal coatings for a variety of devices including electronic, semiconductor, and liquid crystal display devices. Peptide formulations which bind to nanoparticles and substrates, including substrates with trenches and vias, to provide conformal coverage as a seed layer. The seed layer can be further enhanced with use of metallic films deposited on the seed layer. Seed layers can be characterized by AFM measurements and improved seed layers provide for better enhancement layers including lower resistivity in the enhancement layer. Peptides can be identified by phage display.

Abstract: A method of forming a virtually defect free lattice mismatched nanoheteroepitaxial layer is disclosed. The method includes forming an interface layer on a portion of a substrate. A plurality of seed pads are then formed by self-directed touchdown by exposing the interface layer to a material comprising a semiconductor material. The plurality of seed pads, having an average width of about 1 nm to 10 nm, are interspersed within the interface layer and contact the substrate. An epitaxial layer is then formed by lateral growth of the seed pads over the interface layer.

Abstract: Some embodiments relate to an apparatus that exhibits vertical diode activity to occur between a semiconductive body and an epitaxial film that is disposed over a doping region of the semiconductive body. Some embodiments include an apparatus that causes both vertical and lateral diode activity. Some embodiments include a gated vertical diode for a finned semiconductor apparatus. Process embodiments include the formation of vertical-diode apparatus.

Abstract: The present invention generally provides semiconductor substrates having submicron-sized surface features generated by irradiating the surface with ultra short laser pulses. In one aspect, a method of processing a semiconductor substrate is disclosed that includes placing at least a portion of a surface of the substrate in contact with a fluid, and exposing that surface portion to one or more femtosecond pulses so as to modify the topography of that portion. The modification can include, e.g., generating a plurality of submicron-sized spikes in an upper layer of the surface.

Abstract: Embodiments relate to a method for fabricating a transistor by using a SOI wafer. A gate insulation layer and a first gate conductive layer on a silicon-on-insulator substrate of a substrate to form a first gate conductive pattern, a gate insulation layer pattern, and a silicon layer pattern. A device isolation insulation layer exposing the top surface of the first gate conductive layer pattern may be formed. A second gate conductive layer may be formed. A mask pattern may be formed. Then, a gate may be formed by etching. After forming a source and drain conductive layer on the silicon layer pattern, the mask pattern may be removed. A salicide layer may be selectively contacting the gate and the source and drain conductive layer may be formed.

Abstract: In this junction element 1, when a forward voltage is applied, a depletion layer is formed in a semiconductor layer 2, prohibiting electrons present in an electrode layer 4 to move into the semiconductor layer 2. For this reason, a majority of holes in a semiconductor layer 3 do not disappear by recombination with conduction electrons in the semiconductor layer 2, but reach the electrode layer 4 while diffusing into the semiconductor layer 2. Accordingly, the junction element 1 can serve as a good conductor for holes, while avoiding the influence of a resistance value, and allows a current to flow therethrough at a level equal to or more than that achieved by a semiconductor element formed of a Si or SiC semiconductor.

Abstract: A production method for an electronic chip component includes the steps of forming a first paste layer by applying paste onto a first end surface of an electronic component body with a second end surface being stuck onto a substrate having an adhesive surface and drying the paste, turning the electronic component body 180 degrees so as to stick the first end surface of the electronic component body onto the substrate by sliding a slider relative to the substrate in a state in which the slider is in contact with the first end surface of the electronic component body, forming a second paste layer by applying the paste onto the second end surface of the electronic component body and drying the paste, and firing the first and second paste layers.

Abstract: A semiconductor structure and a system for fabricating an integrated circuit chip. The semiconductor structure includes: a buried oxide layer on a semiconductor wafer; a thin fin structure on the buried oxide layer, wherein the thin fin structure includes a first hard mask on a semiconductor fin, wherein the semiconductor fin is disposed between the first hard mask and a surface of the buried oxide layer; and a thick mesa structure on the buried oxide layer, and wherein the thick mesa structure includes a semiconductor mesa. The system for fabricating an integrated circuit chip enables: providing a buried oxide layer on and in direct mechanical contact with a semiconductor wafer; and concurrently forming at least one fin-type field effect transistor and at least one thick-body device on the buried oxide layer.

Abstract: A PIN diode comprising an N-type substrate comprising a cathode of the PIN diode and having an intrinsic layer disposed upon the N-type substrate and having a top surface a P-type material disposed upon the top surface of the intrinsic layer comprising an anode of the PIN diode and a N-type material disposed over the sidewall of the cathode and over the sidewall and a portion of the top surface of the intrinsic material that is not occupied by the anode, wherein a horizontal gap is defined between the anode and the cathode through the intrinsic material, the gap being variable in width and/or the horizontal gap is less than the thickness of the intrinsic layer.

Abstract: A method of fabricating a semiconductor device includes forming a fin-shaped active region including opposing sidewalls and a surface therebetween protruding from a substrate, forming a gate structure on the surface of the active region, and performing an ion implantation process to form source/drain regions in the active region at opposite sides of the gate structure. The source/drain regions respectively include a first impurity region in the surface of the active region and second impurity regions in the opposing sidewalls of the active region. The first impurity region has a doping concentration that is greater than that of the second impurity regions. Related devices are also discussed.

Abstract: In one aspect, the present invention teaches a multiple-gate transistor 130 that includes a semiconductor fin 134 formed in a portion of a bulk semiconductor substrate 132. A gate dielectric 144 overlies a portion of the semiconductor fin 134 and a gate electrode 146 overlies the gate dielectric 144. A source region 138 and a drain region 140 are formed in the semiconductor fin 134 oppositely adjacent the gate electrode 144. In the preferred embodiment, the bottom surface 150 of the gate electrode 146 is lower than either the source-substrate junction 154 or the drain-substrate junction 152.

Abstract: A semiconductor wafer and a method for cutting the same are provided, which enable separation of the semiconductor wafer by natural cleavage planes. The cutting method includes preparing a substrate including a semiconductor layer with at least one projection, formed on a predetermined area thereof; forming a post on an upper surface of the semiconductor layer at one or both sides of the projection to be placed on a cleaving line for cutting of the semiconductor layer; and cutting the substrate including the semiconductor layer along the cleaving line by performing a scribing process in a direction from the substrate and a breaking process in a direction from the semiconductor layer.

Abstract: A semiconductor substrate (1) includes a plurality of semiconductor elements (2) in which functional elements are constructed and which is formed in a grid pattern, wherein continuous linear grooves (3) are formed on longitudinal and lateral separating lines (4) that individually separate the plurality of semiconductor elements (2) with the exception of intersections of the separating lines (4) and portions corresponding to corners of each semiconductor element (2).

Abstract: An integrated circuit semiconductor device includes a substrate, a deep via within the substrate which is provided with a dielectric cladding in contact with the substrate, metal fill located within the deep via and defining an upper surface, interconnect wiring, and a dielectric layer located above the deep via and a void between the upper surface of the metal fill and the dielectric layer. The interconnect wiring layer contacts the metal fill laterally.