Abstract: A semiconductor device includes a semiconductor body comprising a first surface and an edge surface, a contact electrode formed on the first surface and comprising an outer edge side, and a passivation layer section conformally covering the outer edge side of the contact electrode. The passivation layer section is a multi-layer stack comprising a first layer, a second layer, and a third layer. Each of the first, second and third layers include outer edge sides facing the edge surface and opposite facing inner edge sides. The outer edge side of the contact electrode is disposed laterally between the inner edge sides and the outer edge sides of each layer.

Abstract: A semiconductor device includes a semiconductor substrate having a first main surface and a metal structure above the first main surface. The metal structure has a periphery region that includes a transition section along which the metal structure transitions from a first thickness to a second thickness less than the first thickness. A polymer-based insulating material contacts and covers at least the periphery region of the metal structure. A thickness of the polymer-based insulating material begins to increase on a first main surface of the metal structure that faces away from the semiconductor substrate and continues to increase in a direction towards the transition section. An average slope of a surface of the polymer-based insulating material which faces away from the semiconductor substrate, as measured with respect to the first main surface of the metal structure, is less than 60 degrees along the periphery region of the metal structure.

Abstract: A method is presented for back-end-of-the-line (BEOL) metallization with lines formed by subtractive patterning and vias formed by damascene processes. The method includes depositing a dielectric layer over a conductive layer formed over a substrate, forming spacers surrounding mandrel sections formed over the dielectric layer, selectively depositing gap fill material adjacent the spacers, selectively removing the spacers, etching the dielectric layer and the conductive layer to expose a top surface of the substrate, depositing and planarizing an interlayer dielectric, selectively forming openings in the dielectric layer, and filling the openings with a conductive material to define metal vias.

Abstract: A compound semiconductor device includes a semiconductor multilayer structure including an electron transit layer and an electron supply layer of a compound semiconductor; a source electrode, a gate electrode, and a drain electrode that are disposed above the semiconductor multilayer structure and are aligned in a first direction; a first insulating film that is formed on the semiconductor multilayer structure between the gate electrode and the drain electrode, and has a tensile stress; a second insulating film that is formed on the semiconductor multilayer structure between the gate electrode and the source electrode, and has a compressive stress; and a protective film that is formed between the first insulating film and the semiconductor multilayer structure, and between the second insulating film and the semiconductor multilayer structure.

Abstract: A semiconductor device includes a semiconductor body and a first portion including silicon and nitrogen. The first portion is in direct contact with the semiconductor body. A second portion including silicon and nitrogen is in direct contact with the first portion. The first portion is between the semiconductor body and the second portion. An average silicon content in the first portion is higher than in the second portion.

Abstract: Some embodiments include an integrated assembly having a paired-memory-cell-region within a memory-array-region. The paired-memory-cell-region includes a bitline-contact-structure between a first charge-storage-device-contact-structure and a second charge-storage-device-contact-structure. A first insulative region is between the bitline-contact-structure and the first charge-storage-device-contact-structure. A second insulative region is between the bitline-contact-structure and the second charge-storage-device-contact-structure. The first and second insulative regions both include a first semiconductor material which is in a nonconductive configuration. A transistor gate is over a peripheral region proximate the memory-array-region. The transistor gate has a second semiconductor material which is a same semiconductor composition and thickness as the first semiconductor material, but which is in a conductive configuration. Some embodiments include methods of forming integrated assemblies.

Abstract: A semiconductor device includes a semiconductor element, a wiring portion, an electrode pad, a sealing resin and a heat dissipation layer. The semiconductor element has a front surface and a back surface opposite to the front surface in a thickness direction of the semiconductor device. The wiring portion is electrically connected to the semiconductor element. The electrode pad is electrically connected to the wiring portion. The sealing resin covers the semiconductor element. The heat dissipation layer is held in contact with the back surface of the semiconductor element and exposed from the sealing resin. The semiconductor element overlaps with the first heat dissipation layer as viewed in the thickness direction.

Abstract: One illustrative integrated circuit product disclosed herein comprises first and second spaced-apart P-active regions positioned on a buried insulation layer positioned on a base substrate, at least one first PFET transistor in the first P-active region, and a plurality of second PFET transistors in the second P-active region, wherein the first P-active region has a first length (in the gate length direction of the device) and the second P-active region has a second length that is greater than the first length and wherein the number of second PFET transistors is greater than the number of first PFET transistors. In this example, the product also includes a tensile-stressed layer of material positioned on the at least one first PFET transistor and above the first P-active region and a compressive-stressed layer of material positioned on the plurality of second PFET transistors and above the second P-active region.

Abstract: Methods for reducing warpage of bowed semiconductor substrates, particularly saddle-shaped bowed semiconductor substrates, are provided herein. Methods involve depositing a bow compensation layer by plasma enhanced chemical vapor deposition on the backside of the bowed semiconductor substrate by region, such as by quadrants, to form a compressive film on a tensile substrate and a tensile film on a compressive substrate. Methods involve flowing different gases from different nozzles on a surface of a showerhead to deliver various gases by region in a one-step operation or flowing gases in a multi-step process by shielding regions of the showerhead during delivery of gases to deliver specific gases from non-shielded regions onto regions of the bowed semiconductor substrate by alternating between rotating the semiconductor substrate and flowing gases to the backside of the bowed semiconductor substrate.

Abstract: A semiconductor device includes a semiconductor element including a bipolar transistor disposed on a compound semiconductor substrate, a collector electrode, a base electrode, and an emitter electrode, the bipolar transistor including a collector layer, a base layer, and an emitter layer, the collector electrode being in contact with the collector layer, the base electrode being in contact with the base layer, the emitter electrode being in contact with the emitter layer; a protective layer disposed on one surface of the semiconductor element; an emitter redistribution layer electrically connected to the emitter electrode via a contact hole in the protective layer; and a stress-relieving layer disposed between the emitter redistribution layer and the emitter layer in a direction perpendicular to a surface of the compound semiconductor substrate.

Abstract: The present invention provides a method for improving the quality of a high-voltage metal oxide semiconductor (HV MOS), the method includes: firstly, a substrate is provided, next, a hard mask layer is formed on the substrate, an oxygen plasma treatment is then performed to the hard mask layer, so as to form an oxide layer on the hard mask layer. Afterwards, a patterned photoresist layer is formed on the oxide layer, and a first cleaning process is performed to a top surface of the oxide layer after the patterned photoresist layer is formed, wherein the first cleaning process comprises rinsing the oxide layer with carbonated water. Next, a first etching process is performed to remove parts of the hard mask layer, and the patterned photoresist layer is then removed. Afterwards, a second etching process is performed, to remove the oxide layer.

Abstract: A semiconductor device includes a substrate including a cell region and a peripheral region, a cell gate electrode buried in a groove crossing a cell active portion of the cell region, a cell line pattern crossing over the cell gate electrode, the cell line pattern being connected to a first source/drain region in the cell active portion at a side of the cell gate electrode, a peripheral gate pattern crossing over a peripheral active portion of the peripheral region, a planarized interlayer insulating layer on the substrate around the peripheral gate pattern, and a capping insulating layer on the planarized interlayer insulating layer and a top surface of the peripheral gate pattern, the capping insulating layer including an insulating material having an etch selectivity with respect to the planarized interlayer insulating layer.

Abstract: A method of forming a capacitor mask includes the following steps. A bulk mandrel and a plurality of strip mandrels are formed on a mask layer. Spacers are formed on sidewalls of the bulk mandrel and the strip mandrels. The strip mandrels are removed while the bulk mandrel is reserved. A material fills in space between the spacers and on the bulk mandrel, wherein the material has a flat top surface. A patterned photoresist is formed to cover the bulk mandrel and a part of the spacers but exposing the other part of the spacers after filling the material.

Abstract: Integrated active-matrix multi-color light emitting pixel arrays based displays and methods of fabricating the integrated displays are provided. An example integrated device includes a backplane device and different color light emitting diodes (LEDs) devices arranged in different height planar layers on the backplane device. The backplane device includes at least one backplane having a number of pixel circuits. Each LED device includes an array of LEDs each operable to emit light with a particular color and conductively coupled to respective pixel circuits in the backplane to form active-matrix LED sub-pixels. The different color LED sub-pixels form an array of active-matrix multi-color display pixels. Plug vias can be arranged in different planar layers to conductively couple upper-level LEDs to respective pixel circuits in respective regions over the backplane device. The plug vias can extend from an upper planar layer into a lower planar layer to fix the two planar layers together.

Abstract: A semiconductor device according to an embodiment includes a first nitride semiconductor layer; a second nitride semiconductor layer on the first nitride semiconductor layer; a first electrode and a second electrode disposed on or above the first nitride semiconductor layer; a gate electrode above the first nitride semiconductor layer; and a gate insulating layer, the gate insulating layer including a silicon oxide film and an aluminum oxynitride film, the aluminum oxynitride film disposed between the first nitride semiconductor layer and the silicon oxide film, a first atomic ratio of nitrogen relative to a sum of oxygen and nitrogen at a first position in the aluminum oxynitride film being higher than a second atomic ratio of nitrogen relative to a sum of oxygen and nitrogen at a second position in the aluminum oxynitride film, and the second position being closer to the silicon oxide film than the first position.

Abstract: A trench structure includes a top metal layer, a silicon carbide (SiC) layer on the top metal layer, a first passivation layer overlying the SiC layer, and a second passivation layer overlying the first passivation layer. The trench structure also includes a first sidewall and a second sidewall that, together with the top metal layer, form a trench. At least one of the first sidewall or the second sidewall includes a sidewall of the second passivation layer and a sidewall of the SiC layer.

Abstract: A method for fabricating a semiconductor device includes: forming a silicon nitride film having a refractive index equal to or larger than 2.2 on a nitride semiconductor layer; and introducing at least one of elements that are oxygen, nitrogen, fluorine, phosphorus, sulfur and selenium into the silicon nitride film, the silicon nitride film including the at least one of elements remaining on the nitride semiconductor layer. The at least one of elements is introduced by a process of exposing the silicon nitride film to plasma including the at least one of elements, a process of ion-implanting the at least one of elements into the silicon nitride film, or a process of thermally diffusing the at least one of elements into the silicon nitride film. The silicon nitride film is formed in contact with a surface of the nitride semiconductor layer.

Abstract: A process for forming a T-gate with enhanced mechanical strength and a reduced gate length for high electron mobility transistors is provided. The process includes the steps of forming a stem portion cavity with rounded top edges to enhance the mechanical strength, creating an insoluble diffused feature shrinking layer to reduce the gate length, carrying out a thermal flow process to further reduce the gate length, and forming a head portion cavity with negative side wall slopes to facilitate lift-off of gate metal layers.

Abstract: A semiconductor device includes: a compound semiconductor stack structure including a plurality of compound semiconductor layers stacked over a semiconductor substrate; and a first insulating film covering the surface of the compound semiconductor stack structure, the first insulating film being a silicon nitride film including, on the top side, a first region containing nitrogen element in excess of the stoichiometric ratio.

Abstract: A method for manufacturing a sensor device is provided. The method prevents corrosion of metal electrodes of a sensor due to outside air with high humidity and preventing the occurrence of warpage of the sensor due to resin sealing of the sensor, thereby reducing the influence on sensor characteristics, and provides the sensor device. The method includes arranging a sensor on a substrate, the sensor having a fixed part, a movable part positioned inside the fixed part, a flexible part connecting the fixed part and the movable part, and a plurality of metal electrodes, electrically connecting the plurality of metal electrodes of the sensor and a plurality of terminals of the substrate with bonding wires, and covering portions of the plurality of metal electrodes of the sensor connected to the bonding wires with a resin so that a part of the bonding wires between the plurality of metal electrodes and the plurality of terminals is exposed.

Abstract: An organic light emitting device comprises a first substrate; a thin film transistor layer provided on the first substrate; a light emitting diode layer provided on the thin film transistor layer; and a passivation layer provided on the light emitting diode layer, the passivation layer including a first inorganic insulating film and a second inorganic insulating film, wherein a content of H contained in the first inorganic insulating film is smaller than that of H contained in the second inorganic insulating film.

Abstract: Techniques are disclosed for enhancing the dielectric breakdown performance of integrated circuit (IC) interconnects. The disclosed techniques can be used to selectively etch the dielectric layer of an IC to form a recess, for example, between a given pair of adjacent/neighboring interconnects (e.g., metal lines). Thereafter, a layer of dielectric material of higher dielectric breakdown field (Ec) than the surrounding/underlying dielectric material (or other suitable insulator, as will be apparent in light of this disclosure) may be deposited/grown so as to substantially conform to the topology provided by the adjacent/neighboring interconnects and etched recess. In some cases, this dielectric layer may help to prevent or otherwise reduce: (1) dielectric breakdown between the adjacent/neighboring interconnects by locally increasing the dielectric breakdown voltage (VBD); and/or (2) diffusion of the interconnect fill metal into the surrounding/underlying dielectric material.

Abstract: Multilayer dielectric structures are provided having silicon nitride (SiN) and silicon oxynitride (SiNO) films for use as capping layers, liners, spacer barrier layers, and etch stop layers, and other components of semiconductor nano-devices. For example, a semiconductor structure includes a multilayer dielectric structure having multiple layers of dielectric material including one or more SiN layers and one or more SiNO layers. The layers of dielectric material in the multilayer dielectric structure have a thickness in a range of about 0.5 nanometers to about 3 nanometers.

Abstract: Various semiconductor devices are disclosed. An exemplary device includes: a substrate; a gate structure disposed over the substrate, wherein the gate structure includes a source region and a drain region; a first etch stop layer disposed over the gate structure, a second etch stop layer disposed over the source region and the drain region; a dielectric layer disposed over the substrate; and a gate contact, a source contact, and a drain contact. The dielectric layer is disposed over both etch stop layers. The gate contact extends through the dielectric layer and the first etch stop layer to the gate structure. The source contact and the drain contact extend through the dielectric layer and the second etch stop layer respectively to the source region and the drain region.

Abstract: Methods for producing air gap-containing metal-insulator interconnect structures for VLSI and ULSI devices using a photo-patternable low k material as well as the air gap-containing interconnect structure that is formed are disclosed. More particularly, the methods described herein provide interconnect structures built in a photo-patternable low k material in which air gaps are defined by photolithography in the photo-patternable low k material. In the methods of the present invention, no etch step is required to form the air gaps. Since no etch step is required in forming the air gaps within the photo-patternable low k material, the methods disclosed in this invention provide highly reliable interconnect structures.

Abstract: A method for semiconductor self-aligned patterning includes steps of providing a substrate comprising a first layer and a second layer, wherein the first layer is on top of the second layer; removing a portion of the first layer to form a first pattern; depositing a first conformal layer on the first pattern; depositing a second conformal layer on the first conformal layer; removing a portion of the second conformal layer to expose a portion of the first conformal layer; and thinning the first conformal layer and the second conformal layer alternatively to form a second pattern. A semiconductor self-aligned structure is also provided.

Abstract: A transistor includes a semiconductor substrate, at least a gate structure, at least a first tensile stress layer, a second tensile stress layer, a source region, and a drain region. The gate structure is disposed within a first transistor region of the semiconductor substrate. The first tensile stress layer includes a curved portion encompassing the gate structure, at least an extension portion with a curved top surface located on the semiconductor substrate at sides of the gate structure, and a transition portion between the curved portion and the extension portion. The first tensile stress layer has a thickness gradually thinning from the curved portion and the extension portion toward the transition portion. The second tensile stress layer is disposed on the first tensile stress layer. And the source/drain regions are separately located in the semiconductor substrate on two sides of the gate structure.

Abstract: The surface recombination velocity of a silicon sample is reduced by deposition of a thin hydrogenated amorphous silicon or hydrogenated amorphous silicon carbide film, followed by deposition of a thin hydrogenated silicon nitride film. The surface recombination velocity is further decreased by a subsequent anneal. Silicon solar cell structures using this new method for efficient reduction of the surface recombination velocity is claimed.

Abstract: A method for manufacturing a semiconductor device includes forming a contact etch stop layer on an active area of a substrate that has a gate stack formed thereon. The gate stack includes a metal gate and a metal oxide. The contact etch stop layer includes a silicon oxide layer sandwiched between a first silicon nitride layer and a second silicon nitride layer that is disposed on the active area. The method further includes forming a contact hole extending through an interlayer dielectric layer on the first silicon nitride layer using the first silicon nitride layer as a protection for the active area, removing a portion of the first silicon nitride layer disposed at the bottom of the contact hole using the silicon oxide layer as a protection for the active area, and removing the metal oxide using the second silicon nitride layer as a protection for the active area.

Abstract: A small contact hole having a large aspect ratio is formed by employing a stop layer with a trench formed therein. A relatively large contact hole is formed above the trench, and the small contact hole is formed below the trench, using properties of the trench and the stop layer to limit the size of the small contact hole.

Abstract: A semiconductor structure includes a substrate, a conductive feature over the substrate, a conductive plug structure contacting a portion of an upper surface of the conductive feature, a first etch stop layer over another portion of the upper surface of the conductive feature, and a second etch stop layer over the first etch stop layer. The first etch stop layer is a doped etch stop layer. The first etch stop layer is to function as an etch stop layer during a predetermined etching process for etching the second etch stop layer.

Abstract: An SOI substrate having an SOI layer that can be used in practical applications even when a substrate with low upper temperature limit, such as a glass substrate, is used, is provided. A semiconductor device using such an SOI substrate, is provided. In bonding a single-crystal semiconductor layer to a substrate having an insulating surface or an insulating substrate, a silicon oxide film formed using organic silane as a material on one or both surfaces that are to form a bond is used. According to the present invention, a substrate with an upper temperature limit of 700° C. or lower, such as a glass substrate, can be used, and an SOI layer that is strongly bonded to the substrate can be obtained. In other words, a single-crystal semiconductor layer can be formed over a large-area substrate that is longer than one meter on each side.

Abstract: A dummy wafer structure and a method of forming the same are disclosed. The dummy wafer structure includes: a silicon substrate; a silicon nitride layer over the silicon substrate; and a silicon dioxide layer over the silicon nitride layer. The method includes: a first step of forming a silicon nitride layer over a silicon substrate so as to form a silicon-silicon nitride structure; and a second step of forming a silicon dioxide layer over the silicon-silicon nitride structure obtained in the first step so as to form a silicon-silicon nitride-silicon dioxide structure. Dummy wafers with this special structure are able to avoid deposition rate inconsistency in a polysilicon deposition process and are capable of avoiding conventional dummy wafers' adverse effect on deposit layer thicknesses of process wafers and hence providing the process wafers with deposit layers having a high inter-wafer uniformity.

Abstract: A semiconductor device includes a main body having a single crystalline semiconductor body. A layered structure directly adjoins a central portion of a main surface of the main body and includes a hard dielectric layer provided from a first dielectric material with Young's modulus greater than 10 GPa. A stress relief layer directly adjoins the layered structure opposite to the main body and extends beyond an outer edge of the layered structure. Providing the layered structure at a distance to the edge of the main body and covering the outer surface of the layered structures with the stress relief layer enhances device reliability.

Abstract: A capacitor and method for fabricating the same. In one configuration, the capacitor has a silicon substrate, a first and a second silicon dioxide layer over the silicon substrate, and silicon nitride fins between the silicon dioxide layers. The capacitor further includes a dielectric layer over the silicon nitride fins and metal vias in the dielectric layer.

Abstract: The present invention relates to a process for the production of solar cells comprising a selective emitter using an improved etching-paste composition which has significantly improved selectivity for silicon layers.

Abstract: Methods of forming a semiconductor device are provided. The methods include, for example, forming a low-k dielectric having a continuous planar surface, and, after forming the low-k dielectric, subjecting the continuous planar surface of the low-k dielectric to an ethylene plasma enhanced chemical vapor deposition (PECVD) treatment.

Abstract: Provided is a trench filling method, which includes: forming a silicon oxide liner on a semiconductor substrate with trenches formed therein, the trenches including narrow-width portions having a first minimum isolation width and wide-width portions having a second minimum isolation width being wider than the first minimum isolation width; forming an oxidation-barrier film on the silicon oxide liner; forming a silicon liner on the oxidation-barrier film; filling the narrow-width portions with a first filling material; filling the wide-width portions with a second filling material; and oxidizing the silicon liner.

Abstract: A dummy wafer structure and a method of forming the same are disclosed. The dummy wafer structure includes: a silicon substrate; a silicon nitride layer over the silicon substrate; and a silicon dioxide layer over the silicon nitride layer. The method includes: a first step of forming a silicon nitride layer over a silicon substrate so as to form a silicon-silicon nitride structure; and a second step of forming a silicon dioxide layer over the silicon-silicon nitride structure obtained in the first step so as to form a silicon-silicon nitride-silicon dioxide structure. Dummy wafers with this special structure are able to avoid deposition rate inconsistency in a polysilicon deposition process and are capable of avoiding conventional dummy wafers' adverse effect on deposit layer thicknesses of process wafers and hence providing the process wafers with deposit layers having a high inter-wafer uniformity.

Abstract: An integrated circuit includes a substrate. A surface region of the substrate includes a contact pad region. A passivation layer stack includes at least one passivation layer. The passivation layer stack is formed over the surface region and adjacent to the contact pad region. An upper portion of the passivation layer stack is removed in, in a portion of the passivation layer stack proximate the contact pad region.

Abstract: The disclosure relates to integrated circuit fabrication, and more particularly to a method for fabricating a semiconductor device. An exemplary method for fabricating the semiconductor device comprises providing a substrate; forming pad oxide layers over a frontside and a backside of the substrate; forming hardmask layers over the pad oxide layers on the frontside and the backside of the substrate; and thinning the hardmask layer over the pad oxide layer on the frontside of the substrate.

Abstract: Various semiconductor devices are disclosed. An exemplary device includes: a substrate; a gate structure disposed over the substrate, wherein the gate structure includes a source region and a drain region; a first etch stop layer disposed over the gate structure, a second etch stop layer disposed over the source region and the drain region; a dielectric layer disposed over the substrate; and a gate contact, a source contact, and a drain contact. The dielectric layer is disposed over both etch stop layers. The gate contact extends through the dielectric layer and the first etch stop layer to the gate structure. The source contact and the drain contact extend through the dielectric layer and the second etch stop layer respectively to the source region and the drain region.

Abstract: In one aspect of the present invention, a method of sawing a semiconductor wafer will be described. A semiconductor wafer is positioned in a wafer sawing apparatus that includes a sawing blade and a movable support structure that physically supports the semiconductor wafer. The semiconductor wafer is coupled with the support structure with various layers, including a die attach film, an adhesive and a base film. The die attach film is cut with the sawing blade. During the cutting operation, a contact portion of the sawing blade engages one of the layers and moves at least partly in one direction. While the contact portion of the sawing blade engages the layer, the support structure moves in the opposite direction. Various aspects of the present invention relate to arrangements and a wafer sawing apparatus that involve the aforementioned sawing method.

Abstract: A method of forming an integrated circuit includes providing a buffer layer comprising a dielectric material above a layer of conductive material and providing a layer of mask material above the buffer layer. The mask material comprises amorphous carbon. The method also includes removing a portion of the buffer layer and the layer of mask material to form a mask. A feature is formed in the layer of conductive material according to the mask.

Abstract: A first example embodiment provides a method of removing first spacers from gates and incorporating a low-k material into the ILD layer to increase device performance. A second example embodiment comprises replacing the first spacers after silicidation with low-k spacers. This serves to reduce the parasitic capacitances. Also, by implementing the low-k spacers only after silicidation, the embodiments' low-k spacers are not compromised by multiple high dose ion implantations and resist strip steps. The example embodiments can improve device performance, such as the performance of a rim oscillator.

Abstract: Non-volatile memory devices, and fabricating methods thereof, include a floating gate over a substrate, a lower barrier layer including a first lower barrier layer on the upper surface of the floating gate, and a second lower barrier layer on a side surface of the floating gate to have a thickness smaller than a thickness of the first lower barrier layer, an inter-gate dielectric layer over the lower barrier layer, and a control gate over the inter-gate dielectric layer.

Abstract: A shallow trench isolation is formed in a semiconductor substrate adjacent a MOS transistor. The shallow trench is filled with a fill material while other processing steps are performed. The fill material is later removed through a thin well etched into layers above the trench, leaving the trench hollow. A thin strain inducing layer is then formed on the sidewall of the hollow trench. The well is then plugged, leaving the trench substantially hollow except for the thin strain inducing layer on the sidewall of the trench. The strain inducing layer is configured to induce compressive or tensile strain on a channel region of the MOS transistor and thereby to enhance conduction properties of the transistor.

Abstract: Methods for fabricating integrated circuits having substrate contacts and integrated circuits having substrate contacts are provided. One method includes forming a first trench in a SOI substrate extending through a buried insulating layer to a silicon substrate. A metal silicide region is formed in the silicon substrate exposed by the first trench. A first stress-inducing layer is formed overlying the metal silicide region. A second stress-inducing layer is formed overlying the first stress-inducing layer. An ILD layer of dielectric material is formed overlying the second stress-inducing layer. A second trench is formed extending through the ILD layer and the first and second stress-inducing layers to the metal silicide region. The second trench is filled with a conductive material.

Abstract: A method for fabricating a semiconductor device, comprising: forming n-channel field-effect transistors on a silicon substrate; forming a first insulating film covering the field-effect transistors; shrinking the first insulating film; forming a second insulating film over the first insulating film; and shrinking the second insulating film, wherein the forming an insulating film covering the field-effect transistors and the shrinking the insulating film are repeated a plurality of time.

Abstract: A method of creating insulating layers on different semiconductor materials includes providing a substrate having disposed thereon a first material and a second material, the second material having a chemical composition different from the first material; non-epitaxially depositing a continuous sacrificial layer of approximately constant thickness onto the first material and the second material, and then converting the sacrificial layer into a layer consisting essentially of SiO2 without oxidizing more than 10 angstroms into the second material. A structure includes a silicon nitride film disposed conformally on a silicon layer and a silicon germanium layer; a SiO2 layer is disposed on the silicon nitride film.