Abstract: According to one embodiment of the disclosure, a method for passivating a circuit device generally includes providing a substrate having a substrate surface, forming an electrical component on the substrate surface, and coating the substrate surface and the electrical component with a first protective dielectric layer. The first protective dielectric layer is made of a generally moisture insoluble material having a moisture permeability less than 0.01 gram/meter2/day, a moisture absorption less than 0.04 percent, a dielectric constant less than 10, a dielectric loss less than 0.005, a breakdown voltage strength greater than 8 million volts/centimeter, a sheet resistivity greater than 1015 ohm-centimeter, and a defect density less than 0.5/centimeter2.

Abstract: An ultra-violet (UV) protection layer is formed over a semiconductor workpiece before depositing a UV curable dielectric layer. The UV protection layer prevents UV light from reaching and damaging underlying material layers and electrical devices. The UV protection layer comprises a layer of silicon doped with an impurity, wherein the impurity comprises O, C, H, N, or combinations thereof. The UV protection layer may comprise SiOC:H, SiON, SiN, SiCO:H, combinations thereof, or multiple layers thereof, as examples.

Abstract: Provided are a semiconductor device and a method for manufacturing the semiconductor device. The semiconductor device includes: a gate electrode formed of polysilicon on a substrate with a gate insulating layer interposed between the gate electrode and the substrate; a source region and a drain region formed on the substrate on either side of the gate electrode; a PMD (poly-metal dielectric) liner nitride layer having a non-stoichiometric structure formed on the gate electrode, the source region, and the drain region; and an interlayer insulating layer formed on the PMD liner nitride layer.

Abstract: There has been a problem that difference in refractive index between an opposite substrate or a moisture barrier layer (passivation film) such as SiN provided thereover, and air is maintained large, and light extraction efficiency is low. Further, there has been a problem that peeling or cracking due to the moisture barrier layer is easily generated, which leads to deteriorate the reliability and lifetime of a light-emitting element. According to the present invention, a light-emitting element comprises a pixel electrode, an electroluminescent layer, a transparent electrode, a passivation film, a stress relieving layer, and a low refractive index layer, all of which are stacked sequentially. The stress relieving layer serves to prevent peeling of the passivation film. The low refractive index layer serves to reduce reflectivity of light generated in the electroluminescent layer in emitting to air.

Abstract: A first silicon oxide film is formed on the surface of the semiconductor substrate in an area of a vertical transfer channel and a read gate contiguous with each other, and a silicon nitride film is formed on the first silicon oxide film. The silicon nitride film is isotropically etched by using a resist pattern formed on the silicon nitride film as a mask. A second silicon oxide film is formed on the surface of the etched silicon nitride film to form an insulating film containing silicon oxide films and a silicon nitride film. A photoelectric conversion element contiguous with the read gate on the opposite side of the vertical transfer channel is formed. The isotropical etching makes the silicon nitride film cover the vertical transfer channel, extend over the read gate, and have a tapered sidewall. A high quality solid state image pickup device can be manufactured.

Abstract: A semiconductor structure including an nFET having a fully silicided gate electrode wherein a new dual stress liner configuration is used to enhance the stress in the channel region that lies beneath the gate electrode is provided. The new dual stress liner configuration includes a first stress liner that has an upper surface that is substantially planar with an upper surface of a fully silicided gate electrode of the nFET. In accordance with the present invention, the first stress liner is not present atop the nFET including the fully silicided gate electrode. Instead, the first stress liner of the present invention partially wraps around, i.e., surrounds the sides of, the nFET with the fully silicided gate electrode. A second stress liner having an opposite polarity as that of the first stress liner (i.e., of an opposite stress type) is located on the upper surface of the first stress liner as well as atop the nFET that contains the fully silicided FET.

Abstract: Interconnects with harmonized stress and methods for fabricating the same. An interconnect comprises a substrate having a conductive member. A composite low-k dielectric layer interposed with at least one stress-harmonizing layer therein overlies the substrate. A conductive feature in the composite low-k dielectric layer passes through the at least one stress-harmonizing layer to electrically connect the conductive member.

Abstract: A system and method for improved dry etching system. According to an embodiment, the present invention provides a partially completed integrated circuit device. The partially completed integrated circuit device includes a semiconductor substrate having a surface region. The partially completed integrated circuit device also includes an etch stop layer overlying the surface region. The etch stop layer is characterized by a thickness having at least a first thickness portion and a second thickness portion. The second thickness portion includes an etch stop surface region. The partially completed integrated circuit device additionally includes a silicon dioxide material provided within the first thickness portion of the etch stop layer. The partially completed integrated circuit device includes a silicon nitride material provided within the second thickness portion of the etch stop layer.

Abstract: A method of forming a crystalline phase material includes: providing stress inducing material within or operatively adjacent a material of a first crystalline phase; and annealing under conditions effective to transform the material to a second crystalline phase. The stress inducing material preferably induces compressive stress during the anneal to lower the activation energy to produce a more dense second crystalline phase. Example compressive stress inducing materials are SiO2, Si3N4, Ge, W and Co. Where the compressive stress inducing material is provided on the same side of a wafer as the crystalline phase material, it is provided to have a thermal coefficient of expansion which is less than that of the first phase crystalline material. Where the compressive stress inducing material is provided on the opposite side of a wafer, it is provided to have a thermal coefficient of expansion which is greater than that of the first phase crystalline material.

Abstract: A structure and a method of making the structure. The structure includes a field effect transistor including: a first and a second source/drain formed in a silicon substrate, the first and second source/drains spaced apart and separated by a channel region in the substrate; a gate dielectric on a top surface of the substrate over the channel region; and an electrically conductive gate on a top surface of the gate dielectric; and a dielectric pillar of a first dielectric material over the gate; and a dielectric layer of a second dielectric material over the first and second source/drains, sidewalls of the dielectric pillar in direct physical contact with the dielectric layer, the dielectric pillar having no internal stress or an internal stress different from an internal stress of the dielectric layer.

Abstract: A method of forming a thin-film layered electronic device over a flexible substrate comprises the steps of depositing a buffer layer over the flexible substrate, heating the substrate and buffer layer stack to a temperature at which plastic deformation of the buffer layer takes place, cooling the stack, then forming the thin-film electronic device over the plastically deformed buffer layer without further plastic deformation of the buffer layer. The heating and cooling to cause plastic deformation of the buffer layer is referred to as annealing. The thin-film electronic device is formed by a process according to which all steps are performed at a temperature below that at which further plastic deformation of the buffer layer occurs. In-process strain and runout are reduced, improving device yield on flexible substrates. An optional metal base layer may be formed over the buffer layer prior annealing.

Abstract: An isolation layer of a semiconductor device and a process for forming the same is described herein. The isolation layer includes a trench that is defined and formed in a semiconductor substrate. A first liner nitride layer is formed on the surface of the trench and a flowable insulation layer is formed in the trench including the first liner nitride layer. The flowable insulation layer is formed such to define a recess in the trench. A second liner nitride layer is formed on the recess including the flowable insulation layer and the first liner nitride layer. Finally, an insulation layer is formed in the recess on the second liner nitride layer to completely fill the trench.

Abstract: A memory cell in a semiconductor memory device has a pair of charge traps formed on opposite sides of a control electrode, above variable resistance regions in the semiconductor substrate. Each charge trap includes a tunnel oxide film, a dual-layer charge trapping film, and a top oxide film. The dual-layer charge trapping film includes a silicon-rich silicon nitride layer or amorphous silicon layer adjacent to the tunnel oxide film, and a stoichiometric or nitrogen-rich silicon nitride layer adjacent to the top oxide film. Most charges injected into the charge trapping film are trapped in the layer adjacent to the tunnel oxide film, near the substrate, which facilitates the reading of the data that the trapped charges represent.

Abstract: The present invention relates to complementary metal-oxide-semiconductor (CMOS) devices having gapped dual stressors with dielectric gap fillers. Specifically, each CMOS device of the present invention includes at least one n-channel field effect transistor (n-FET) and at least one p-channel field effect transistor (p-FET). A tensilely stressed dielectric layer overlays the n-FET, and a compressively stressed dielectric layer overlays the p-FET. A gap is located between the tensilely and compressively stressed dielectric layers and is filled with a dielectric filler material. In one specific embodiment of the present invention, both the tensilely and compressively stressed dielectric layers are covered by a layer of the dielectric filler material, which is essentially free of stress. In an alternatively embodiment of the present invention, the dielectric filler material is only present in the gap between the tensilely and compressively stressed dielectric layers.

Abstract: A method of fabricating a semiconductor-on-insulator semiconductor wafer is described that includes providing first and second semiconductor substrates. A first insulating layer is formed on the first substrate with a first predetermined stress and a second insulating layer is formed on the second substrate with a second predetermined stress different than the first predetermined stress. The first insulating layer is bonded to the second insulating layer to form a composite insulating layer bonding the first substrate to the second substrate and a portion of the one substrate is removed to form a thin crystalline active layer on the composite insulating layer. The first and second insulating layers are formed with different stresses to provide a desired composite stress, which can be any stress from compressive to unstressed to tensile, depending upon the desired application.

Abstract: The present invention provides a method for fabricating a flexible pixel array substrate as follows. First, a release layer is formed on a rigid substrate. Next, on the release layer, a polymer film is formed, the adhesive strength between the rigid substrate and the release layer being higher than that between the release layer and the polymer film. The polymer film is formed by spin coating a polymer monomer and performing a curing process to form a polymer layer. Afterwards, a pixel array is formed on the polymer film. The polymer film with the pixel array formed thereon is separated from the rigid substrate.

Abstract: The present invention provides an SOS wafer comprising a non-transparent polysilicon layer provided on a back surface of a sapphire substrate, a silicon nitride layer which protects the polysilicon layer, and a stress relaxing film which cancels stress produced in the silicon nitride layer, wherein the silicon nitride layer and the stress relaxing film are provided on the back surface side.

Abstract: A semiconductor device including a compound semiconductor laminated structure having a plurality of compound semiconductor layers formed over a semiconductor substrate, a first insulation film covering at least a part of a surface of the compound semiconductor laminated structure, and a second insulation film formed on the first insulation film, wherein the second insulation film includes more hydrogen than the first insulation film.

Abstract: A highly stressed dielectric material, such as a tensile stressed material, may be deposited in a conformal manner so as to respect any deposition constraints caused by pronounced surface topography of highly scaled semiconductor devices, followed by the deposition of a buffer material having enhanced gap-filling capabilities. Thereafter, a further stress-inducing layer is deposited to form a doublet structure, which acts on the transistor elements, thereby enhancing overall performance, without increasing the probability of creating deposition-related irregularities. Hence, production yield as well as performance of highly scaled semiconductor devices may be increased.

Abstract: Methods of forming dual-damascene metal wiring patterns include forming a first metal wiring pattern (e.g., copper wiring pattern) on an integrated circuit substrate and forming an etch-stop layer on the first metal wiring pattern. These steps are followed by the steps of forming an electrically insulating layer on the etch-stop layer and forming an inter-metal dielectric layer on the electrically insulating layer. The inter-metal dielectric layer and the electrically insulating layer are selectively etched in sequence to define an opening therein that exposes a first portion of the etch-stop layer. This opening may include a trench and a via hole extending downward from a bottom of the trench. A first barrier metal layer is formed on a sidewall of the opening and directly on the first portion of the etch-stop layer. A portion of the first barrier metal layer is selectively removed from the first portion of the etch-stop layer.

Abstract: Embodiments of a silicon-on-insulator (SOI) wafer having an etch stop layer overlying the buried oxide layer, as well as embodiments of a method of making the same, are disclosed. The etch stop layer may comprise silicon nitride, nitrogen-doped silicon dioxide, or silicon oxynitride, as well as some combination of these materials. Other embodiments are described and claimed.

Abstract: Disclosed is a semiconductor structure and associated method of performing the structure with good performance and stability trade-offs for digital circuits and SRAM cells and/or analog FETs on the same chip. Specifically, a dual-strain layer is formed over digital circuits and the other devices on a chip. The dual-strain layer comprises tensile sections above digital logic n-type transistors, compressive sections above digital logic p-type transistors and additional tensile sections above SRAM cells and/or analog FETs. An amorphization ion-implant is performed to relax the strain over SRAM cell p-FETs and, thereby, eliminate variability and avoid p-FET performance degradation in the SRAM cells. Additionally, this ion-implant can relax the strain above both analog p-FETs and n-FETs and, thereby, eliminate variability and the coupling of the logic device process to the analog FETs and provide more predictable and well-controlled analog FETs.

Abstract: A nitride semiconductor light-emitting device including a first n-type nitride semiconductor layer, a light-emitting layer, a p-type nitride semiconductor layer, and a second n-type nitride semiconductor layer in this order, and further including an electrode formed of a transparent conductive film on the second n-type nitride semiconductor layer is provided. The nitride semiconductor light-emitting device has improved light extraction efficiency. The electrode formed of a transparent conductive film is preferably formed on a part of a surface of the second n-type nitride semiconductor layer.

Abstract: The surface recombination velocity of a silicon sample is reduced by deposition of a thin hydrogenated amorphous silicon or hydrogenated amorphous silicon carbide film, followed by deposition of a thin hydrogenated silicon nitride film. The surface recombination velocity is further decreased by a subsequent anneal. Silicon solar cell structures using this new method for efficient reduction of the surface recombination velocity is claimed.

Abstract: A semiconductor device and a method for fabricating the same. The semiconductor device includes a gate pattern formed on a semiconductor substrate, a first impurity-doped region formed in the substrate on one side of the gate pattern and a second impurity-doped region formed in the substrate on the other side of the gate pattern, a salicide shielding film pattern partially covering either the first impurity-doped region or the second impurity-doped region, an insulating film formed on the semiconductor substrate, the insulating film including a first hole which exposes the salicide shielding film pattern, and a second hole which partially exposes the first impurity-doped region or the second impurity-doped region that is not covered by the salicide shielding film pattern, and a first line coming in contact with the salicide shielding film pattern through the first hole.

Abstract: The present invention provides a semiconductor device having dual nitride liners, a silicide layer, and a protective layer beneath one of the nitride liners for preventing the etching of the silicide layer. A first aspect of the invention provides a semiconductor device comprising a protective layer adjacent a first device, a first silicon nitride liner over the protective layer, a second silicon nitride liner adjacent a second device, and a first silicide layer adjacent the first device and a second silicide layer adjacent the second device, wherein a thickness is substantially the same in the first and second silicide layers.

Abstract: A method for manufacturing a semiconductor laser. As a preparative step for coating an end face of a resonator with a dielectric film, a cleavage plane of a semiconductor laminated structure that is to be the end face is subjected to a plasma cleaning to prevent a conductive film, which absorbs laser light, from attaching to the cleavage plane. During the plasma cleaning, a first process gas containing argon gas and nitrogen gas is introduced into a vacuumed ECR sputtering apparatus. After the cleavage plane is exposed to the first process gas in the plasma state for a certain time period without application of a voltage, a second process gas containing argon gas and oxygen gas is introduced, and the cleavage plane is exposed to the second process gas in the plasma state while a voltage is applied to the silicon target.

Abstract: A barrier film formed on top of a substrate, a barrier film formed so as to cover a functional element region fabricated on top of a substrate, or a barrier film formed on both a substrate and a functional element region, wherein the barrier film includes at least one layer of a silicon nitride film formed by laminating two or more silicon nitride layers having different Si/N composition ratios.

Abstract: A protective insulation film covering a surface of a compound semiconductor region is formed to have a two-layer structure of a first insulation film and a second insulation film which have different properties. The first insulation film is a non-stoichiometric silicon nitride film while the second insulation film is a silicon nitride film in an almost stoichiometric state.

Abstract: A mechanically robust semiconductor structure with improved adhesion strength between a low-k dielectric layer and a dielectric-containing substrate is provided. In particular, the present invention provides a structure that includes a dielectric-containing substrate having an upper region including a treated surface layer which is chemically and physically different from the substrate; and a low-k dielectric material located on a the treated surface layer of the substrate. The treated surface layer and the low-k dielectric material form an interface that has an adhesion strength that is greater than 60% of the cohesive strength of the weaker material on either side of the interface. The treated surface is formed by treating the surface of the substrate with at least one of actinic radiation, a plasma and e-beam radiation prior to forming of the substrate the low-k dielectric material.

Abstract: The present invention provides a semiconducting device including a gate dielectric atop a semiconducting substrate, the semiconducting substrate containing source and drain regions adjacent the gate dielectric; a gate conductor atop the gate dielectric; a conformal dielectric passivation stack positioned on at least the gate conductor sidewalls, the conformal dielectric passivation stack comprising a plurality of conformal dielectric layers, wherein no electrical path extends entirely through the stack; and a contact to the source and drain regions, wherein the discontinuous seam through the conformal dielectric passivation stack substantially eliminates shorting between the contact and the gate conductor. The present invention also provides a method for forming the above-described semiconducting device.

Abstract: Embodiments relate to a Metal-Oxide Semiconductor Field Effect Transistor (MOSFET) and a method of fabricating a MOSFET. According to embodiments, a method of forming a MOSFET may include forming a first gate insulating layer on a semiconductor substrate, nitrifying the first gate insulating layer, forming a second gate insulating layer on the first gate insulating layer, injecting fluorine ions into the second gate insulating layer, and diffusing the fluorine ions into the first gate insulating layer.

Abstract: A system and method for improved dry etching system. According to an embodiment, the present invention provides a partially completed integrated circuit device. The partially completed integrated circuit device includes a semiconductor substrate having a surface region. The partially completed integrated circuit device also includes an etch stop layer overlying the surface region. The etch stop layer is characterized by a thickness having at least a first thickness portion and a second thickness portion. The second thickness portion includes an etch stop surface region. The partially completed integrated circuit device additionally includes a silicon dioxide material provided within the first thickness portion of the etch stop layer. The partially completed integrated circuit device includes a silicon nitride material provided within the second thickness portion of the etch stop layer.

Abstract: The invention proposes am improved twin MONOS memory device and its fabrication. The ONO layer is self-aligned to the control gate horizontally. The vertical insulator between the control gate and the word gate does not include a nitride layer. This prevents the problem of electron trapping. The device can be fabricated to pull the electrons out through either the top or the bottom oxide layer of the ONO insulator. The device also incorporates a raised memory bit diffusion between the control gates to reduce bit resistance. The twin MONOS memory array can be embedded into a standard CMOS circuit by the process of the present invention.

Abstract: Disclosed is a semiconductor device comprising a semiconductor substrate, a gate electrode, a first insulating film formed between the semiconductor substrate and the gate electrode, and a second insulating film formed along a top surface or a side surface of the gate electrode and including a lower silicon nitride film containing nitrogen, silicon and hydrogen and an upper silicon nitride film formed on the lower silicon nitride film and containing nitrogen, silicon and hydrogen, and wherein a composition ratio N/Si of nitrogen (N) to silicon (Si) in the lower silicon nitride film is higher than that in the upper silicon nitride film.

Abstract: A method, apparatus and system are provided for relieving stress in the via structures of semiconductor structures whenever a linewidth below a via is larger than a ground-rule, including providing a via at least as large as the groundrule, providing a landing pad above the via, providing a via bar in place of a via, slotting the metal linewidth below the via, or providing an oversize via with a sidewall spacer.

Abstract: Disclosed is a method for fabricating a MOS transistor. The present method includes forming a buffer layer pattern including nitrogen on the semiconductor substrate; forming a gate insulating layer and a gate electrode on the exposed substrate surface; forming a LDD region in the substrate under the buffer pattern; forming a spacer on a top surface of the buffer pattern and sidewalls of the gate electrode; and forming a source/drain region in the substrate under the buffer pattern.

Abstract: By forming isolation trenches of different types of intrinsic stress on the basis of separate process sequences, the strain characteristics of adjacent active semiconductor regions may be adjusted so as to obtain overall device performance. For example, highly stressed dielectric fill material including compressive and tensile stress may be appropriately provided in the respective isolation trenches in order to correspondingly adapt the charge carrier mobility of respective channel regions.

Abstract: A method of manufacturing a mechanically robust insulating layer, including forming a low-k dielectric layer having a first dielectric constant on a substrate and forming a carbon nitride cap layer on the low-k dielectric layer, the insulating layer thereby having a second dielectric constant that is less than the first dielectric constant.

Abstract: A display device is provided in which contact holes, each having a sidewall with an ideal tapered shape, are formed in a structure in which a silicon oxide film, a silicon nitride film and a silicon oxide film are stacked in the named order. The display device includes a first silicon oxide film, a silicon nitride film stacked on the first silicon oxide film, a second silicon oxide film stacked on the silicon nitride film, and a contact hole which extends through at least these three layers. In the display device, letting d2 and d3 denote, respectively, a film thickness of the silicon nitride film and a film thickness of the second silicon oxide film, these films are stacked to satisfy the relationship d2<d3, and the contact hole is formed to have a tapered shape free of constrictions.

Abstract: The present invention provides a semiconductor device having a multilayer wiring structure including a lower Cu buried-wiring layer, a SiC film, a SiOC film of 400 nm in thickness functioning as an interlayer insulating film, and an upper Cu buried-wiring layer electrically connected to the lower buried-wiring layer through contact plugs passing through the interlayer insulating film. The contact plugs and the upper Cu buried wiring layer are formed a single burying step of the dual damascene process. The SiOC film has a carbon content of about 12 atomic % and a relative dielectric constant of about 3.0. The upper Cu buried wiring layer is formed by burying a Cu film, through a barrier metal, in wiring grooves which are provided in the inter-wiring insulating film including a laminated film of an organic film, e.g., a PAE film of 200 nm in thickness, and a SiOC film of 150 nm in thickness.

Abstract: A method of depositing dielectric material into sub-micron spaces and resultant structures is provided. After a trench is etched in the surface of a wafer, a liner layer preferably is deposited into the trench. An anisotropic plasma process is then performed on the trench. A silicon layer may be deposited on the base of the trench during the plasma process, or the plasma can treat the liner layer. The trench is then filled with a spin-on precursor. A densification or reaction process is then applied to convert the spin-on material into an insulator, and oxidizing the silicon rich layer on the base of the trench. The resulting trench has a consistent etch rate from top to bottom of the trench.

Abstract: A semiconductor device having a nonconductive cap layer comprising a first metal element. The nonconductive cap layer comprises a first metal nitride, a first metal oxide, or a first metal oxynitride over conductive lines and an insulating material between the conductive lines. An interface region may be formed over the top surface of the conductive lines, the interface region including the metal element of the cap layer. The cap layer prevents the conductive material in the conductive lines from migrating or diffusing into adjacent subsequently formed insulating material layers. The cap layer may also function as an etch stop layer.

Abstract: The present invention provides a semiconductor device having a multilayer wiring structure including a lower Cu buried-wiring layer, a SiC film, a SiOC film of 400 nm in thickness functioning as an interlayer insulating film, and an upper Cu buried-wiring layer electrically connected to the lower buried-wiring layer through contact plugs passing through the interlayer insulating film. The contact plugs and the upper Cu buried wiring layer are formed a single burying step of the dual damascene process. The SiOC film has a carbon content of about 12 atomic % and a relative dielectric constant of about 3.0. The upper Cu buried wiring layer is formed by burying a Cu film, through a barrier metal, in wiring grooves which are provided in the inter-wiring insulating film including a laminated film of an organic film, e.g., a PAE film of 200 nm in thickness, and a SiOC film of 150 nm in thickness.

Abstract: A method of passivating an integrated circuit (IC) is provided. An insulating layer is formed onto the IC. An adhesion layer is formed onto a surface of the insulating layer by treating the surface of the insulating layer with a gas. A first passivation layer is formed upon the adhesion layer, the first passivation layer and the gas including at least one common chemical element.

Abstract: A method for manufacturing a semiconductor laser. As a preparative step for coating an end face of a resonator with a dielectric film, a cleavage plane of a semiconductor laminated structure that is to be the end face is subjected to a plasma cleaning to prevent a conductive film, which absorbs laser light, from attaching to the cleavage plane. During the plasma cleaning, a first process gas containing argon gas and nitrogen gas is introduced into a vacuumed ECR sputtering apparatus. After the cleavage plane is exposed to the first process gas in the plasma state for a certain time period without application of a voltage, a second process gas containing argon gas and oxygen gas is introduced, and the cleavage plane is exposed to the second process gas in the plasma state while a voltage is applied to the silicon target.

Abstract: A CMOS device and manufacturing method thereof wherein a bilayer etch stop is used over a PMOS transistor, and a single etch stop layer is used for an NMOS transistor, for forming contacts to the source or drain of the CMOS device. A surface tension-reducing layer is disposed between the source or drain region of the PMOS transistor and an overlying surface tension-inducing layer. The surface tension-inducing layer may comprise a nitride material or carbon-containing material, and the surface tension-reducing layer may comprise an oxide material. Degradation of hole mobility in the PMOS transistor is prevented by the use of the surface tension-reducing layer of the bilayer etch stop.

Abstract: A method for fabricating a semiconductor device where a critical dimension in a peripheral region is decreased. The method includes the steps of: forming a silicon nitride layer on a substrate including a cell region and a peripheral region; forming a silicon oxynitride layer on the silicon nitride layer; forming a line-type photoresist pattern on the silicon oxynitride layer such that the photoresist pattern in the cell region has a width larger than that of a final pattern structure and the photoresist pattern in the peripheral region has a width that reduces an incidence of pattern collapse; etching the silicon oxynitride layer and the silicon nitride layer until widths of a remaining silicon oxynitride layer and a remaining silicon nitride layer are smaller than the width of the photoresist pattern used as an etch mask through suppressing generation of polymers; and over-etching the remaining silicon nitride layer.

Abstract: An embodiment of the invention is a method of making a semiconductor structure 10 where the spacer oxide layer 90 is formed by a hydrogen free precursor CVD process. Another embodiment of the invention is a semiconductor structure 10 having a spacer oxide layer 90 with a hydrogen content of less than 1%.

Abstract: A semiconductor device has a split-gate type memory transistor, a capacitor element, and another capacitor element formed on the same chip, in which the capacitor values of the capacitor element and the another capacitor element are independently set to different values. A capacitor element 53 has a dielectric film that includes a silicon oxide film 41 (thermal oxide film), a silicon nitride film 43b and a silicon oxide film 57 (thermal oxide film). A capacitor element 55 has a dielectric film that includes a silicon oxide film 25 (thermal oxide film), a silicon oxide film 37 (CVD silicon oxide film), a silicon oxide film 41 (thermal oxide film), a silicon nitride film 43b and a silicon oxide film 57 (thermal oxide film).