Abstract: A new method is provided for the creation of a high-reliability metal capacitor as part of back-end processing. A first layer of metal interconnect is created, ac contact point is provided in the surface of the first layer of interconnect aligned with which a capacitor is to be created. A copper interconnect is formed overlying the contact point using TaN for the bottom plate, a high dielectric-constant dielectric material capacitor and using TaN for the top plate. The deposited layers are patterned and etched, a spacer layer is formed over sidewalls of the capacitor to prevent capacitor sidewall leakage. Top interconnect metal is then formed by first depositing a layer of etch stop material for further interconnection of the capacitor and the semiconductor devices provided in the underlying substrate.

Abstract: A shallow trench isolation (STI) structure and method of forming the same with reduced stress to improve charge mobility the method including providing a semiconductor substrate comprising at least one patterned hardmask layer overlying the semiconductor substrate; dry etching a trench in the semiconductor substrate according to the at least one patterned hardmask layer; forming one or more liner layers to line the trench selected from the group consisting of silicon dioxide, silicon nitride, and silicon oxynitride; forming one or more layers of trench filling material comprising silicon dioxide to backfill the trench; carrying out at least one thermal annealing step to relax accumulated stress in the trench filling material; carrying out at least one of a CMP and dry etch process to remove excess trench filling material above the trench level; and, removing the at least one patterned hardmask layer.

Abstract: A semiconductor device has an n channel conductivity type field effect transistor having a channel formation region formed in a first region on one main surface of a semiconductor substrate and a p channel conductivity type field effect transistor having a channel formation region formed in a second region on the main surface of the semiconductor substrate, which second region is different from the first region. An internal stress generated in the channel formation region of the n channel conductivity type field effect transistor is different from an internal stress generated in the channel formation region of the p channel conductivity type field effect transistor. The internal stress generated in the channel formation region of the n channel conductivity type field effect transistor is a tensile stress, while the internal stress generated in the channel formation region of the p channel conductivity type field effect transistor is a compressive stress.

Abstract: In the fabrication of semiconductor devices using the PECVD process to deposit hardmask material such as amorphous carbon, structure and process are described for reducing migration of species from the amorphous carbon which can damage an overlying photoresist. In one embodiment useful to 248 nm and 193 nm photolithography exposure wavelengths, amorphous carbon is plasma-deposited on a substrate to pre-defined thickness and pre-defined optical properties. A SiON layer is combined with a silicon-rich oxide layer, a silicon-rich nitride layer or a TEOS layer to create a capping layer resistant to species-migration. Layers are formulated to pre-determined thicknesses, refractive indices and extinction coefficients. The capping stacks constitute an effective etch mask for the amorphous carbon; and the hardmask properties of the amorphous carbon are not compromised. The disclosure has immediate application to fabricating polysilicon gates.

Abstract: Methods for making a semiconductor structure are discussed. The methods include forming openings in a high-density area and a high-speed area, and forming a metallization layer simultaneously into the high-density area and the high-speed area. The metallization layer includes a combination of substances and compounds that reduce vertical resistance, reduce horizontal resistance, and inhibit cross-diffusion.

Abstract: A semiconductor integrated circuit device has a semiconductor substrate, an interlayer insulating film including SiOF films formed on a main surface of the semiconductor substrate, a wiring groove formed by dry etching of the interlayer insulating film, and a Cu wiring buried in the wiring groove by a Damascene method, wherein a silicon oxynitride film is provided between a silicon nitride film serving as an etching stopper layer for the dry etching and the SiOF film, so that free F generated in the SiOF film is trapped with the silicon oxynitride film.

Abstract: The present invention relates to an integrated circuit having a sealed nitride layer. In one embodiment, a method of forming a sealing nitride layer overlaying a silicon oxide layer in a contact opening of an integrated circuit is disclosed. The method comprises, forming a second layer of nitride overlaying a first layer of nitride to form the sealing nitride layer. The second layer of nitride further overlays an exposed portion of a surface of a substrate in the contact opening and sidewalls of the contact opening. Using reactive ion etching (RIE etch) without a mask to remove a portion of the second nitride layer adjacent the surface of the substrate in the contact opening to expose a portion of the surface of the substrate in the contact opening without removing portions of the second nitride layer covering the sidewalls of the contact opening.

Abstract: A semiconductor device includes a substrate that further includes source, drain and channel regions. The device may further include a bottom oxide layer formed upon the substrate, a charge storage layer formed upon the bottom oxide layer, and a steam oxide layer thermally grown upon the charge storage layer. The device may also include an alumina oxide layer formed upon the steam oxide layer and a gate electrode formed upon the alumina oxide layer.

Abstract: A method for manufacturing a multi-level interconnection structure in a semiconductor device includes the steps of consecutively forming an anti-diffusion film and an interlevel dielectric film on a first level Cu layer, forming first through third hard mask films on the interlevel dielectric film, etching the interlevel dielectric film by using the first hard mask to form first through-holes, etching the first and second hard mask films and a top portion of the interlevel dielectric film by using the third hard mask film to form trenches, and etching the anti-diffusion film to form through-holes. The first hard mask film protects the interlevel dielectric film during removal of the second and third hard mask films.

Abstract: In one aspect, the invention includes a semiconductor processing method, comprising: a) providing a silicon nitride material having a surface; b) forming a barrier layer over the surface of the material, the barrier layer comprising silicon and nitrogen; and c) forming a photoresist over and against the barrier layer.

Abstract: An object of the present invention is to increase adhesiveness between thin films, particularly a high molecular film formed on an insulating surface, and the present invention provides a semiconductor device with high reliability and a method for manufacturing the semiconductor device with high yield. A semiconductor device of the present invention comprises a laminate structure formed in close contact with an organic insulating film on a hydrophobic surface of an inorganic insulating film including silicon and nitrogen. A film having the hydrophobic surface is an insulating film having a contact angle of water of equal to or more than 30°, preferably of equal to or more than 40°.

Abstract: There are disclosed TFTs having improved reliability. An interlayer dielectric film forming the TFTs is made of a silicon nitride film. Other interlayer dielectric films are also made of silicon nitride. The stresses inside the silicon nitride films forming these interlayer dielectric films are set between ?5×109 and 5×109 dyn/cm2. This can suppress peeling of the interlayer dielectric films and difficulties in forming contact holes. Furthermore, release of hydrogen from the active layer can be suppressed. In this way, highly reliable TFTs can be obtained.

Abstract: A system and method of processing a substrate including loading a substrate into a plasma chamber and setting a pressure of the plasma chamber to a pre-determined pressure set point. Several inner surfaces that define a plasma zone are heated to a processing temperature of greater than about 200 degrees C. A process gas is injected into the plasma zone to form a plasma and the substrate is processed.

Abstract: The present invention provides a semiconductor device, a method of manufacture therefor, and an integrated circuit including the aforementioned semiconductor device. The semiconductor device, in accordance with the principles of the present invention, may include a substrate, and a graded capping layer located over the substrate, wherein the graded capping layer includes at least two different layers, wherein first and second layers of the at least two different layers have different stress values.

Abstract: An insulating tube includes a underlying insulating film, a first sidewall insulating film disposed on the underlying insulating film, a second sidewall insulating film disposed on the underlying insulating film, opposite to the first sidewall insulating film so as to provide a cavity between the first and second sidewall insulating films having the same height as the first sidewall insulating film, and an upper insulating film provided over the first and second sidewall insulating films.

Abstract: According to one embodiment, a memory cell structure comprises a semiconductor substrate, a first silicon oxide layer situated over the semiconductor substrate, a charge storing layer situated over the first silicon oxide layer, a second silicon oxide layer situated over the charge storing layer, and a gate layer situated over the second silicon oxide layer. In the exemplary embodiment, the charge storing layer comprises silicon nitride having reduced hydrogen content, e.g., in the range of about 0 to 0.5 atomic percent. As a result, the reduced hydrogen content reduces the charge loss in the charge storing layer. The reduced charge loss in the charge storing layer has the benefit of reducing threshold voltage shifts, programming data loss, and programming capability loss in the memory device, thereby improving memory device performance.

Abstract: A high k dielectric film and methods for forming the same are disclosed. The high k material includes two peaks of impurity concentration, particularly nitrogen, such as at a lower interface and upper interface, making the layer particularly suitable for transistor gate dielectric applications. The methods of formation include low temperature processes, particularly CVD using a remote plasma generator and atomic layer deposition using selective incorporation of nitrogen in the cyclic process. Advantageously, nitrogen levels are tailored during the deposition process and temperatures are low enough to avoid interdiffusion and allow maintenance of the desired impurity profile.

Abstract: A polysilicon thin film transistor and a method of forming the same is provided. A poly-island layer is formed over a substrate. A gate insulation layer is formed over the poly-island layer. A gate is formed over the gate insulation layer. Using the gate as a mask, an ion implantation of the poly-island layer is carried out to form a source/drain region in the poly-island layer outside the channel region. An oxide layer and a silicon nitride layer, together serving as an inter-layer dielectric layer, are sequentially formed over the substrate. Thickness of the oxide layer is thicker than or the same as (thickness of the nitride layer multiplied by 9000 ?)1/2 and maximum thickness of the nitride layer is smaller than 1000 ?.

Abstract: A thin film transistor with a channel less than 100 angstroms thick, preferably less than 80 angstroms thick, preferably less than 60 angstroms thick. The very thin channel reduces variability of threshold voltage from one TFT to the next. This is particularly advantageous for TFT memory arrays. It is possible that an extremely thin channel restricts the size of grains, forcing many small grains to be formed.

Abstract: The invention includes a semiconductor construction comprising a semiconductor substrate, and a first layer comprising silicon and nitrogen over the substrate. A second layer comprising at least 50 weight% carbon is over and physically against the first layer, and a third layer consisting essentially of a photoresist system is over and physically against the second layer. The invention also includes methodology for forming the semiconductor construction.

Abstract: A low-thermal budget, silicon-rich silicon nitride film may include a concentration of hydrogen in Si—H bonds being at least 1.5 times as great as a concentration of hydrogen in N—H bonds. The silicon nitride film suppresses boron diffusion in boron-doped devices when such devices are processed using high-temperature processing operations that conventionally urge boron diffusion. The low-thermal budget, silicon-rich silicon nitride film may be used to form spacers in CMOS devices, it may be used as part of a dielectric stack to prevent shorting in tightly packed SRAM arrays, and it may be used in BiCMOS processing to form a base nitride layer and/or nitride spacers isolating the base from the emitter. Furthermore the low-thermal budget, silicon-rich silicon nitride film may remain covering the CMOS structure while bipolar devices are being formed, as it suppresses the boron diffusion that results in boron penetration and boron-doped poly depletion.

Abstract: A semiconductor device has a pair of impurity regions in a semiconductor substrate. A silicon layer is formed on the impurity region. A gate insulating film is formed between the impurity regions. A gate electrode is formed on the gate insulating film. A first silicon nitride film is formed on the gate electrode. A silicon oxide film is formed on a side surface of the gate electrode. A second silicon nitride film is partially formed on the silicon layer and on a side surface of the silicon oxide film. A conductive layer is formed on the silicon layer.

Abstract: An ultrathin gate dielectric having a graded dielectric constant and a method for forming the same are provided. The gate dielectric is believed to allow enhanced performance of semiconductor devices including transistors and dual-gate memory cells. A thin nitrogen-containing oxide, preferably having a thickness of less than about 10 angstroms, is formed on a semiconductor substrate. A silicon nitride layer having a thickness of less than about 30 angstroms may be formed over the nitrogen-containing oxide. The oxide and nitride layers are annealed in ammonia and nitrous oxide ambients, and the nitride layer thickness is reduced using a flowing-gas etch process. The resulting two-layer gate dielectric is believed to provide increased capacitance as compared to a silicon dioxide dielectric while maintaining favorable interface properties with the underlying substrate. In an alternative embodiment, a different high dielectric constant material is substituted for the silicon nitride.

Abstract: A semiconductor integrated circuit is disclosed, which includes a semiconductor substrate, a memory cell formed on the semiconductor substrate and having a first gate insulating layer of a stacked structure which includes a silicon nitride layer to become a charge storage layer, and a transistor formed on the semiconductor substrate and having a second gate insulating layer. Here, source and drain diffused layers of the memory cell are covered with a part of the first gate insulating layer, and metal silicide layers are formed on surfaces of source and drain diffused layers of the transistor.

Abstract: An ultra high-speed semiconductor device has a high-K dielectric gate insulator layer, wherein spread of impurities to a Si substrate from a gate electrode through the high-K dielectric gate insulator layer, and spread of oxygen and metallic elements from the high-K dielectric gate insulator layer to the Si substrate or the gate electrode are suppressed by arranging the high-K dielectric film sandwiched by nitrogen atomic layers on the Si substrate that is covered by an oxygen atomic layer.

Abstract: A semiconductor device having memory cells. Each of the memory cells has a word gate formed over a semiconductor substrate with a first gate insulating layer interposed, an impurity layer, and first and second control gates in the shape of sidewalls. The first and second control gates adjacent to each other with the impurity layer interposed are connected to a common contact section. The common contact section includes a first contact conductive layer, a second contact conductive layer, and a pad-shaped third contact conductive layer. The third contact conductive layer is formed over the first and second contact conductive layers.

Abstract: A process for forming a final passivation layer over an integrated circuit comprises a step of forming, over a surface of the integrated circuit, a protective film by means of High-Density Plasma Chemical Vapor Deposition.

Abstract: Methods and apparatus for forming word line stacks comprise forming a thin nitride layer coupled between a bottom silicon layer and a conductor layer. In a further embodiment, a diffusion barrier layer is coupled between the thin nitride layer and the bottom silicon layer. The thin nitride layer is formed by annealing a silicon oxide film in a nitrogen-containing ambient.

Abstract: Methods are provided for forming a transistor for use in an active matrix liquid crystal display (AMLCD). In one aspect a method is provided for processing a substrate including providing a glass substrate, depositing a conductive seed layer on a surface of the glass substrate, depositing a resist material on the conductive seed layer, patterning the resist layer to expose portions of the conductive seed layer, and depositing a metal layer on the exposed portions of the conductive seed layer by an electrochemical technique.

Abstract: A passivation method includes disassociating ammonia so as to expose at least interfaces between silicon-containing and passivation structures to at least hydrogen species derived from the ammonia and forming an encapsulant layer that is positioned so as to substantially contain the hydrogen species in the presence of the interfaces. The hydrogen passivation reduces a concentration of dangling silicon bonds at the interfaces by as much as about two orders of magnitude or greater. The encapsulant layer, which may include silicon nitride, prevents hydrogen species from escaping therethrough as high temperature processes are subsequently conducted. Once high temperature processes have been completed, portions of the encapsulant layer may be removed, as needed, to provide access to features of the semiconductor device structure that underlie the encapsulant layer. Semiconductor device structures that have been passivated in such a manner are also disclosed.

Abstract: An improved transistor structure that decreases source/drain (S/D) resistance without increasing gate-to-S/D capacitance, thereby increasing device operation. S/D structures are formed into recesses formed on a semiconductor wafer through a semiconductor layer and a first layer of a buried insulator having at least two layers. A body is formed from the semiconductor layer situated between the recesses, and the body comprises a top body surface and a bottom body surface that define a body thickness. Top portions of the S/D structures are within and abut the body thickness. An improved method for forming the improved transistor structure is also described and comprises: forming recesses through a semiconductor layer and a first layer of a buried insulator so that a body is situated between the recesses; and forming S/D structures into the recesses so that top portions of the S/D structures are within and abut a body thickness.

Abstract: A semiconductor device having a structure in which no short circuit occurs between plug interconnections even when a void occurs in an insulating layer in a gap between wiring layers and a method of manufacturing the same are attained. The method includes: a step of forming transfer gates so as to be close to each other with a gap on a semiconductor substrate; a step of burying the gap and covering a wiring layer; a step of opening a contact hole in an insulating layer in the gap portion; a step of depositing a short-circuit preventing insulating film in the contact hole; an etch back step of removing the short-circuit preventing insulating film at least on the bottom of the gap to expose the semiconductor substrate; and a step of forming a plug interconnection.

Abstract: A semiconductor device of the present invention has (1) an active element provided on a semiconductor substrate, (2) an interlayer insulating film formed so as to cover the active element, (3) a pad metal for an electrode pad which is provided on the interlayer insulating film, (4) a barrier metal layer which is provided on the active element with the interlayer insulating film therebetween, so that the pad metal is formed on the barrier metal layer, and (5) an insulating layer having high adherence to the barrier metal layer, the insulating layer being provided between the interlayer insulating film and the barrier metal layer. With this arrangement, the adherence between the barrier metal layer, the insulating film and the interlayer insulating film is surely improved, and even in the case where an external force is applied to the electrode pad upon bonding or after bonding, the barrier metal layer hardly comes off the part thereunder.

Abstract: A semiconductor device and a method of making it are described. During the formation of the semiconductor device, a hard mask is formed of an etch-resistant material. The mask prevents etchant from etching an area within a dielectric material near a conductive plug. The mask may be formed of a nitride. Conductive material is then deposited withinan etched via and is contacted with the conductive plug.

Abstract: A semiconductor integrated circuit device has a semiconductor substrate, an interlayer insulating film including SiOF films formed on a main surface of the semiconductor substrate, a wiring groove formed by dry etching of the interlayer insulating film, and a Cu wiring buried in the wiring groove by a Damascene method, wherein a silicon oxynitride film is provided between a silicon nitride film serving as an etching stopper layer for the dry etching and the SiOF film, so that free F generated in the SiOF film is trapped with the silicon oxynitride film.

Abstract: A semiconductor device and a method for manufacturing the same, wherein a gate electrode structure is formed on a surface of a semiconductor substrate. Next, a gate poly oxide (GPOX) layer is deposited on a surface of the gate electrode structure and on the semiconductor substrate. Then, the surface of the semiconductor substrate is cleaned to remove any residue and the GPOX layer remaining on the semiconductor substrate. Next, an etch stopper is formed on the surface of the gate electrode structure and on the semiconductor substrate. Last, a high-density plasma (HDP) oxide layer is deposited on the etch stopper. The semiconductor device and method for manufacturing the same are capable of preventing bubble defects.

Abstract: A semiconductor device of this invention includes a silicon nitride film formed on a semiconductor substrate and having a density of 2.2 g/cm3 or less, and a silicon oxide film formed on the silicon nitride film in an ambient atmosphere containing TEOS and O3.

Abstract: An electronic structure having a first conductive layer provided by a dual damascene fabrication process; an etch-stop layer provided by the fabrication process, and electrically coupled with the first conductive layer, the etch-stop layer having a preselected dielectric constant and a predetermined geometry; and a second conductive layer, electrically coupled with the etch-stop layer. The structure can be, for example, a metal-insulator-metal capacitor, an antifuse, and the like.

Abstract: A low-k dielectric metal conductor interconnect structure having no micro-trenches present therein and a method of forming such a structure are provided. Specifically, the above structure is achieved by providing an interconnect structure which includes at least a multilayer of dielectric materials which are applied sequentially in a single spin apply tool and then cured in a single step and a plurality of patterned metal conductors within the multilayer of spun-on dielectrics. The control over the conductor resistance is obtained using a buried etch stop layer having a second atomic composition located between the line and via dielectric layers of porous low-k dielectrics having a first atomic composition. The inventive interconnect structure also includes a hard mask which assists in forming the interconnect structure of the dual damascene-type.

Abstract: A nonvolatile semiconductor memory device includes comprises: an element isolation region being in contact with a first element region, an insulating film covering a memory cell, a peripheral transistor and the element isolation region, an inter-level insulating film provided on the surface of the insulating film, and a contact hole provided in the inter-level insulating film and the insulating film. The inter-level insulating film contains an insulator different from the insulating film. The contact hole reaches at least one of source and drain diffusion layers of the memory cell and overlaps the element isolation region. The insulating film contains an insulator different from the element isolation region and the insulating film is harder for an oxidizing agent to pass therethrough than a silicon oxide film. A surface of the insulating film is oxidized.

Abstract: Shallow trench isolation among transistors and other devices on a semiconductor substrate is provided by initially forming a plurality of light absorbing layers having a combined extinction coefficient >0.5. As reflected light passes through the light absorbing layers, a substantially amount of light is absorbed therein thereby blocking such reflected light from negatively interfering with patterning of the photoresist during photo-lithography. Following patterning of the photoresist, isolation trenches are formed in the semiconductor substrate by etching through the light absorbing layers and into the semiconductor substrate in accordance with the pattern formed on the photoresist.

Abstract: A method, apparatus and system are provided for relieving stress in the via structures of semiconductor structures whenever a linewidth below a via is larger than a ground-rule, including providing a via at least as large as the groundrule, providing a landing pad above the via, providing a via bar in place of a via, slotting the metal linewidth below the via, or providing an oversize via with a sidewall spacer.

Abstract: A lower insulation layer, a charge storing layer, and an upper insulation layer are sequentially stacked on a substrate to form a gate insulation layer. A gate conductive layer is formed on the gate insulation layer. The gate electrode is patterned to expose a surface of the gate insulation layer. The charge storing layer is a barrier layer to oxygen diffusion during oxidization for curing etching damages caused by patterning. Thus, a gate bird's beak is prevented in the lower insulation layer. Spacers are formed on sidewalls of the gate electrode. The upper insulation layer is etched using the gate electrode and the spacers as an etch mask. Impurity ions are implanted into the substrate adjacent to the gate electrode to form an impurity region. Since an upper insulation layer is not exposed during the ion implantation process, the upper insulation layer is not damaged.

Abstract: An etch-stop layer is selectively provided between layers of a multiple-layered circuit in a selective manner so as to allow for outgassing of impurities during subsequent fabrication processes. The etch-stop layer is formed over an underlying stud so as to serve as an alignment target during formation of an overlying stud formed in an upper layer. In this manner multiple-layered circuits, for example memory devices, can be fabricated in relatively dense configurations.

Abstract: An exemplary implementation of the invention is a process for forming passivation protection on a semiconductor assembly by the steps of: forming a layer of oxide over patterned metal lines having sidewalls; forming a first passivation layer of silicon nitride over the layer of oxide such that the first passivation layer of silicon nitride resides along the sidewalls of metal lines and pinches off a gap between the metal lines; performing a facet etch to remove material from the edges of the first passivation layer of silicon nitride and re-deposits some of removed material across a pinch-off junction; forming a second passivation layer of silicon nitride on the first passivation layer of silicon nitride.

Abstract: The present invention provides a semiconductor device having a protective layer for use in packaging the semiconductor device. The apparatus includes a dielectric layer, a first passivation layer formed above the dielectric layer, and a protective layer formed above the first passivation layer, the protective layer adapted to reduce stress defect failures in the semiconductor device when packaged.

Abstract: This invention provides a capacitor and a method for manufacturing of the same, which are adaptable to preventing a lower electrode from being oxidized at a following thermal process. The capacitor includes: a lower electrode; an oxidation barrier layer formed on the lower electrode, wherein the oxidation barrier layer is formed of at least double nitridation layers; a dielectric layer formed on the oxidation barrier layer; and an upper electrode formed on the dielectric layer.

Abstract: Disclosed is a semiconductor device comprising a semiconductor substrate, a gate electrode, a first insulating film formed between the semiconductor substrate and the gate electrode, and a second insulating film formed along a top surface or a side surface of the gate electrode and including a lower silicon nitride film containing nitrogen, silicon and hydrogen and an upper silicon nitride film formed on the lower silicon nitride film and containing nitrogen, silicon and hydrogen, and wherein a composition ratio N/Si of nitrogen (N) to silicon (Si) in the lower silicon nitride film is higher than that in the upper silicon nitride film.

Abstract: A method and structure for fabricating isolation regions on a silicon on insulator (SOI) substrate, wherein the SOI substrate comprises a buried oxide layer and a silicon layer disposed on the buried oxide layer, wherein the silicon layer is less than about 20 nanometers. The method and structure includes a nitride liner layer conformally deposited in the isolation regions.

Abstract: A method and structure for fabricating isolation regions on a silicon on insulator (SOI) substrate, wherein the SOI substrate comprises a buried oxide layer and a silicon layer disposed on the buried oxide layer, wherein the silicon layer is less than about 20 nanometers. The method and structure includes a nitride liner layer conformally deposited in the isolation regions.