Abstract: A protective insulation film covering a surface of a compound semiconductor region is formed to have a two-layer structure of a first insulation film and a second insulation film which have different properties. The first insulation film is a non-stoichiometric silicon nitride film while the second insulation film is a silicon nitride film in an almost stoichiometric state.

Abstract: A semiconductor device according to an embodiment, includes a dielectric film and an Si semiconductor part. The dielectric film is formed by using one of oxide, nitride and oxynitride. The Si semiconductor part is arranged below the dielectric film, having at least one element of sulfur (S), selenium (Se), and tellurium (Te) present in an interface with the dielectric film, and formed by using silicon (Si).

Abstract: A semiconductor device includes a substrate, a semiconductor, a first surface passivation film including nitride, a second passivation film, a gate electrode, and a source electrode and a drain electrode. The semiconductor layer is provided on the substrate. The first surface passivation film including nitride is provided on the semiconductor layer and has at least two openings. The second surface passivation film covers an upper surface and a side surface of the first surface passivation film. The gate electrode is provided on a part of the second surface passivation film. The source electrode and the drain electrode are respectively provided on the two openings. In addition, the second surface passivation film includes a material of which melting point is higher than the melting points of the gate electrode, the source electrode, and the drain electrode.

Abstract: A semiconductor light emission device is disclosed. The semiconductor light emission device includes: a substrate; a current concentration preventing pattern formed in a mesh net shape on the substrate; an n-type clad layer formed on the substrate loaded with the current concentration preventing pattern; an active layer and a p-type clad layer sequentially formed on the n-type clad layer; an n-type electrode formed on a part of the n-type clad layer which is exposed by partially etching the p-type clad layer and active layer; and a p-type electrode formed on the p-type clad layer. The current concentration preventing pattern is formed in a double layer structure which includes a first layer formed from one material of SiO and SiN and on the substrate, and a second layer formed from a metal material and on the first layer.

Abstract: Disclosed are a passivation film for an electronic device having a nitride film formed on a substrate by a plasma-enhanced chemical vapor deposition (PECVD) method using a silicon-containing gas and a nitrogen-containing gas and a plasma-processed film formed by plasma processing a surface of the nitride film by a PECVD method using an NH3 gas, an N2 gas, and a H2 gas, and a method of manufacturing the passivation film.

Abstract: Some embodiments include patterning methods. First and second masking features may be formed over first and second regions of a semiconductor base, respectively. A protective mask may be formed over the second masking features. First and second spacers may be formed along sidewall edges of the first masking features and along lateral edges of the protective mask, respectively. The protective mask and the first masking features may be removed without removing the second masking features, without removing the first spacers, and without removing the second spacers. The first spacers may be third masking features that are at a tighter pitch than the first masking features. Patterns of the second masking features and the third masking features may be transferred into the semiconductor base. Some embodiments include patterned semiconductor bases.

Abstract: An integrated circuit device includes a plurality of stacked circuit layers, at least one of the plurality of circuit layers including a composite interlayer insulation layer including laterally adjacent first and second insulating material regions having different mechanical strengths and dielectric properties and a plurality of circuit components disposed in the composite interlayer insulation layer. The first insulating material region may have a lower dielectric constant and a lower mechanical strength than the second insulating material region such that, for example, the first insulating material region may be positioned near signal lines or other circuit features to reduce capacitance while using the second insulating material region near a location that is susceptible to localized mechanical stress, such as a fuse location, an external connection bonding location or a scribe line location.

Abstract: The present invention may be a semiconductor device including of a fluorinated insulating film and a SiCN film deposited on the fluorinated insulating film directly, wherein a density of nitrogen in the SiCN film decreases from interface between the fluorinated insulating film and the SiCN film. In the present invention, the SiCN film that is highly fluorine-resistant near the interface with the CFx film and has a low dielectric constant as a whole can be formed as a hard mask.

Abstract: A semiconductor device and its manufacturing method, wherein the NMOS device is covered by a layer of silicon nitride film having a high ultraviolet light absorption coefficient through PECVD, said silicon nitride film can well absorb ultraviolet light when being subject to the stimulated laser surface anneal so as to achieve a good dehydrogenization effect, and after dehydrogenization, the silicon nitride film will have a high tensile stress; since the silicon nitride film has a high ultraviolet light absorption coefficient, there is no need to heat the substrate, thus avoiding the adverse influences to the device caused by heating the substrate to dehydrogenize, and maintaining the heat budget brought about by the PECVD process.

Abstract: Disclosed are: a silicon nitride film of a semiconductor element, which is formed by applying a bias power and appropriately controls hydrogen leaving from the silicon nitride film; and a method and apparatus for producing a silicon nitride film. Specifically disclosed is a silicon nitride film which is formed on a substrate (19) by plasma processing and used in a semiconductor element. If the silicon nitride film is in contact with a film (41) to which supply of hydrogen is required to be shut off, the silicon nitride film is configured of a biased SiN (31) that is formed by applying a bias to the substrate (19) and an unbiased SiN (32) that is formed without applying a bias to the substrate (19) and the unbiased SiN (32) is arranged on the side on which the silicon nitride film is in contact with the film (41).

Abstract: A dielectric capping layer having a dielectric constant of less than 4.2 is provided that exhibits a higher mechanical and electrical stability to UV and/or E-Beam radiation as compared to conventional dielectric capping layers. Also, the dielectric capping layer maintains a consistent compressive stress upon post-deposition treatments. The dielectric capping layer includes a tri-layered dielectric material in which at least one of the layers has good oxidation resistance, is resistance to conductive metal diffusion, and exhibits high mechanical stability under at least UV curing. The low k dielectric capping layer also includes nitrogen content layers that contain electron donors and double bond electrons. The low k dielectric capping layer also exhibits a high compressive stress and high modulus and is stable under post-deposition curing treatments, which leads to less film and device cracking and improved device reliability.

Abstract: A composite dielectric layer including a tensile stressed nitride layer over an oxide layer serves the dual function of acting as an SMT (stress memorization technique) film while an annealing operation is carried out and then remains partially intact as it is patterned to further serve as an RPO film during a subsequent silicidation process. The composite dielectric layer covers part of a semiconductor substrate that includes a gate structure. The tensile stressed nitride layer protects the oxide layer and alleviates oxide damage during a pre-silicidation PAI (pre-amorphization implant) process. Portions of the gate structure and the semiconductor substrate not covered by the composite dielectric layer include amorphous portions that include the PAI implanted dopant impurities. A silicide material is disposed on the gate structure and portions of the semiconductor substrate not covered by the composite dielectric layer.

Abstract: A method for the deposition of an anti-reflection film on a substrate is disclosed. A substrate including a plurality of solar cell structures is provided and placed in a vacuum chamber with a target including silicon. A flow of a nitrogen-containing reactive gas into the vacuum chamber is set to a first value while a voltage between the target and ground is switched off and then increased to a second value. A voltage is applied between the target and ground, whereby a film of silicon and nitrogen is deposited on the substrate in a flow of the nitrogen-containing reactive gas which is higher than the first value.

Abstract: A method of manufacturing a semiconductor bio-sensor comprises providing a substrate, forming a first dielectric layer on the substrate, forming a patterned first conductive layer on the first dielectric layer, the patterned first conductive layer including a first portion and a pair of second portions, forming a second dielectric layer, a third dielectric layer and a fourth dielectric layer in sequence over the patterned first conductive layer, forming cavities into the fourth dielectric layer, forming vias through the cavities, exposing the second portions of the patterned first conductive layer, forming a patterned second conductive layer on the fourth dielectric layer, forming a passivation layer on the patterned second conductive layer, forming an opening to expose a portion of the third dielectric layer over the first portion of the patterned first conductive layer, and forming a chamber through the opening.

Abstract: The semiconductor light receiving element 1 includes a semiconductor substrate 101, and a semiconductor layer having a photo-absorption layer 105 disposed on the top of the semiconductor substrate 101. The semiconductor layer of the semiconductor light receiving element 1 containing at least the photo-absorption layer 105 has a mesa structure, and a side wall of the mesa is provided with a protective film 113 covering the side wall. The protective film 113 is a silicon nitride film containing hydrogen, and a hydrogen concentration in one surface of the protective film 113 located at the side of the mesa side wall is lower than a hydrogen concentration in the other surface of the protective film 113 located at the side that is opposite to the side of the mesa side wall.

Abstract: A semiconductor device including: a silicon dioxide layer; an n-type field effect transistor (NFET) including at least one recessed source/drain trench and located over a portion of the silicon dioxide layer; a p-type field effect transistor (PFET) including at least one recessed source/drain trench and located over a portion of the silicon dioxide layer; a nitride stress liner over the NFET and the PFET, the nitride stress liner filling the at least one recessed source/drain trench of the NFET and the at least one recessed source/drain trench of the PFET; and a first contact formed in the silicon dioxide layer, the first contact abutting one of the NFET or the PFET.

Abstract: Disclosed are a passivation film for an electronic device having a nitride film formed on a substrate by a plasma-enhanced chemical vapor deposition (PECVD) method using a silicon-containing gas and a nitrogen-containing gas and a plasma-processed film formed by plasma processing a surface of the nitride film by a PECVD method using an NH3 gas, an N2 gas, and a H2 gas, and a method of manufacturing the passivation film.

Abstract: The invention relates to a nonvolatile semiconductor memory cell and to an associated fabrication method, a source region (7), a drain region (8) and a channel region lying in between being formed in a substrate (1). In order to realize locally delimited memory locations (LB, RB), an electrically non-conductive charge storage layer (3) situated on a first insulation layer (2) is divided by an interruption (U), thereby preventing, in particular, a lateral charge transport between the memory locations (LB, RB) and significantly improving the charge retention properties.

Abstract: A method of forming an integrated circuit includes forming magnetic tunnel junction (MTJ) layers; etching the MTJ layers to form a MTJ cell; and forming a dielectric capping layer on sidewalls of the MTJ cell, wherein the step of forming the dielectric capping layer is in-situ performed with the step of etching the MTJ layers.

Abstract: An alpha particle blocking structure and method of making the structure. The structure includes: a semiconductor substrate; a set of interlevel dielectric layers stacked from a lowermost interlevel dielectric layer closest to the substrate to a uppermost interlevel dielectric layer furthest from the substrate, each interlevel dielectric layer of the set of interlevel dielectric layers including electrically conductive wires, top surfaces of the wires substantially coplanar with top surfaces of corresponding interlevel dielectric layers; an electrically conductive tot final pad contacting a wire pad of the uppermost interlevel dielectric layer; an electrically conductive plating base layer contacting a top surface of the terminal pad; and a copper block on the plating base layer.

Abstract: A strengthened semiconductor die substrate and package are disclosed. The substrate may include contact fingers formed with nonlinear edges. Providing a nonlinear contour to the contact finger edges reduces the mechanical stress exerted on the semiconductor die which would otherwise occur with straight edges to the contact fingers. The substrate may additionally or alternatively include plating traces extending at an angle from the contact fingers. Extending at an angle, at least the ends of the plating traces at the edge of the substrate are covered beneath a lid in which the semiconductor package is encased. Thus, when in use with a host device, contact between the ends of the plating traces beneath the lid and contact pins of the host device is avoided.

Abstract: A method for making a semiconductor device including at least three interconnection layers sequentially stacked without intervention of a via layer. At least one of the interconnection layers includes an interconnection and a via which connects interconnections provided in interconnection layers underlying and overlying the one interconnection layer.

Abstract: An SOI substrate having an SOI layer that can be used in practical applications even when a substrate with low upper temperature limit, such as a glass substrate, is used, is provided. A semiconductor device using such an SOI substrate, is provided. In bonding a single-crystal semiconductor layer to a substrate having an insulating surface or an insulating substrate, a silicon oxide film formed using organic silane as a material on one or both surfaces that are to form a bond is used. According to the present invention, a substrate with an upper temperature limit of 700° C. or lower, such as a glass substrate, can be used, and an SOI layer that is strongly bonded to the substrate can be obtained. In other words, a single-crystal semiconductor layer can be formed over a large-area substrate that is longer than one meter on each side.

Abstract: An integrated circuit device includes a plurality of stacked circuit layers, at least one of the plurality of circuit layers including a composite interlayer insulation layer including laterally adjacent first and second insulating material regions having different mechanical strengths and dielectric properties and a plurality of circuit components disposed in the composite interlayer insulation layer. The first insulating material region may have a lower dielectric constant and a lower mechanical strength than the second insulating material region such that, for example, the first insulating material region may be positioned near signal lines or other circuit features to reduce capacitance while using the second insulating material region near a location that is susceptible to localized mechanical stress, such as a fuse location, an external connection bonding location or a scribe line location.

Abstract: A barrier film formed on top of a substrate, a barrier film formed so as to cover a functional element region fabricated on top of a substrate, or a barrier film formed on both a substrate and a functional element region, wherein the barrier film includes at least one layer of a silicon nitride film formed by laminating two or more silicon nitride layers having different Si/N composition ratios.

Abstract: A method for forming silicon nitride films on semiconductor devices is provided. In one embodiment of the method, a silicon-comprising substrate is first exposed to a mixture of dichlorosilane (DCS) and a nitrogen-comprising gas to deposit a thin silicon nitride seeding layer on the surface, and then exposed to a mixture of silicon tetrachloride (TCS) and a nitrogen comprising gas to deposit a TCS silicon nitride layer on the DCS seeding layer. In another embodiment, the method involves first nitridizing the surface of the silicon-comprising substrate prior to forming the DCS nitride seeding layer and the TCS nitride layer. The method achieves a TCS nitride layer having a sufficient thickness to eliminate bubbling and punch-through problems and provide high electrical performance regardless of the substrate type. Also provided are methods of forming a capacitor, and the resulting capacitor structures.

Abstract: The present invention provides an SOS wafer comprising a non-transparent polysilicon layer provided on a back surface of a sapphire substrate, a silicon nitride layer which protects the polysilicon layer, and a stress relaxing film which cancels stress produced in the silicon nitride layer, wherein the silicon nitride layer and the stress relaxing film are provided on the back surface side.

Abstract: A method of creating insulating layers on different semiconductor materials includes providing a substrate having disposed thereon a first material and a second material, the second material having a chemical composition different from the first material; non-epitaxially depositing a continuous sacrificial layer of approximately constant thickness onto the first material and the second material, and then converting the sacrificial layer into a layer consisting essentially of SiO2 without oxidizing more than 10 angstroms into the second material. A structure includes a silicon nitride film disposed conformally on a silicon layer and a silicon germanium layer; a SiO2 layer is disposed on the silicon nitride film.

Abstract: A semiconductor device including a compound semiconductor laminated structure having a plurality of compound semiconductor layers formed over a semiconductor substrate, a first insulation film covering at least a part of a surface of the compound semiconductor laminated structure, and a second insulation film formed on the first insulation film, wherein the second insulation film includes more hydrogen than the first insulation film.

Abstract: A method of fabricating an integrated circuit including arranging a plurality of cells to form a desired floor plan of the integrated circuit, wherein each cell comprises at least one transistor, forming a plurality of circuit constituents from the plurality of cells of the floor plan, wherein each circuit constituent comprises at least one cell and belongs to one of a plurality circuit constituent types, and applying mechanical stress to channel regions of the at least one transistor of each cell based on the circuit constituent type of the circuit constituent to which the cell belongs.

Abstract: Embodiments of semiconductor devices are provided. In one embodiment, the semiconductor device includes a substrate, an etch stop layer formed on the substrate, an adhesion promotion layer formed directly on the etch stop layer, and a dielectric layer formed directly on the adhesion promotion layer. The etch stop layer may include silicon, carbon, and nitrogen. The dielectric layer may include silicon, oxygen, and carbon. The adhesion promotion layer may include carbon, oxygen, and nitrogen. An example of an adhesion promotion layer includes polyimide.

Abstract: A dielectric layer including a film with silicon compound contain oxygen and a film with silicon compound contain nitrogen is provided. A ratio of Si—N group absorption intensity to a thickness of the film with silicon compound contain nitrogen in an FTIR spectrum is substantially greater than or substantially equal to 0.67/?m. The dielectric layer can be incorporated in switch devices.

Abstract: According to one embodiment of the disclosure, a method for passivating a circuit device generally includes providing a substrate having a substrate surface, forming an electrical component on the substrate surface, and coating the substrate surface and the electrical component with a first protective dielectric layer. The first protective dielectric layer is made of a generally moisture insoluble material having a moisture permeability less than 0.01 gram/meter2/day, a moisture absorption less than 0.04 percent, a dielectric constant less than 10, a dielectric loss less than 0.005, a breakdown voltage strength greater than 8 million volts/centimeter, a sheet resistivity greater than 1015 ohm-centimeter, and a defect density less than 0.5/centimeter2.

Abstract: Disclosed are embodiments of a wafer that incorporates fill structures with varying configurations to provide uniform reflectance. Uniform reflectance is achieved by distributing across the wafer fill structures having different semiconductor materials such that approximately the same ratio and density between the different semiconductor materials is achieved within each region and, optimally, each sub-region. Alternatively, it is achieved by distributing across the wafer fill structures, including one or more hybrid fill structure containing varying proportions of different semiconductor materials, such that approximately the same ratio between the different semiconductor materials is achieved within each region and, optimally, each sub-region.

Abstract: A capacitance dielectric layer is provided. The capacitance dielectric layer includes a first dielectric layer, a second dielectric layer and a silicon nitride stacked layer. The silicon nitride stacked layer is disposed between the first dielectric layer and the second dielectric layer. The structure of the capacitance dielectric layer permits an increase in the capacitance per unit area by decreasing the thickness of the capacitance dielectric layer and eliminates the problems of having a raised leakage current and a diminished breakdown voltage.

Abstract: There are disclosed TFTs having improved reliability. An interlayer dielectric film forming the TFTs is made of a silicon nitride film. Other interlayer dielectric films are also made of silicon nitride. The stresses inside the silicon nitride films forming these interlayer dielectric films are set between ?5×109 and 5×109 dyn/cm2. This can suppress peeling of the interlayer dielectric films and difficulties in forming contact holes. Furthermore, release of hydrogen from the active layer can be suppressed. In this way, highly reliable TFTs can be obtained.

Abstract: A stress-transmitting dielectric layer is formed on the at least one PFET and the at least one NFET. A tensile stress generating film, such as a silicon nitride, is formed on the at least one NFET by blanket deposition and patterning. A compressive stress generating film, which may be a refractive metal nitride film, is formed on the at least one PFET by a blanket deposition and patterning. An encapsulating dielectric film is deposited over the compress stress generating film. The stress is transferred from both the tensile stress generating film and the compressive stress generating film into the underlying semiconductor structures. The magnitude of the transferred compressive stress from the refractory metal nitride film may be from about 5 GPa to about 20 GPa. The stress is memorized during an anneal and remains in the semiconductor devices after the stress generating films are removed.

Abstract: An inventive semiconductor device includes at least three interconnection layers sequentially stacked without intervention of a via layer. At least one of the interconnection layers includes an interconnection and a via which connects interconnections provided in interconnection layers underlying and overlying the one interconnection layer.

Abstract: A highly stressed dielectric material, such as a tensile stressed material, may be deposited in a conformal manner so as to respect any deposition constraints caused by pronounced surface topography of highly scaled semiconductor devices, followed by the deposition of a buffer material having enhanced gap-filling capabilities. Thereafter, a further stress-inducing layer is deposited to form a doublet structure, which acts on the transistor elements, thereby enhancing overall performance, without increasing the probability of creating deposition-related irregularities. Hence, production yield as well as performance of highly scaled semiconductor devices may be increased.

Abstract: In one aspect, the invention includes a semiconductor processing method. An antireflective material layer is formed over a substrate. At least a portion of the antireflective material layer is annealed at a temperature of greater than about 400° C. A layer of photoresist is formed over the annealed antireflective material layer. The layer of photoresist is patterned. A portion of the antireflective material layer unmasked by the patterned layer of photoresist is removed. In another aspect, the invention includes the following semiconductor processing. An antireflective material layer is formed over a substrate. The antireflective material layer is annealed at a temperature of greater than about 400° C. A layer of photoresist is formed over the annealed antireflective material layer. Portions of the layer of photoresist are exposed to radiation waves. Some of the radiation waves are absorbed by the antireflective material during the exposing.

Abstract: A method is disclosed for producing a semiconductor device produced by (i) doping hydrogen ions or rare gas ions into a device substrate in which a transfer layer (16) is formed, (ii) then bonding the device substrate to a carrier target substrate, and (iii) transferring the transfer layer (16) onto the carrier substrate (30) by cleaving the device substrate along a portion in which the hydrogen ions or the rare gas ions are doped, the method including providing a blocking layer (11) for blocking diffusion of a bubble-causing substance between (i) a bonding surface (13), which serves as a bonding interface between the device substrate and the carrier substrate, and (ii) the transfer layer (16). This prevents bubbles from forming at the bonding interface between the semiconductor substrate and the target substrate due to the diffusion of the bubble-causing substance.

Abstract: A structure and a method of making the structure. The structure includes a field effect transistor including: a first and a second source/drain formed in a silicon substrate, the first and second source/drains spaced apart and separated by a channel region in the substrate; a gate dielectric on a top surface of the substrate over the channel region; and an electrically conductive gate on a top surface of the gate dielectric; and a dielectric pillar of a first dielectric material over the gate; and a dielectric layer of a second dielectric material over the first and second source/drains, sidewalls of the dielectric pillar in direct physical contact with the dielectric layer, the dielectric pillar having no internal stress or an internal stress different from an internal stress of the dielectric layer.

Abstract: In a method for manufacturing a layer arrangement, a plurality of electrically conductive structures are embedded in a substrate. Material of the substrate is removed at least between adjacent electrically conductive structures. An interlayer is formed on at least one portion of sidewalls of each of the electrically conductive structures. A first layer is formed on the interlayer where an upper partial region of the interlayer remaining free of a covering with the first layer. An electrically insulating second layer is formed selectively on that partial region of the interlayer which is free of the first layer, in such a way that the electrically insulating second layer bridges adjacent electrically conductive structures such that air gaps are formed between adjacent electrically conductive structures.

Abstract: In one aspect, the invention includes a semiconductor processing method. An antireflective material layer is formed over a substrate. At least a portion of the antireflective material layer is annealed at a temperature of greater than about 400° C. A layer of photoresist is formed over the annealed antireflective material layer. The layer of photoresist is patterned. A portion of the antireflective material layer unmasked by the patterned layer of photoresist is removed. In another aspect, the invention includes the following semiconductor processing. An antireflective material layer is formed over a substrate. The antireflective material layer is annealed at a temperature of greater than about 400° C. A layer of photoresist is formed over the annealed antireflective material layer. Portions of the layer of photoresist are exposed to radiation waves. Some of the radiation waves are absorbed by the antireflective material during the exposing.

Abstract: An outer border, and a seal ring substantially co-extensive with and spaced from the outer border is disclosed. A plurality of fault detection chains extend from adjacent the outer border to within the seal ring. At least a first one of the plurality of fault detection chains includes a contact pad, a first metal feature coupled to the contact pad by a first via in a passivation layer, a second metal feature coupled to the first metal feature by a second via, and a substrate contact coupled to the second metal feature by a third via.

Abstract: Method of fabricating thin-film transistors in which contact with connecting electrodes becomes reliable. When contact holes are formed, the bottom insulating layer is subjected to a wet etching process, thus producing undercuttings inside the contact holes. In order to remove the undercuttings, a light etching process is carried out to widen the contact holes. Thus, tapering section are obtained, and the covering of connection wiring is improved.

Abstract: A method for reducing leakage current in a semiconductor structure is disclosed. One or more dielectric layers are formed on a semiconductor substrate, on which at least one device is constructed. A hydrogen-containing layer is formed over the dielectric layers. A silicon nitride passivation layer covers the dielectric layers and the hydrogen-containing layer. The hydrogen atoms of the hydrogen-containing layer are introduced into the dielectric layers without being blocked by the silicon nitride layer, thereby reducing leakage current therein.

Abstract: A 4-T SRAM cell in which two layers of permanent SOG (with an intermediate oxide layer) are used to provide planarization between the first and topmost poly layers.

Abstract: A semiconductor device is provided with a first insulating film, a first wiring layer formed in the first insulating film, a second insulating film formed above the first wiring layer and the first insulating film, the second insulating film including a low dielectric constant film, a second wiring layer formed in the second insulating film and coupled to the first wiring layer through a first connection section, and a third insulating film formed above the second wiring layer and the second insulating film and serving as one of an interlayer insulating film and a passivation film, and at least one of the first and third insulating films being one of a film formed mainly of SiON, a film formed mainly of SiN, and a laminated film being the films formed mainly of SiON or SiN respectively.

Abstract: According to one embodiment of the disclosure, a method for passivating a circuit device generally includes providing a substrate having a substrate surface, forming an electrical component on the substrate surface, and coating the substrate surface and the electrical component with a first protective dielectric layer. The first protective dielectric layer is made of a generally moisture insoluble material having a moisture permeability less than 0.01 gram/meter2/day, a moisture absorption less than 0.04 percent, a dielectric constant less than 10, a dielectric loss less than 0.005, a breakdown voltage strength greater than 8 million volts/centimeter, a sheet resistivity greater than 1015 ohm-centimeter, and a defect density less than 0.5/centimeter2.