Abstract: A method is described for fabricating a lightly doped drain MOSFET integrated circuit device. The method begins by forming a pattern of gate electrode structures upon a semiconductor substrate which structures each includes a gate oxide, a polysilicon layer and a refractory metal silicide. A thin silicon nitride layer is formed over each of the structures and the exposed surfaces therebetween of the substrate. A pattern of lightly doped regions in the substrate is formed by ion implantation using the polycide gate structures as the mask. A dielectric spacer structure is formed upon the sidewalls of each of the polycide gate structures and over the adjacent portions of the substrate. A pattern of heavily doped regions in the substrate is formed by ion implantation using the polycide structures with spacer structures as the mask to produce the lightly doped drain source/drain structures of an MOSFET device.

Abstract: A method is provided for patterning a submicron semiconductor layer of an integrated circuit, and an integrated circuit formed according to the same. An interlevel dielectric layer is formed over the surface of the integrated circuit. A substantially planarizing layer is formed over the interlevel dielectric layer. A photoresist layer is formed and patterned over the planarizing layer. The planarizing layer is etched to form openings exposing selected portions of the interlevel dielectric layer, wherein each opening has substantially the same lateral dimensions. The photoresist and planarizing layers are then removed. The interlevel dielectric layer is etched in the openings to expose portions of the underlying integrated circuit.

Abstract: An integrated circuit comprises a charge coupled device and an MOS transistor. The charge coupled device has a lower and an upper gate electrode on the substrate. The insulating film between the substrate and the electrodes comprises silicon nitride. The insulating film between the electrodes is formed by thermal oxidizing the lower gate electrode using the silicon nitride film as a mask.

Abstract: A semiconductor Nonvolatile memory. The memory cell has the following structure. Within a P type silicon substrate 3, there are provided an n.sup.+ type source 26 and an n.sup.+ type drain 28, the two regions forming a channel region 30. On top of the channel region 30 there are laminated a silicon dioxide film 5, an insulating layer which consists of the nitride film 18a,18b and 18c, and the oxide film 20a,20b and 20c. Further, on top of the insulating layer, there is formed a polysilicon film 24, which serves as a control electrode. By using the memory cell and row select transistor a semiconductor nonvolatile memory can be constructed.

Abstract: A semiconductor device is protected by a passivation layer, which includes underlying and overlying silicon nitride layers deposited by the plasma-assisted CVD method by changing layer forming conditions. The silicon nitride layers respectively have their intrinsic compressive stresses. The underlying silicon nitride layer in contact with a metal wiring layer has the intrinsic compressive stress of 3.times.10.sup.9 to 1.times.10.sup.10 dyne/cm.sup.2. The overlying silicon nitride layer has the intrinsic compressive stress which is less than or equal to half of the intrinsic compressive stress of the underlying silicon nitride layer. The underlying and overlying silicon nitride layers have different degrees of the hydrogen content. The underlying silicon nitride layer has the hydrogen content of 0.5.times.10.sup.20 to 5.times.10.sup.21 atm/cm.sup.3. The overlying silicon nitride layer has the hydrogen content which is more than or equal to twice of the hydrogen content of the underlying silicon nitride layer.

Abstract: An electrically programmable read only memory device store data bits in the form of electric charges accumulated in floating gate electrodes of the memory cells, and a spin-on glass film is incorporated in an inter-level insulating film structure over the memory cells so as to create a smooth surface for wirings, wherein a silicon oxynitride film is inserted between the floating gate electrodes and the spin-on-glass film for preventing the accumulated electric charges from undesirable ion-containing water diffused from the spin-on-glass film.

Abstract: In a nonvolatile semiconductor memory device with a two-layer gate structure, an interlayer insulating film is formed on a floating gate electrode of, e.g., polycrystalline silicon. The interlayer insulating film has a four-layer structure in which a first silicon nitride film, a first silicon oxide film, a second silicon nitride film and a second silicon oxide film are laminated in this order on the floating gate electrode, or a two-layer structure in which a first silicon nitride film and a first silicon oxide film are laminated in this order on the floating gate electrode. With the above structure, the threshold voltage of the semiconductor device is stabilized even after data-erase operation. Since, moreover, the first silicon oxide film can be formed by oxidizing the first silicon nitride film, then the quality of the first silicon oxide film can be enhanced, and accordingly the charge retaining properties of the device can be increased.

Abstract: A cryogenic radiation-hard dual-layer field oxide of reoxidized nitrided oxide (ONO) which provides radiation hardness for field-effect transistors and other semiconductor devices at cryogenic temperatures. The dual-layer field oxide includes a thin lower dielectric layer of reoxidized nitrided oxide and an upper deposited dielectric layer that remains charge neutral. The upper dielectric layer is preferably silicon nitride or a doped oxide, such as phospho silicate glass or boro phospho silicate glass. The lower dielectric layer can be made very thin since reoxidized nitrided oxide is a much better barrier layer to the diffusion of boron or phosphorous from the upper dielectric layer into the silicon substrate than silicon dioxide. A thin lower dielectric layer allows only a small amount of positive charge buildup, while the upper dielectric layer traps both holes and electrons and remains charge neutral.

Abstract: A silicon-on-insulator lateral bipolar transistor having an edge-strapped base contact is disclosed. A thin layer of oxide is deposited on a silicon-on-insulator structure and a layer of polysilicon is deposited on the thin oxide layer that is patterned and etched to form an extrinsic base region of the transistor. The polysilicon extrinsic base is very heavily doped and the thin oxide layer acts as both a diffusion stop and an etch stop during the formation of the extrinsic base. A silicon edge contact region is formed of selective epitaxy or polysilicon to connect the extrinsic base to the intrinsic base formed in the silicon-on-insulator layer.

Abstract: A gate insulating layer, which is formed on a channel region of a semiconductor substrate and interposed between the semiconductor substrate and a gate electrode, consists of a first part and a second part adjoining each other. The first part includes an oxide lower layer and a nitride upper layer, and a second part includes a nitride lower layer and an oxide upper layer.

Abstract: A trap film assembly of a semiconductor memory device includes a tunnel oxide layer formed on a semiconductor substrate and plural multi-layer film layers laminated on the tunnel oxide film. A thickness of each multi-layer film layer is sequentially increased in a direction away from the semiconductor substrate and towards a gate electrode, thereby displacing the charge centroid of the assembly towards the semiconductor substrate.

Abstract: A microwave plasma enhanced CVD method and apparatus wherein a microwave is applied, after expanded, over a greater area than the area in which a desired thin film is to be formed. With this arrangement, uniform microwave application is assured to produce uniform plasma over a wide area. This enables realization of a large size liquid crystal display.

Abstract: A semiconductor device including a semiconductor substrate with a P-type well formed in the semiconductor substrate and a gate insulator layer formed on the semiconductor substrate. N-type diffusion regions are formed in the P-type well on both sides of the gate insulator layer. A gate electrode is formed on the gate insulator layer, where the gate electrode has top and side surfaces. The gate electrode and the N-type diffusion regions respectively form gate, source and drain of a N-channel MOS transistor. An insulating layer covers a portion of the N-type diffusion regions, the side surfaces of the gate electrode and at least a portion of the top surface of the gate electrode. The side wall layer which is made of an insulating material is formed on the insulating layer to provide a smooth coverage around the side of the gate electrode and aligns with an edge of said insulating layer which stops covering the N-type diffusion regions.

Abstract: Methods and systems are disclosed for fabricating electrically programmable link structures by fabricating a first conductor, which comprises a refractory conductive material, then fabricating an insulative link material over the refractory conductive material and, subsequently, depositing an upper conductive material over the link material. In use, an electrical path can be formed between the first and second conductive elements by applying a voltage between such elements across at least one selected region of the insulator, such that the insulative link material is transformed in the region and rendered conductive to form an electrical signal path. The link material is preferably a silicon oxide insulator andThe U.S. Government has rights in this invention pursuant to Contract No. F19628-90-C-0002 awarded by the Department of the Air Force.

Abstract: A trench structure (10) using germanium silicate. The trench structure (10) has a substrate material (12) and a hard mask material (14) that overlies the substrate material (12). An opening is formed in the hard mask material and the opening is used to form a trench (16) in the substrate material (12). The trench (16) has a sidewall portion and a bottom portion. A barrier (18 and 20) is formed overlying the bottom portion of the trench (16) and adjacent to the sidewall portion of the trench (16). A planar germanium silicate region (22) is formed overlying the barrier (18 and 20).

Abstract: A resin molded type semiconductor device has a metallic guard ring that is formed to cover the peripheral edge of the surface of a tetragonal semiconductor substrate. In order to prevent a passivation film on the guard ring from being cracked by stresses due to a resin mold package concentrating in the four corners of the semiconductor substrate, slits or rows of small holes are formed in the corner portions of the guard ring.

Abstract: An improved semiconductor device having no posioned via produced therein includes a semiconductor substrate having a first conductor pattern formed thereon, a first insulator film provided on the semiconductor substrate to cover the first conductor pattern, and a coat applied onto the first insulator film to flatten an uneven surface of the first insulator film. A nitride layer having a thickness of 10.ANG. or more and including a binding of silicon and nitrogen is provided in a surface of the coat. A second insulator film is formed on the coat including the nitride layer. A via hole for exposing a portion of the surface of the first conductor pattern is formed to penetrate the first insulator film, the coat and the second insulator film. The device further includes a second conductor pattern having a portion thereof buried in the via hole and thereby connected to the first conductor pattern.

Abstract: A small-area single-transistor EEPROM memory cell includes buried bit lines (44,46) extending through the array and connecting together many memory cells. Formed above a channel area (25) and between the bit lines (44,46) are oxide-nitride-oxide layers (50,52,54) for providing isolation between overlying polysilicon word lines (56, 66) and the underlying conduction channel (25). The nitride layer (52) provides the charge retention mechanism for programming the memory cell. The word lines (56, 66) provide electrical contact to a number of memory cells in the row. Electrical contact is made to the word lines (56, 66) by metal contacts (68, 70), and to the bit lines (44,46) by metal contacts (72, 74) at the array periphery, thereby avoiding metal contacts to every memory cell of the array. A EEPROM memory cell of 4-5.2 microns can be fabricated.

Abstract: A semiconductor device comprises a substrate, first insulation layers formed on the substrate, and a second insulation layer formed on the substrate. The second insulation layer, which acts as a dielectric material of a capacitor component of the semiconductor device, is thinner than each of the first insulation layers.