Abstract: A 4-T SRAM cell in which two layers of permanent SOG (with an intermediate oxide layer) are used to provide planarization between the first and topmost poly layers.

Abstract: A semiconductor device, which has a silicon body that includes at least one planar p-n junction that intersects a surface of the body, uses a multilayer arrangement that includes a first layer of thermally grown silicon dioxide, a second layer of Chemical-Vapor-Deposited (CVD) silicon nitride, a third layer of CVD oxygen-rich polysilicon, and a fourth layer of CVD silicon dioxide to passivate the junction. Common metallization contacts both the diffused region of the planar junction and the oxygen-rich polysilicon.

Abstract: A semiconductor device (and method of manufacturing thereof) having metal leads (114+130) with improved reliability, comprising metal leads (114+130) on a substrate 112, a low-dielectric constant material (116) at least between the metal leads (114+130), and dummy vias (122+134) in contact with the metal leads (114+130). Heat from the metal leads (114+130) is transferable to the dummy vias (122+134), and the dummy vias (122+134) are capable of conducting away the heat. The low-dielectric constant material (116) may have a dielectric constant of less than about 3.5. An advantage of the invention is to improve reliability of metal leads in circuits using low-dielectric constant materials, especially in scaled-down circuits that are compact in the horizontal direction.

Abstract: The present invention provides a method of manufacturing a semiconductor device improved so that stress at a boundary between a semiconductor substrate and an element isolation oxide film can be relaxed. In the method, the surface of a semiconductor substrate is oxidized with a nitride film used as a mask to form an element isolation oxide film in the surface of semiconductor substrate. After removing an underlay oxide film and nitride film, semiconductor substrate is heat-treated at a temperature of 950.degree. C. or more. An element is formed in an element region.

Abstract: A semiconductor-on-diamond structure has a free-standing layer of diamond material that is thick enough to provide integrity for the integrated circuit and to insulate the circuit. The structure has a layer of diamond material 12 on a layer of silicon nitride 62. A device layer of semiconductor material 30 is positioned over the silicon nitride layer.

Abstract: A process for etching nitride layers in three steps is disclosed. The process comprises selecting a process chemistry of CF.sub.4 to CHF.sub.3 to set a predetermined critical dimension bias; conducting a primary etch of the process chemistry which will have a high etch rate; and conducting a secondary etch of ion bombardment having a lower etch rate and high selectivity to pad oxide. In selecting the process chemistry, selecting greater amounts of CHF.sub.3 will result in higher polymer concentration on the etched sidewall. Varying the pressure and power can also be used to vary the polymer concentration. This in turn is used to select the desired critical dimension bias. The secondary etch uses a mixture of NF.sub.3 and HBr and is performed at a high pressure and a low power to promote high nitride to oxide selectivity.

Abstract: Provided between a control gate electrode and a channel region of the EEPROM memory cell is a capacitor. Formed on the channel region are a first gate dielectric layer of silicon oxide, a first carrier capture layer of silicon nitride, a carrier migration layer of n.sup.31 polysilicon, a second carrier capture layer of silicon nitride, and a second gate dielectric layer of silicon oxide. The carrier capture state of the carrier capture layer is changed to generate a polarization state in the capacitor, and the generated polarization state is held as data. The gate dielectric layer is not destroyed since the movement of carriers is limited to within the capacitor, and by adjusting the carrier bound energy, low-voltage drive can be accomplished.

Abstract: A manufacturable III-V semiconductor gate structure having small geometries is fabricated. A silicon nitride layer is formed on a III-V semiconductor material and a dielectric layer comprised of aluminum is formed on the silicon nitride layer. Another dielectric layer comprised of silicon and oxygen is formed over the dielectric layer comprised of aluminum. The dielectric layer comprised of aluminum acts as an etch stop for the etching of the dielectric layer comprised of silicon and oxygen with a high power reactive ion etch. The dielectric layer comprised of aluminum may then be etched with a wet etchant which does not substantially etch the silicon nitride layer. Damage to the surface of the semiconductor material by exposure to the high power reactive ion etch is prevented by forming the dielectric layer comprised of aluminum between the silicon nitride layer and the dielectric layer comprised of silicon and oxygen.

Abstract: A thin film transistor includes a thin film transistor body above a gate electrode. The thin film transistor body is hydrogenated to prevent the transistor body from apparently capturing and releasing electrons. The transistor body itself is coated with an upper and lower layer of silicon nitride to prevent the trapped hydrogen from migrating out of the transistor body over time. This is formed by depositing a layer of silicon dioxide, then a layer of silicon nitride over the gate electrode, followed by deposition of a polysilicon layer which is then etched to form the transistor body. This is hydrogenated after threshold adjustment implant and source/drain implant and subsequently coated with an upper sealing layer of silicon nitride. This enables the establishment of relatively high Ion/Ioff ratio and improves the reliability of the transistor.

Abstract: A trench for element isolation is formed on the main surface of a semiconductor substrate. A conductive layer is formed in the trench, electrically connected to the semiconductor substrate. Oxide films and a dielectric film is formed between the conductive layer and the sidewall of the trench. A field oxide film is formed on the conductive layer. The dielectric film extends from the sidewall of the field oxide film to a region between the sidewall of the trench and the conductive layer. Consequently, a semiconductor device having an element isolation structure of superior isolation capability and high reliability can be obtained.

Abstract: A solid-state imaging device which restrains the smear phenomenon effectively without reduction of the dielectric breakdown strength between the transfer electrode and the light shielding film. A first insulating film covers photoelectrical converting regions each of which receives incident light through the first insulation film to generate and store a signal charge. A second insulating film covering a charge transfer region is of a layered structure containing a first insulation layer with a relatively lower dielectric constant such as SiO.sub.2 and a second insulation layer with a relatively higher dielectric constant such as Si.sub.3 N.sub.4. The distance between the transfer electrode and the light shielding film can be decreased, providing decrease in thickness of the first insulating film. The smear phenomenon is restrained effectively without reduction of the dielectric breakdown strength between the transfer electrode and the light shielding film.

Abstract: A method for passivating an integrated circuit includes the RF sputtering of a hard passivation layer on the surface of the integrated circuit. The hard passivation layer can be a ceramic material such as various doped and undoped titanates, zirconates, niobates, tantalates, stanates, hafnates, and manganates, in either their ferroelectric or non-ferroelectric phases. Other exotic, hard, and usually non-ferroelectric materials not normally found in integrated circuit processing such as carbides may also be used. If the integrated circuit sought to be passivated contains ferroelectric devices, the hard passivation layer can be fabricated out of the same material used in the integrated ferroelectric devices. An optional silicon dioxide insulating layer can be deposited on the surface of the integrated circuit before the hard passivation layer is deposited. The optional silicon dioxide layer is used to prevent any possible contamination of the integrated circuit by the passivation layer.

Abstract: High quality, ultra thin SiO.sub.2 /Si.sub.3 N.sub.4 (ON) dielectric layers have been fabricated by in situ multiprocessing and low pressure rapid-thermal N.sub.2 O-reoxidation (LRTNO) of Si.sub.3 N.sub.4 films. Si.sub.3 N.sub.4 film was deposited on the RTN-treated polysilicon by rapid-thermal chemical vapor deposition (RT-CVD) using SiH.sub.4 and NH.sub.3, followed by in situ low pressure rapid-thermal reoxidation in N.sub.2 O (LRTNO) or in O.sub.2 (LRTO) ambient. Results show that ultra thin (T.sub.ox,eq =.about.29 .ANG.) ON stacked film capacitors with LRTNO have excellent electrical properties, and reliability.

Abstract: A CMOS integrated circuit structure is disclosed having a patterned nitride passivation layer, wherein the nitride is patterned such that it does not overlie the thin gate oxide portions of one or more of the MOS devices. When protection against the effects of external radiation is desired, the thin gate oxide areas of the PMOS devices are left uncovered by the patterned nitride passivation layer. When protection is desired against the effects of internally generated "hot electrons", the thin gate oxide areas of the NMOS devices are left uncovered by the patterned nitride passivation layer.

Abstract: A resin molded type semiconductor device has a metallic guard ring that is formed to cover the peripheral edge of the surface of a tetragonal semiconductor substrate. In order to prevent a passivation film on the guard ring from being cracked by stresses due to a resin mold package concentrating in the four corners of the semiconductor substrate, slits or rows of small holes are formed in the corner portions of the guard ring.

Abstract: Reflective notching of a photoresist pattern (20), generated over reflective materials on a semiconductor substrate (12), is minimized by using an anti-reflective layer (20) of silicon-rich silicon nitride. The layer of silicon-rich silicon nitride is formed over the reflective materials and a layer of photoresist is then formed over the silicon-rich silicon nitride. The photoresist layer is then photolithographically patterned to form an integrated circuit pattern (20). The silicon-rich silicon nitride layer has an absorptive index of greater than 0.25, which allows it to be used as an anti-reflective layer with photolithographic patterning systems having ultraviolet and deep ultraviolet exposure wavelengths.

Abstract: A thin film resistor on a semiconductor device may be laser trimmed while reducing the influence of film thickness of a passivation film formed on the thin film resistor. An underlying oxide film consisting of a BPSG film and a silicon oxide film is formed on an Si substrate. A silicon oxide film and a silicon nitride film are formed on the underlying film as a passivation film, and a silicon oxide film is formed on this assembly. The silicon oxide film contributes to controlling a variation of the laser energy absorption rate of a thin film resistor due to an uneven thickness of the silicon nitride film. Thus, it is possible to stabilize adjustment of the resistance value of the thin film resistor with a laser.

Abstract: In a semiconductor device having a passivation layer, the passivation layer includes a laminated configuration formed by a plurality of tight insulating layers and a plurality of coarse insulating layers alternating with the tight insulating layers.

Abstract: This invention discloses a semiconductor device comprising a semiconductor substrate, a first conducting layer formed on the surface of the semiconductor substrate, an insulating layer formed above the semiconductor substrate, the insulating layer having a contact hole reaching the first conducting layer to expose it, a second conducting layer formed on the insulating layer, the sidewall of the contact hole, and the first conducting layer, and an anti-oxidation layer formed on at least part of the surface of the second conducting layer.

Abstract: According to this invention, after a semiconductor nitride film is formed on the entire surface of a semiconductor memory device, the semiconductor nitride film on a memory cell portion is removed. After a semiconductor oxide-based film is formed as an interlayer insulator on the entire surface of the semiconductor memory device, the semiconductor oxide-based film on a peripheral circuit portion is removed using the semiconductor nitride film as a stopper. For this reason, a shallow contact hole is formed in the peripheral circuit portion, and highly reliable wiring can be obtained. In addition, since hydrogen can be supplied to a surface of a semiconductor substrate in the memory cell portion by hydrogen annealing, an interface state on the surface can be eliminated, and the data retention characteristics of the memory cells can be improved.

Abstract: A semiconductor device (8) has an insulating layer (16) overlying a semiconductor substrate (12). The insulating layer has a first opening that defines an aperture (18) extending from the insulating layer to the semiconductor substrate, and at least a first portion of a first conductive terminal (42) is disposed in the aperture. A second conductive terminal (52) has a second portion (28) disposed in the aperture. The second portion of the second conductive terminal is separated from the first conductive terminal by a composite dielectric layer including a nitride layer (32) and an oxide layer (30). In one approach, the oxide layer is formed by the oxidation of the second portion of the second conductive terminal.

Abstract: A method is provided for forming an improved poly-buffered LOCOS process by forming a pad oxide layer over a substrate. A first nitride layer is formed over the pad oxide layer and a polysilicon layer is formed over the first nitride layer. A second nitride layer is formed over the polysilicon layer. An opening is etched through the second nitride layer, the polysilicon layer, the first nitride layer and the pad oxide layer to expose a portion of the underlying substrate. A field oxide region is then formed in the opening.

Abstract: A tunnel insulating film is formed on a main surface of a silicon substrate. A floating gate electrode is formed on the tunnel insulating film. A nitride layer formed of a material of the floating gate electrode is formed in the vicinity of an interface between the floating gate electrode and the tunnel insulating film located in a tunnel region A. Therefore, the write/erase characteristics of a non-volatile semiconductor memory device can be improved without decreasing the driving capability of a memory transistor at lower voltages.

Abstract: A semiconductor device and method of manufacturing the same includes the steps of forming silicon nitride films including much silicon than a stoichiometric silicon nitride (Si.sub.3 N.sub.4) and which will be an anti-reflection film, forming a resist film on the plasma silicon nitride films and, and concurrently patterning plasma silicon nitride films and conductive layers and using the resist film as a mask. As a result, high integration of the semiconductor device can be attained.

Abstract: In a semiconductor device according to this invention, a first insulating film formed on only a pattern formation conductive film on a semiconductor substrate and having a reflectance which is 25% or more and periodically changes in accordance with a change in film thickness of the first insulating film is formed on the semiconductor substrate. A second insulating film having a reflectance which is 25% or more and periodically changes in accordance with a change in film thickness and having a refractive index different from that of the first insulating film is formed on only the first insulating film. A total reflectance of the first and second insulating films is less than 25%. A photosensitive film is formed on the second insulating film and exposed through a reticle to form a predetermined pattern. Etching is performed using the photosensitive film having this pattern to form a conductive pattern.

Abstract: A semiconductor device of this invention includes an N-type semiconductor region functioning as a collector of a bipolar transistor, a silicon dioxide film doped with boron and formed in contact with the surface of the N-type semiconductor region, a P-type semiconductor region formed in contact with the silicon dioxide film doped with boron in the N-type semiconductor region and functioning as a base of the bipolar transistor, and an N-type semiconductor region formed in the P-type semiconductor region and functioning as an emitter of the bipolar transistor.

Abstract: A device protecting film having a UV transmissible SiN film, wherein the film is formed by a plasma CVD process in such a manner that a composition ratio Si/N falls within the range of 0.75 to 0.87, a Si--H bond concentration Z (cm.sup.-3) in the SiN film has a value near the value Z expressed by the following formula in accordance with a value X of Si/N:Z=1.58.times.10.sup.22 X-9.94.times.10.sup.21and, at the same time, a hydrogen bond concentration Y (cm.sup.-3) determining the Si--H bond concentration has a value near the value Y expressed by the following formula in accordance with X:Y=1.01.times.10.sup.22 X+0.54.times.10.sup.22The resulting SiN film transmits ultraviolet rays having a wavelength of 254 nm, reduces a stress inside the film, and has high moisture resistance.

Abstract: A photo sensor comprises a semiconductor substrate, a bipolar photo transistor having an emitter region, a base region and a collector region which is formed in the surface region of the semiconductor substrate, a silicon dioxide formed on the bipolar phototransistor, and a film having a smaller diffusion coefficient of hydrogen than the silicon dioxide formed all over the silicon dioxide.

Abstract: An improved EEPROM cell structure is disclosed which provides protection against external detection of data stored within the cell. One or more cavities filled with a high etching film and extending in a substantially vertical direction are provided in a region adjacent to an end of the floating gate such that during an attempted deprocessing of the cell using an etching process, the etchant will rapidly diffuse through these cavities and expose the floating gate via these cavities before exposing and removing the control gate via the insulating layers overlapping the control gate. Any charge once present on the floating gate will dissipate before the control gate can be removed, thereby making it impossible to read data stored within the cell.

Abstract: In a thin-film insulated gate type field effect transistor having a metal gate in which the surface of the gate electrode is subjected to anodic oxidation, a silicon nitride film is provided so as to be interposed between the gate eiectrode and the gate insulating film to prevent invasion of movable ions into a channel, and also to prevent the breakdown of the gate insulating film due to a potential difference between the gate electrode and the channel region. By coating a specific portion of the gate eiectrode with metal material such as chrome or the like for the anodic oxidation, and then removing only the metal material such as chrome or the like together with the anodic oxide of the metal material such as chrome or the like, an exposed portion of metal gate (e.g. aluminum) is formed, and an upper wiring is connected to the exposed portion.

Abstract: A semiconductor memory device of the present invention includes a memory cell comprising two transfer transistors and two driver transistors in which a nitride film is covered only on these driver transistor areas. The nitride film is formed over source and drain regions and a gate electrode of the driver transistor.

Abstract: Embodiments according to the present invention provide tamper resistant structures which make it more difficult to reverse engineer integrated circuits. In one embodiment, a tamper resistant structure on a passivation layer leaves portions of the passivation layer exposed. Mechanical or chemical removal of the tamper resistant structure damages exposed portions of the passivation layer and makes reverse engineering difficult. Other embodiments of the tamper resistant structure include patterned and unpatterned structures containing hard materials, chemically resistant materials, amalgams, fibrous materials, and/or meshes attached to a passivation layer. Tamper resistant structures can also be provided between layers of the active circuitry.

Abstract: A nonvolatile storage element of a single-layer gate type structure is arranged so that a floating gate is formed of a conductive layer which partly overlaps with a control gate, formed of a diffused layer, and is provided with a barrier layer covering a part of or the whole surface of the floating gate. Nonvolatile storage elements characterized as such are used for redundancy control of defects or change of functions.

Abstract: A plastic package type semiconductor device is composed of a rolled metal substrate made of copper or copper alloy and an insulating film formed on the surface of the substrate. The film may be a single-layer film made of silicon oxynitride or a composite film formed by laminating a silicon oxide layer and a silicon oxynitride layer (or a silicon nitride layer). A semiconductor element is mounted on the film or on the exposed surface of the substrate. Other passive elements are provided on the film. After connecting these elements with bonding wires, the entire device is sealed in a resin molding. This device is thus free of cracks due to difference in thermal expansion between the film and the substrate, or peeling due to moisture absorption.

Abstract: A memory coil section, formed on a semiconductor substrate and including a floating gate and a control gate, for storing a charge in a non-volatile semiconductor device is covered with a silicon nitride layer. The periphery of a contact hole for allowing contact between a wiring layer and the substrate is also covered with a silicon nitride layer.

Abstract: A semiconductor device has a substrate and a trench formed therein, the semiconductor device including a dielectric formed on the surface of the trench, a first amorphus silicon film formed on the dielectric film, a dopant film, a second amorphus silicon film, and a capping film formed between the dopant film and one of the first and second amorphus silicon films, the dopant film being formed between the other of the first and second amorphus silicon films and the capping film. The capping film is formed from one of silicon oxide and silicon nitride.

Abstract: A photosensor includes a substrate; a photoconductive layer formed on the substrate; a pair of electrodes mounted on and electrically connected to the photoconductive layer; a light reception portion formed between the electrodes; and a protective layer formed on the light reception portion; wherein an organic silicon film with a small content of metal ion is formed at least at the uppermost portion of the protective layer.

Abstract: An SOI-type semiconductor device in which electrical elements formed on one semiconductor substrate are isolated from each other by an insulating film and a shield layer, to ensure a stable operation of the electrical elements against electrical noise etc., and at the same time, a stress relief film is formed between the insulating film and the shield layer to ensure that an SOI layer is stabilized by being free from crystal defects. A process for producing same is also disclosed.

Abstract: A thin-film transistor (3, 5a, 5b and 5c) is covered with a first silicon nitride film (9) formed by an LPCVD method. A first silicon oxide film (6) is formed on the first silicon nitride film (9). A second silicon nitride film (7), i.e., passivation film which is formed by a plasma CVD method is provided on the first silicon oxide film (6). In addition, the thin-film transistor includes a semiconductor layer covering a gate electrode. The semiconductor layer includes source, drain and active regions. The active region preferably includes a smaller amount of fluorine than the gate electrode.

Abstract: A MOS semiconductor device and a method of making the same are arranged to include a semiconductor substrate of a first conductivity type; a pair of impurity diffused layers of a second conductivity type different from the first conductivity type formed in the semiconductor substrate and mutually separated by a distance of 0.1 .mu.m or less; a gate insulating film including at least two layers of a silicon oxide film and a silicon nitride film and formed on a portion of the semiconductor substrate disposed between the pair of impurity diffused layers; and a gate electrode formed on the gate insulating film, wherein preferably the silicon nitride film has a thickness of 4.5 nm to 14.86 nm.

Abstract: A semiconductor device has a conductive interconnection layer formed on a semiconductor substrate covered with a protection insulation film. A pad electrode opening is provided in the protection insulation film so that the surface of the conductive interconnection layer is exposed in the region which becomes the pad electrode. The conductive interconnection layer is electrically connected to an external terminal by a bonding wire. At least the surface of the protection insulation film in the proximity of the pad electrode opening and the inner peripheral side face of the pad electrode opening are covered with an elastic insulation film. The pad electrode opening is covered with the bonding wire. Since the conductive interconnection layer is not exposed at the pad electrode opening according to this structure, the phenomenon of moisture intruding into the pad electrode opening to corrode the conductive interconnection layer is prevented to improve reliability.

Abstract: A p type well is formed on a silicon substrate. An n.sup.- type region forming a photo diode is formed in the p type well. A p type region is also formed in the p type well. The p type region is used for surrounding the n type region which becomes a vertical CCD register part. Generally, such a structure is called a Hi-C structure. A P.sup.+ type region for controlling the potential height when transferring is formed between the photo diode and the vertical CCD register part. A P.sup.+ type region is formed for electrical separation. A P.sup.++ type region is formed on the surface of a silicon substrate of the photo diode. On the silicon substrate, a gate oxide film is grown. A silicon nitride film is grown in a specified region on the gate oxide film. On the silicon nitride film, a polysilicon electrode which is a conductive electrode, acting as a driving electrode, is formed. On the surface of the polysilicon electrode, a polysilicon oxide film is grown by thermal oxidation.

Abstract: A semiconductor device having a capacitor of a large capacitance in spite of its small area, is composed of a first insulating film formed on a semiconductor substrate, a first polysilicon film, a second insulating film and a second polysilicon film which are formed in that order on the first insulating film. The second polysilicon film is connected to the semiconductor substrate by means of a metal film to function as one electrode while the first polysilicon film functions as the other electrode. The first and second insulating film are each made of a dielectric material.

Abstract: A process for forming a thin film on a surface of a semiconductor device. The process involves formation of a silicon dioxide film by plasma enhanced thermal oxidation, employing a mixture of ozone and oxygen which are generated separately from the reactor chamber in a volume ratio of about 1-10/1, preferably about 5-7/1, at a temperature generally below 440.degree. C., preferably about 350.degree.-400.degree. C. The process is used to form sidewall oxide spacers on polysilicon gates for field effect transistors. A relatively fast oxidation rate is achieved at a temperature significantly below that employed in conventional oxidation processes, and this serves to reduce dopant diffusion from the polysilicon. In addition, the resulting film demonstrates low stress with good conformal step coverage of the polysilicon gates. Another use of the process is to grow thin gate oxides and oxide-nitride-oxide with a thickness of less than 100 .ANG..

Abstract: An EEPROM device capable of operating with a single low-voltage power supply includes a control gate electrode (30) and a select gate electrode (14) overlying separate portions of a channel region (32). Electrical charge is stored in an ONO layer (20) overlying a portion of the channel region (32) and separating the control gate electrode (30) from the channel region (32). The memory device is programmed using source-side injection, where electrons traverse the channel region (32) and are injected into trapping sites (34) located within the silicon nitride layer (24) of the ONO layer (20). To provide the necessary field gradient within the channel region (32), the control gate electrode (30) is spaced apart from the source region (16) by the select gate electrode (14). In either of two embodiments, two layers of polysilicon are used to form the select gate electrode (14) and the control gate electrode (30). The second layer of polysilicon is formed as a sidewall spacer on the first layer of polysilicon.

Abstract: A semiconductor device of this invention includes an N-type semiconductor region functioning as a collector of a bipolar transistor, a silicon dioxide film doped with boron and formed in contact with the surface of the N-type semiconductor region, a P-type semiconductor region formed in contact with the silicon dioxide film doped with boron in the N-type semiconductor region and functioning as a base of the bipolar transistor, and an N-type semiconductor region formed in the P-type semiconductor region and functioning as an emitter of the bipolar transistor.

Abstract: A new method of forming the dielectric layer of an integrated circuit is described. A thick insulating layer is formed over semiconductor device structures in and on a semiconductor substrate. A first metal layer is deposited over the thick insulating layer. The first metal layer is etched using conventional photolithography and etching techniques to form the desired metal pattern on the surface of the thick insulating layer. The intermetal dielectric layer is formed by first covering the patterned first metal layer with a layer of silicon oxide. The silicon oxide layer is covered with a layer of spin-on-glass material which is baked and cured. A second layer of silicon oxide completes the intermetal dielectric layer. Via openings are formed through the intermetal dielectric layer to the underlying patterned first metal layer.

Abstract: A semiconductor device wherein a coating film which is made of a polyimide resin or a polyimide isoindoloquinazolinedione resin and which is at least 10 .mu.m thick is disposed on at least an active region of a semiconductor substrate, and the resultant semiconductor substrate is encapsulated in a ceramic package. The semiconductor device has troubles relieved conspicuously, the troubles being ascribable to alpha-rays which come flying from impurities contained in the material of the package.

Abstract: A non-volatile semiconductor memory providing a semiconductor substrate including source and drain diffusion regions and a gate electrode, and an insulating film which is at least provided on the semiconductor substrate just below the gate electrode and has a smaller dielectric breakdown strength on the source side than on the drain side, wherein the insulating film is comprised of a laminated film having a multilayer structure on the drain side and a single-layer film or multilayer film which is broken down at a smaller voltage on the source side than on the drain side, and a predetermined voltage is applied to break down the single-layer film or multilayer film on the source side, so that data can electrically be written only once.

Abstract: A thin film transistor is used as a load transistor in a memory cell in a SRAM. A load thin film transistor is arranged on an interlayer insulating layer on the surface of a silicon substrate. A silicon layer in which source/drain regions of the thin film transistor are formed is covered with an oxidation preventing film. An interlayer insulating layer which is to be subject to high temperature reflow processing is formed on the surface of the oxidation preventing film. The oxidation preventing film is formed of polycrystalline silicon, amorphous silicon, silicon nitride, or the like and formed on the silicon layer in the thin film transistor directly or through an insulating layer to cover the surface of the silicon layer.