Abstract: A method and apparatus for depositing a low dielectric constant film by reaction of an organo silane compound and an oxidizing gas at a low RF power level from 20-200 W. The oxidized organo silane film has excellent barrier properties for use as a liner or cap layer adjacent other dielectric layers. The oxidized organo silane film can also be used as an etch stop or an intermetal dielectric layer for fabricating dual damascene structures. The oxidized organo silane films also provide excellent adhesion between different dielectric layers. A preferred oxidized organo silane film is produced by reaction of methyl silane, CH.sub.3 SiH.sub.3, and nitrous oxide, N.sub.2 O, at a pulsed RF power level from 50-200 W during 10-30% of the duty cycle.

Abstract: An integrated circuit comprises a dielectric layer disposed outwardly from a semiconductor substrate, the dielectric layer comprising at least one cavity having sidewalls extending from an outer surface of the dielectric layer inwardly toward the substrate. The integrated circuit further comprises a contaminant resistant barrier disposed outwardly from at least the sidewalls of the cavity in the dielectric layer.

Abstract: A semiconductor device with first and second types of devices formed in a semiconductor substrate with a barrier layer formed over the surface of the semiconductor device including over the first and second types of devices with the barrier layer removed from over the first type of device. The first type of device is a positive charge sensitive device such as a nonvolatile memory device. The semiconductor device has a hydrogen getter layer formed under the barrier layer.

Abstract: In the manufacture of a field effect transistor which can improve the breakdown voltage between a gate and a drain and can also prevent a gate lag, an oxide film is formed or wet cleaning is carried out over the semiconductor surface of an inter-source-gate region while a nitride film is formed or dry cleaning is carried out over the semiconductor surface of an inter-gate-drain region, in order that surface traps in the semiconductor surface of the inter-gate-drain region, which is not covered with electrode metal, is greater in number than those in the semiconductor surface of the inter-source-gate region.

Abstract: A technique for forming integrated circuit device contacts includes the formation of nitride spacers along side gate electrodes for LDD definition. In addition, a nitride cap layer is formed over the gate electrodes. When a contact opening is formed through the interlevel oxide dielectric, the nitride cap and sidewall spacers protect the gate electrode from damage and shorting. A highly doped poly plug is formed in the opening to make contact to the underlying substrate. Metalization is formed over the poly plug in the usual manner.

Abstract: The present invention intends to form multilayer interconnects without deteriorating the advantage of an organosiloxane film (an interlayer dielectric), i.e., the low dielectric constant. According to the present invention, an organosiloxane film, a silicon nitride film, an inorganic SOG film, and a photoresist pattern are formed on a first metal layer, in series. The inorganic SOG film is then etched with use of the photoresist pattern as a mask to transfer the photoresist pattern to the inorganic SOG film. The photoresist pattern is then removed by oxygen plasma treatment with use of the silicon nitride film as a protection mask for protecting the organosiloxane film. Subsequently thereto, the silicon nitride film and the organosiloxane film are etched with use of the inorganic SOG film to form a contact hole reaching the first metal layer. After removing the inorganic SOG film, a second metal layer is formed to contact with the first metal layer through the contact hole.

Abstract: An insulating layer in a semiconductor device and a process for forming the insulating layer is described. The insulating layer comprises of a nitride layer over the substrate having a residual stress of between -8.times.10.sup.9 dynes/cm.sup.-2 and -3.times.10.sup.10 dynes/cm.sup.-2. The insulating layer can further comprise a doped oxide layer under the nitride layer and can further comprise an interlevel dielectric layer over the nitride layer. Moreover, the nitride layer can be formed by bringing the temperature in a chemical vapor deposition reactor to below 550 degrees Celsius, placing the substrate into the reactor at the temperature, and forming the nitride layer on the substrate. Alternatively, the nitride layer can be formed by pushing the substrate into a chemical vapor deposition reactor at a speed greater than 300 millimeters per minute, and forming the nitride layer on the substrate.

Abstract: An integrated circuit (IC) is provided. The IC includes a silicon substrate and a dielectric layer formed upon the silicon substrate. The IC further includes a terminal metal layer (TML) formed upon the dielectric layer. The dielectric layer and the TML form a die active area. The TML has formed therein a plurality of spaced locking structures. The plurality of space locking structures are electrically isolated therebetween. Each locking structure is formed outside the die active area. The IC further includes a passivation layer adhering to the locking structures.

Abstract: A semiconductor structure comprises a silicon substrate of a first conductivity type including wells of a second conductivity type disposed on a surface thereof and a dielectric layer including silicon nitride disposed on the surface. The dielectric layer includes openings at least partially disposed on the p-wells. The dielectric layer also includes a top latter comprising silicon dioxide having a thickness of less than ten angstroms. Trenches having a depth comparable to or greater than a depth of the wells extend into the substrate surface within the openings. A nonconductive material is disposed within the trenches and has an upper surface that is substantially coplanar with the dielectric layer. Portions of the dielectric layer are used as gate dielectrics for transistors.

Abstract: A structure and method of fabrication of a semiconductor integrated circuit is described. A first patterned electrically conductive layer contains a low dielectric constant first insulating material such as organic polymer within the trenches of the pattern. A second insulating material such as a silicon dioxide or other insulating material having a greater mechanical strength and thermal conductivity and a higher dielectric constant than the first insulating material is formed over the first patterned electrically conductive layer. Vias within the second insulating material filled with electrically conductive plugs and a second patterned electrically conductive layer may be formed on the second insulating material. The structure can be repeated as many times as needed to form a completed integrated circuit.

Abstract: A semiconductor device with a multi-level insulator formed on a semiconductor substrate is provided, which enables to restraint of impurity atoms doped into a material contacted with the insulator from diffusing into the insulator. The multi-level structured insulator contains a first dielectric film formed on the substrate and a second dielectric film formed on the first dielectric film. The first dielectric film is thicker than the second dielectric film so that an interface of the first and second dielectric films exists at a level higher than the central level of the insulator. The first dielectric film is made of an oxide of a semiconductor constituting the substrate. The second dielectric film is made of a nitride or oxynitride of the semiconductor constituting the substrate. The insulator preferably contains only the first and second dielectric films to have a two-level structure.

Abstract: A semiconductor processing method is provided for making contact openings. It includes depositing several insulative layers and performing an anisotropic etch. One layer is a conformal oxide covering the contact area and adjacent structures. A second layer is a breadloafed oxide deposited over the contact area and adjacent structures. A third layer is a doped oxide deposited over the two lower layers. The anisotropic etch is performed through the oxide layers to the contact area located on a lower substrate. The etch is selectively more rapid in the third oxide than in the two other oxides. The breadloafed oxide provides additional protection and reduces the risk of etch-through to conductive structures adjacent the contact area. An alternate embodiment replaces the two lowest oxide layers by a breadloafed nitride layer. In this embodiment, the anisotropic etch is selectively more rapid in oxides than in nitrides.

Abstract: A etch stop layer for use in a silicon oxide dry fluorine etch process is made of silicon nitride with hydrogen incorporated in it either in the form of N--H bonds, O--H bonds, or entrapped free hydrogen. The etch stop layer is made by either increasing the NH.sub.3 flow, decreasing the SiH.sub.4 flow, decreasing the nitrogen flow, or all three, in a standard PECVD silicon nitride fabrication process. The etch stop can alternatively be made by pulsing the RF field in either a PECVD process or an LPCVD process.

Abstract: A semiconductor device includes a silicon substrate, a first insulating film, a barrier film, a contact hole, a protective film, a barrier metal, and an interconnection metal. A semiconductor element is formed on the silicon substrate. The first insulating film is formed on the silicon substrate. The barrier film is formed on the first insulating film to prevent moisture from externally entering. The contact hole is formed through the barrier film and the insulating film to a depth at which the silicon substrate is exposed. The protective film is formed on the side surface of the contact hole to protect the first insulating film against etching which is performed to remove a spontaneous oxide film formed on a surface of the silicon substrate which is exposed on a bottom surface of the contact hole. The barrier metal is continuously formed on at least the side and bottom surfaces of the contact hole and serves as a buffer conductor.

Abstract: A modified LOCOS isolation process for semiconductor devices is disclosed. First, a shielding layer is formed overlying a semiconductor substrate. The shielding layer is then patterned to form an opening that exposes a portion of the semiconductor substrate for forming a device isolation region. Next, oxygen ions are implanted with a tilt angle into the semiconductor substrate to form a doped region extending to the area under the margin of the shielding layer. A thermal oxidation process is then performed to form a field oxide layer on the semiconductor substrate. Since the oxidation rate of the area under the margin of the shielding layer is increased by the implanted oxygen ions, the bird's beak effect shown in conventional LOCOS process can be eliminated. After that, the shielding layer is removed to complete the fabricating process of this invention.

Abstract: There is disclosed a semiconductor device which includes a semiconductor substrate having an element region and source and drain regions, a gate dielectric film containing nitrogen formed in the element region of said semiconductor substrate, a gate electrode formed on the gate dielectric film, a first dielectric film formed adjacent to the gate electrode so as to define a side wall therefor, a second dielectric film formed so as to cover the gate electrode and the first dielectric film, the second dielectric film being doped with nitrogen, and a third dielectric film formed so as to cover the second dielectric film, the third dielectric film being formed of silicon nitride. A method for manufacturing such a semiconductor device is also described.

Abstract: A resin material having low dielectric constant is used as an inter-layer insulating film and its bottom surface is contacted with a silicon oxide film across the whole surface thereof. Thereby, the surface may be flattened and capacity produced between a thin film transistor and an pixel electrode may be reduced. Further, it allows to avoid a problem that impurity ions and moisture infiltrate into the lower surface of the resin material, thus degrading the reliability of whole semiconductor device.

Abstract: A semiconductor device comprising: a silicon nitride film formed on a semiconductor substrate having a first wiring layer; a first silicon oxide film formed on said silicon nitride film; and a second silicon oxide film formed on said first silicon oxide film by way of an atmospheric pressure CVD process using tetraethyl orthosilicate, siloxane, or disilazane as a source material.

Abstract: Inventive antireflective structures comprise a semiconductor substrate having hereon a combination of a plurality of layers that either that absorb reflected light or that dissipate reflected light into patterns and intensities that do not substantially alter photoresist material on the semiconductor substrate. The semiconductor substrate has formed thereon a feature having a width of less than about 0.25 microns. Antireflective structures contemplated include a first layer of polysilicon and first layer of silicon nitride material that is formed upon the first layer of polysilicon. The antireflective structure has the ability to scatter unabsorbed light into patterns and intensities that are substantially ineffective to alter photoresist material exposed to said patterns and intensities.

Abstract: On a transparent substrate, on which is positioned a gate electrode, a silicon nitride film and a silicon oxide film are formed as gate insulating films, and furthermore a polycrystalline silicon film is formed as a semiconductor film to become an active region. A stopper is positioned on the polycrystalline silicon film to correspond to a gate electrode, and a silicon oxide film, a silicon nitride film, and a silicon oxide film are formed as interlayer insulating film so as to cover the stopper. Contact holes are formed in the layer insulating film to correspond to a source region and a drain region, and a source electrode and a drain electrode are positioned through these contact holes.

Abstract: A semiconductor structure comprises a silicon substrate of a first conductivity type including wells of a second conductivity type disposed on a surface thereof and a dielectric layer including silicon nitride disposed on the surface. The dielectric layer includes openings at least partially disposed on the p-wells. The dielectric layer also includes a top layer comprising silicon dioxide having a thickness of less than ten angstroms. Trenches having a depth comparable to or greater than a depth of the wells extend into the substrate surface within the openings. A nonconductive material is disposed within the trenches and has an upper surface that is substantially coplanar with the dielectric layer. Portions of the dielectric layer are used as gate dielectrics for transistors.

Abstract: A thin film transistor of the present invention has an active layer including at least source, drain and channel regions formed on an insulating surface. A high resistivity region is formed between the channel region and each of the source and drain regions. A film capable of trapping positive charges therein is provided on at least the high resistivity region so that N-type conductivity is induced in the high resistivity region. Accordingly, the reliability of N-channel type TFT against hot electrons can be improved.

Abstract: A pair of source/drain regions are formed on a semiconductor substrate at a predetermined interval. A gate insulator film is formed on the semiconductor substrate between the source/drain regions of the pair. A gate electrode is formed on the gate insulator film. A film for covering the gate electrode and the source/drain regions has a low permeability against water and a hydroxide group, and has a thickness greater than 3 nm and less than 5 nm.

Abstract: A semiconductor device with the trench isolation structure is provided, in which the leakage current problem does not occur. This device is comprised of a semiconductor substrate, an isolation trench formed in a surface region of the substrate and filled with first and second isolation dielectrics, an interlayer dielectric layer formed on the surface region of the substrate to cover the isolation trench, and a conductive layer formed on the interlayer dielectric layer to be overlapped with the isolation trench. The interlayer dielectric layer has a contact hole located near the isolation trench. The contact hole is formed by etching. The conductive layer is contacted with and electrically connected to a region of the substrate through the contact hole of the interlayer dielectric layer. The first isolation dielectric serves as a primary insulator. The second isolation dielectric serves as a secondary insulator.

Abstract: In an active area on a semiconductor substrate is formed a MOS transistor including a gate insulating film, gate electrode, an insulating film formed on the entire surface of the substrate, a conductive side wall formed on the side surfaces of the gate electrode with the insulating film interposed therebetween, low concentration source/drain regions and high concentration source/drain regions. The high concentration drain region and the conductive side wall are electrically conducting to each other via a second interconnection within a second contact hole. In the usage of the MOS transistor, the conductive side wall is at the same potential as the drain voltage, thereby suppressing the degradation due to a hot carrier. In addition, since there is no need to provide an alignment margin between the second contact hole and the gate electrode, the area of the drain region is decreased.

Abstract: A structure of a bond pad to prevent probe pin contamination is disclosed herein a first conductor layer is formed on the substrate. A passivation layer including a titanium nitride layer, a silicon nitride layer, and a silicon oxide layer is formed on the first conductor layer. A photoresist layer is patterned on the passivation layer to define a contact hole, and then etching the passivation layer using the photoresist layer as a mask to form the contact hole. A second conductor layer serving as a top metal of bond pad harder than the first conductor layer is selectively deposited on the first conductor layer, and filled in the contact hole. The present invention can reduce a probe pin contamination so that extend the probe pin lifetime using this selective deposition technique to form the pond pad structure. Additionally, the structure can prevent the contact resistance between the probe pin head and the bond pad increasing, and reduce the probe pin overkill ratio.

Abstract: A tunnel oxide film is formed on the surface of a p-type silicon substrate, and a floating gate electrode made from a polysilicon film is formed on the surface of the tunnel oxide film. On the surface of the floating gate electrode, a control gate electrode is formed via an NON film formed by sequentially stacking a silicon nitride film, a silicon oxide film, and a silicon nitride film. A side oxide film is formed on the side surfaces of the floating gate electrode and the control gate electrode. Source and drain regions made from an n-type diffused layer are formed on the surfaces of element regions of the silicon substrate on the two sides of the floating gate electrodes.

Abstract: Inventive antireflective structures comprise a semiconductor substrate having thereon a combination of a plurality of layers that either that absorb reflected light or that dissipate reflected light into patterns and intensities that do not substantially alter photoresist material on the semiconductor substrate. The semiconductor substrate has formed thereon a feature having a width of less than about 0.25 microns. Antireflective structures contemplated include a first layer of polysilicon and first layer of silicon nitride material that is formed upon the first layer of polysilicon. The antireflective structure has the ability to scatter unabsorbed light into patterns and intensities that are substantially ineffective to alter photoresist material exposed to said patterns and intensities.

Abstract: Disclosed is a method for making a passivation coated semiconductor structure. The method includes providing a substrate having a metallization line patterned over the substrate. The metallization line defining at least one interconnect feature having a first thickness, and depositing a first silicon nitride barrier layer having a second thickness over the substrate and the metallization line. The method further including applying an oxide material over the first silicon nitride barrier layer that overlies the substrate and the metallization line. The oxide application includes a deposition component and a sputtering component, and the sputtering component is configured to remove at least a part of an edge of the first silicon nitride layer. The edge is defined by the metallization line underlying the first silicon nitride layer.

Abstract: A method for preparing an SRAM or DRAM structure on a substrate with an oppositely doped well therein, a field oxide region extending above and between the well and the substrate, first and second N-MOS transistors on the silicon substrate, and a P-MOS transistor on the silicon well. The source and drain regions of each of the P-MOS transistor and the first and second N-MOS transistors each have a polysilicon plug making contact therewith. Each polysilicon plug is isolated one from another by nitride spacers, has the same doping as the region with which it makes contact, and is self-aligned to the nitride spacers lining the passage of the polysilicon plugs to their respective contacts on either the silicon substrate or the silicon well. The self-aligned nature of the polysilicon plugs is due to the nitride spacers formed by etchant selectivities and photoresist masks.

Abstract: An LSI semiconductor device having a device isolation structure and a method of fabricating the isolation structure are presented. The device is a buried-type field-shielding device which is fabricated in non-active regions of the LSI circuit, and includes field-shield insulator film formed on the interior walls of trench cavities formed on the substrate and the field-shield electrodes buried within the trench cavity. Unlike the conventional buried-type isolation devices, the top surface of present isolation structure is level with the upper surface of the substrate. Therefore, this device structure utilizes the interior space of the substrate rather than the surface area of the substrate as in the conventional field-shield isolation structure.

Abstract: Described is a structure and process for forming a hermetically sealed chip. This hermetically sealed chip will greatly simplify packaging requirements and eventually lead to the realization of a "packageless chip". The hermetic sealing is composed of two parts, an extremely thin passivation layer which is deposited over the entire chip top and side surfaces and a passivation layer which is deposited over the bonding pad surface. Preferably, SiN is deposited as a chip surface passivation layer and Ni is selectively deposited as a metal passivation layer. The extremely thin nitride layer will minimize the stress and the amount of hydrogen in the SiN film and minimize deleterious effects upon device performance caused by stress and hydrogen. The thickness of the metal passivation layer may be the same as that of the dielectric layer so as to give a planar surface or it may be thick enough so as to give a protruding metal passivation bump.

Abstract: A semiconductor wafer having an impurity diffusion layer formed in an inner surface of a trench is cleaned. The semiconductor wafer is inserted into a furnace, and NH.sub.3 gas is introduced into the furnace in the low-pressure condition to create an atmosphere in which the temperature is set at 800.degree. C. to 1200.degree. C. and the partial pressures of H.sub.2 O and O.sub.2 are set at 1.times.10.sup.-4 Torr or less. A natural oxide film formed on the inner surface of the trench is removed, and substantially at the same time, a thermal nitride film is formed on the impurity diffusion layer. Then, a CVD silicon nitride film is formed on the thermal nitride film without exposing the thermal nitride film to the outside air in the same furnace. Next, a silicon oxide film is formed on the CVD nitride film. As a result, a composite insulative film formed of the thermal nitride film, CVD silicon nitride film and silicon oxide film is obtained.

Abstract: A semiconductor device in which dry etching properties are rendered compatible with satisfactory anti-reflection characteristics in far-infrared lithography the semiconductor device has a semiconductor substrate and an electrode and wire pattern on the substrate. The semiconductor device also has an anti-reflective layer on the substrate which presents a variation in the composition of a constituent element along the film thickness over the semiconductor substrate. The anti-reflective layer is selected from the group consisting of SiO.sub.x, SiN.sub.x and Si.sub.x O.sub.y N.sub.z.

Abstract: Methods for depositing a nitride layer on a surface of an integrated circuit wafer for protecting against over etching during subsequent etching of overlying layers. A first nitride deposition method utilizes a chemical vapor deposition process having a variable ammonia flow rate. The ammonia flow rate is decreased during the chemical vapor deposition process. A second nitride deposition method produces an oxygen rich etch stop film on the surface of the nitride layer. The method comprises the application of an oxygen/argon plasma treatment to the surface of the nitride layer in a reactive ion etching process. A third nitride deposition method produces an oxygen rich etch stop film on the surface of the nitride layer. The method comprises the application of a nitrous oxide plasma treatment to the surface of the nitride layer in a chemical vapor deposition chamber.

Abstract: On a surface of a silicon substrate having conductivity type of p-type, a field oxide layer and a gate oxide layer to be an isolation region are formed. A gate electrode is formed via the gate oxide layer. A surface silicon oxide layer is formed on a surface of the gate electrode. An etch stop layer is formed at a region outside of the surface silicon oxide layer, which etch stop layer is formed of a material different from a material of the gate oxide layer. Also, on the upper surface of the etch stop layer, an interlayer insulation layer is formed. Then, on the surface of the silicon substrate in the vicinity of the end of the gate electrode, an n.sup.- -diffusion layer is formed. In a region outside of the n.sup.- -diffusion layer, an n.sup.+ -diffusion layer is formed. On the other hand, between the upper surface of the n.sup.- -diffusion layer and the n.sup.

Abstract: A display device including a liquid crystal held between an active matrix substrate made up by arranging thin film transistors thereon, each using polycrystalline silicon as a semiconductor layer, in one-to-one relation to intersections between a plurality of signal lines and a plurality of scan lines, and an opposite substrate opposed to the active matrix substrate, wherein the active matrix substrate includes a film having tensile stress disposed at least below or above the semiconductor layer.

Abstract: A semiconductor device includes an interlevel film constituted by a first dielectrics film containing dangling bonds and a bonded group of Si and hydrogen, and a second dielectrics film formed on the first dielectrics film.

Abstract: A method is provided for forming an improved device dielectric of a semiconductor integrated circuit, and an integrated circuit formed according to the same. For scaling geometries for use in the submicron regime, a composite dielectric layer used as a device dielectric is formed over a plurality of active areas adjacent to a field oxide region. The composite dielectric layer is formed before the field oxide region is formed and comprises a non-porous silicon nitride layer. The non-porous silicon nitride layer preferably comprises a thin deposited silicon nitride layer overlying a thin nitridized region of the substrate. The silicon nitride layer is partially oxidized during the subsequent formation of a field oxide region between the plurality of active areas. An oxide layer may be formed over the silicon nitride layer before the formation of the field oxide region which will then be densified during the field oxide formation.

Abstract: A method for forming a contact opening is described and which includes providing a node location to which electrical connection is to be made; forming a conductive line adjacent the node location, the conductive line having a conductive top and sidewall surfaces; forming electrically insulative oxide in covering relation relative to the top surface of the conductive line; forming electrically insulative nitride sidewall spacers over the conductive sidewall surfaces, the nitride sidewall spacers projecting outwardly of the conductive line top conductive surface, the electrically insulative oxide positioned between the nitride sidewall spacers; forming an electrically insulative layer outwardly of the conductive line, and the node location; and etching a contact opening to the node location or the top surface through the electrically insulative layer substantially selective relative to the nitride sidewall spacers.

Abstract: An MOS transistor has a gate electrode is electrically conductively connected to an exposed contact area (pad). The contact area is electrochemically corrosion-resistant and is dimensioned for connection to a living cell. The surface topology is relatively flat and the surface, with the exception of the contact area, is protected with a dielectric passivation layer.

Abstract: A method is provided for forming a planar transistor of a semiconductor integrated circuit, and an integrated circuit formed according to the same. A transistor encapsulated in a dielectric is formed over a substrate. First source and drain regions are formed in the substrate adjacent the transistor. Conductive raised second source and drain regions are formed which overly exposed portions of the first substrate source and drain regions adjacent the transistor. The raised second source and drain regions are formed such that an upper surface of the raised second source and drain regions are substantially planar with an upper surface of the transistor. The dielectric encapsulating the transistor electrically isolates the transistor from the raised second source and drain regions.

Abstract: The invention relates to a semiconductor device with a substrate, with at least one isolation layer with at least one window, with a passivation layer scheme lying on the isolation layer and a metallization lying on the passivation layer scheme, the latter comprising at least two dielectric layers of which the first dielectric layer covers the isolation layer with its edges as well as the substrate in an outer edge zone of the window, and of which the second dielectric layer covers the first dielectric layer also over the edge of the isolation layer and in a portion of the outer region of the window.

Abstract: In an integrated circuit, gate electrode stack of which is subjected to self-alignment processes, the sheet resistance is lowered by including a tungsten layer 15. The tungsten layer 14 is protected by a sidewall material 21 of SiN.sub.x or SiO.sub.2 after an etching step which did not extend to the substrate 11. During a subsequent etching step in which the stack extends to the substrate 11, the sidewall material 31 acts as a hard mask protecting the upper portion of the stack. After the lower portion of the stack is protected by a re-oxidation layer 41, the entire stack can be processed further without deterioration of the sheet resistance of the tungsten layer 15.

Abstract: A method for fabricating a semiconductor device comprising fabricating a sacrificial wafer having a substrate wafer which includes a diffused layer and one or two epi layers. The sacrificial wafer is fusion bonded to a separately fabricated carrier/handle wafer having a layer of oxide on its surface, to form a composite wafer. Selective regions of the composite wafer are anodized and oxidized to form a plurality of wells separated from each other by a dielectric insulating layer. Next, N- epi regions above P+ epi regions are removed or alternatively, P+ diffused layers are removed from above an N- epi layer in selected regions. Finally, P- or N- single crystal silicon is grown back to the removed regions, depending on how the regions were removed. If N- single crystal is grown back to the removed regions, a high temperature drive-in is employed to finish the processing. The final structure contains N and P regions which are dielectrically isolated from each other and from the substrate.

Abstract: Described is a structure and process for forming a hermetically sealed chip. This hermetically sealed chip will greatly simplify packaging requirements and eventually lead to the realization of a "packageless chip". The hermetic sealing is composed of two parts, an extremely thin passivation layer which is deposited over the entire chip top and side surfaces and a passivation layer which is deposited over the bonding pad surface. Preferably, SiN is deposited as a chip surface passivation layer and Ni is selectively deposited as a metal passivation layer. The extremely thin nitride layer will minimize the stress and the amount of hydrogen in the SiN film and minimize deleterious effects upon device performance caused by stress and hydrogen. The thickness of the metal passivation layer may be the same as that of the dielectric layer so as to give a planar surface or it may be thick enough so as to give a protruding metal passivation bump.

Abstract: A method is provided for forming a planar surface of a semiconductor integrated circuit, and an integrated circuit formed according to the same. A gate oxide layer is formed over a silicon substrate. A first polysilicon layer is formed over the gate oxide layer and a nitride layer is formed over the first polysilicon layer. The first polysilicon and nitride layers are then patterned and etched to form an opening which exposes a portion of the gate oxide layer. An oxidation step is then performed to form a field oxide region in the opening. The field oxide region is formed to a thickness having an upper surface substantially planar with an upper surface of the first polysilicon layer. The nitride layer is then removed and the gate oxide and first polysilicon layers are patterned and etched to form a gate electrode and an interconnect.

Abstract: A method for forming interconnections for semiconductor fabrication and semiconductor devices have such interconnections are described. A first patterned dielectric layer is formed over a semiconductor substrate and has a first opening filed with conductive material. Another patterned dielectric layer is formed over the first dielectric layer and has a second opening over at least a portion of the conductive material. The first patterned dielectric layer may serve as an etch-stop in patterning the other patterned dielectric layer. Also, a dielectric etch-stop layer may be formed over the first patterned dielectric layer and over the conductive material before the other patterned dielectric layer has been formed. This dielectric etch-stop layer may serve as an etch-stop in patterning the other patterned dielectric layer. The second opening exposes a portion of the dielectric etch-stop layer. The exposed portion of the dielectric etch-stop layer is removed. The second opening is filled with conductive material.

Abstract: An integrated circuit includes a conductive fusible link that may be blown by heating with laser irradiation, The integrate circuit comprises a silicon substrate; a first insulating layer; a fusible link on the first layer; a second insulating layer overlying the first layer and the fusible link; an opening through the second layer exposing the fuse; and a protective layer over the surfaces of the opening. A laser beam is irradiated through the opening and the protective layer to melt the fusible link. The protective layer is highly transparent to a laser beam and does not interfere with the laser melting (trimming) operation.

Abstract: This invention discloses a semiconductor device comprising a semiconductor substrate, a first conducting layer formed on the surface of the semiconductor substrate, an insulating layer formed above the semiconductor substrate, the insulating layer having a contact hole reaching the first conducting layer to expose it, a second conducting layer formed on the insulating layer, the sidewall of the contact hole, and the first conducting layer, and an anti-oxidation layer formed on at least part of the surface of the second conducting layer.