Abstract: A street lamp intelligent measurement and control device includes an MCU chip, and an electrical parameter measuring circuit, an NB-IoT communication circuit, a dimming circuit and a switching control circuit respectively connected to the MCU chip. The electrical parameter measuring circuit determines electrical parameter data and electrical energy data of a street lamp load, and transmits the electrical parameter data and the electrical energy data to the MCU chip. The MCU chip actively uploads the electrical parameter data and/or the electrical energy data to a remote control center according to a preset time interval, receives a controlling instruction from the remote control center, and sends out a switching signal and/or a dimming signal according to the controlling instruction. The switching control circuit controls an on-off of the street lamp load according to the switching signal sent by the MCU chip.

Abstract: A semiconductor package according to an embodiment of the present invention Includes: a lead frame comprising a pad and a lead spaced apart from the pad by a regular interval; a semiconductor chip adhered on the pad; and a clip structure electrically connecting the semiconductor chip and the lead, wherein an one end of the clip structure connected to the semiconductor chip inclines with respect to upper surfaces of chip pads of the semiconductor chip and is adhered to the upper surfaces of the chip pads of the semiconductor chip. A semiconductor package according to another embodiment of the present invention includes: a semiconductor chip comprising one or more chip pads; one or more leads electrically connected to the chip pads; and a sealing member covering the semiconductor chip, wherein an one end of the lead inclines with respect to one surface of the chip pad and is adhered to the chip pad and an other end of the lead is exposed to the outside of the sealing member.

Abstract: A metal oxide varistor (MOV) device including a MOV chip having first and second electrodes disposed on opposing side thereof, a first lead frame portion including a first contact tab electrically connected to the first electrode and a first lead contiguous with the first contact tab and extending away from the MOV chip, a second lead frame portion including a second contact tab electrically connected to the second electrode and a second lead contiguous with the second contact tab and extending away from the MOV chip, and a device body encasing the MOV chip, the first contact tab, the second contact tab, and portions of the first and second leads, wherein the first and second leads extend out of the device body and are bent into flat abutment with a bottom surface of the device body.

Abstract: An apparatus, system and method capable of providing a high precision connection between a plurality of pins of a C form factor pluggable (CFP) and a connection pad of a printed circuit board (PCB). The apparatus, system and method include: a connector mask suitable to receive therein a body of the CFP; a ruler suitable to receive therein the connector mask, and sized and shaped for direct physical associated with the PCB about the connection pad; and an adjustment mechanism at least partially passing through the ruler for contacting at least the connector mask and capable of adjusting the position of the pins in relation to the connection pad.

Abstract: A dual in-line package (DIP) light emitting diode (LED) device includes a molded member, a positive lead passing through and fixed to the molded member, the positive lead comprising an upper end and lower end, a negative lead passing through and fixed to the molded member, the negative lead comprising an upper end and lower end, and at least one LED body connected to the top ends of the positive lead and the negative lead. The lower ends of the positive lead and the negative lead are flush with each other. The top end of the positive lead is higher than the top end of the negative lead. The positive lead and the negative lead are both bent at the top ends thereof.

Abstract: A manufacturing method of a sensor chip package structure is provided. In the manufacturing method, a wafer including a plurality of sensor chips is provided, and each sensor chip has an active region and defines a pre-thinned region thereon. Each pre-thinned region is located at one side of the active region and covers a boundary line of each sensor chip. The pre-thinned region of each sensor chip is etched to form a concave portion. A redistribution layer is formed on the wafer. Subsequently, the wafer is cut to separate the sensor chips from one another, and each separated sensor chip has a wiring layer extending from the active region along a sidewall surface to a bottom surface of the concave portion. The separated sensor chips are respectively mounted on a plurality of substrates, and the active region is electrically connected to the substrate through the wiring layer.

Abstract: A power semiconductor module includes a substrate with a metallization layer; at least one power semiconductor chip bonded to the substrate; and a mold encapsulation partially encapsulating the semiconductor chip and the substrate; the mold encapsulation includes at least one window exposing a terminal area of the metallization layer; and a border part of the mold encapsulation between the window and a border of the substrate has a height over the substrate smaller than a maximal height of a central part of the mold encapsulation.

Abstract: A package for a semiconductor device includes: a plate-shaped base member having a substantially rectangular shape in a plan view; a first and second electrode solder pads configured to be electrically connected to a semiconductor element when the semiconductor element is mounted on an upper surface of the base member, the electrode solder pads being disposed at a lower surface side of the base member to face each other in a first direction; and first and second auxiliary solder pads disposed on a lower surface of the base member, the auxiliary solder pads being disposed at both sides of the electrode solder pads such that the first and second electrode solder pads are disposed between the first and second auxiliary solder pads in a plan view.

Abstract: A lighting device includes a light source and a light distributor disposed on a light emission side of the light source. The light distributor includes an entrance surface through which light enters and an exit surface through which the light that enters through the entrance surface exits. At least one of the entrance surface and the exit surface includes concave regions. Each of the concave regions includes a smooth concave surface. The concave regions control distribution of light from the light source that is refracted or reflected by an optical lens or a reflective component.

Abstract: An electronic unit is provided including a heat dissipating device having a projecting heat transfer portion, a substrate on one surface side of which the heat dissipating device is disposed and in which an opening portion where the heat transfer portion is inserted is formed, an electronic part disposed on the other surface side of the substrate so that a heat dissipating surface is positioned in the opening portion and connected to the substrate via a frame-shaped connecting portion disposed with a gap between the substrate and itself, and a heat conductive member provided between the heat transfer portion and the heat dissipating surface and between an outer circumference of the heat transfer portion and an inner circumference of the connecting portion, wherein an end portion of the heat conductive member is positioned closer to the heat dissipating device than the gap between the connecting portion and the substrate.

Abstract: A composite electronic component includes a substrate with a first main surface and a side end surface, a first electronic component including external electrodes and mounted on the first main surface of the substrate, a second electronic component including external electrodes and being different in electrical function from the first electronic component mounted on the first main surface of the substrate, and a conductive pattern on the first main surface of the substrate, electrically connecting the first electronic component and the second electronic component to each other, and including one end reaching a side of one side end of the substrate, one external electrode of the first electronic component and one external electrode of the second electronic component being located on the side of the one side end of the substrate, another external electrode of the first electronic component and another external electrode of the second electronic component being connected to the conductive pattern, and the compos

Abstract: A method of manufacturing a light emitting device having a resin package which provides an optical reflectivity equal to or more than 70% at a wavelength between 350 nm and 800 nm after thermal curing, and in which a resin part and a lead are formed in a substantially same plane in an outer side surface, includes a step of sandwiching a lead frame provided with a notch part, by means or an upper mold and a lower mold, a step of transfer-molding a thermosetting resin containing a light reflecting material in a mold sandwiched by the upper mold and the lower mold to form a resin-molded body in the lead frame and a step of cutting the resin-molded body and the lead frame along the notch part.

Abstract: Reinforcement components for electrical connections with limited accessibility Shield structures with reduced spacing between adjacent insulation components and systems and methods for making the same are provided. In some embodiments, a reinforcement component may be compressed between two portions of a first electronic component in order to deform the reinforcement component for filling in a void between the reinforcement component and a coupling formed between the first electronic component and a second electronic component. The first electronic component may be a flexible circuit component that may be folded over the reinforcement component prior to the reinforcement component being compressed. This may enable the reinforcement component to be effectively positioned with respect to the first electronic component prior to being deformed for reinforcing one or more couplings made between the first electronic component and the second electronic component.

Abstract: A component such as an interposer or microelectronic element can be fabricated with a set of vertically extending interconnects of wire bond structure. Such method may include forming a structure having wire bonds extending in an axial direction within one of more openings in an element and each wire bond spaced at least partially apart from a wall of the opening within which it extends, the element consisting essentially of a material having a coefficient of thermal expansion (“CTE”) of less than 10 parts per million per degree Celsius (“ppm/° C.”). First contacts can then be provided at a first surface of the component and second contacts provided at a second surface of the component facing in a direction opposite from the first surface, the first contacts electrically coupled with the second contacts through the wire bonds.

Abstract: Wafer-level package semiconductor devices are described that have a smallest distance between two adjacent attachment bumps smaller than about twenty-five percent (25%) of a pitch between the two adjacent attachment bumps. The smallest distance between the two adjacent attachment bumps allows for an increase in the number of attachment bumps per area without reducing the size of the bumps, which increases solder reliability. The increased solder reliability may reduce stress to the attachment bumps, particularly stress caused by CTE mismatch during thermal cycling tests, dynamic deformation during drop tests or cyclic bending tests, and so on.

Abstract: A printed wiring board includes an insulating layer including insulating material, and a conductor layer formed on a surface of the insulating layer and including conductor pads and conductor patterns such that the conductor pads are positioned to connect one or more electronic components and that the conductor patterns are formed between the conductor pads. The conductor patterns are formed such that each conductor pattern has a pattern width of 3 ?m or less and that the conductor patterns have a pattern interval of 3 ?m or less between adjacent conductor patterns, and the insulating layer has recess portions formed on the surface between the conductor patterns at least along the conductor patterns such that the recess portions have a depth in a range of 0.1 ?m to 2.0 ?m relative to a contact interface at which the conductor patterns and the insulating layer are in contact with each other.

Abstract: An integrated circuit (IC) package that includes a first die, a wire bond coupled to the first die, a first encapsulation layer that at least partially encapsulates the first die and the wire bond, a second die, a redistribution portion coupled to the second die, and a second encapsulation layer that at least partially encapsulates the second die. In some implementations, the wire bond is coupled to the redistribution portion. In some implementations, the integrated circuit (IC) package further includes a package interconnect that is at least partially encapsulated by the second encapsulation layer. In some implementations, the integrated circuit (IC) package further includes a via that is at least partially encapsulated by the second encapsulation layer. In some implementations, the integrated circuit (IC) package has a height of about 500 microns (?m) or less.

Abstract: A wiring substrate includes an insulating substrate having a quadrangular planar outline; a quadrangular frame positioned on the surface of the insulating substrate along the periphery, and including an upper surface, a corner portion, and an adjacent portion, the corner portion including a width-expanded portion defining a via hole extending through the frame, the width-expanded portion including an inner wall surface having a rectilinear edge in a plan view, the adjacent portion including an inner wall surface, the inner wall surface of the width-expanded portion forming an obtuse angle with the inner wall surface of the adjacent portion; a via conductor filling the via hole and not exposed from the inner wall surface of the width-expanded portion; and a sealing metallization layer formed on the upper surface of the frame and electrically connected to the via conductor.

Abstract: Provided is an electronic component package that does not lower reliability while enabling miniaturization and high performance of the electronic component package. The electronic component package includes a main substrate, a first electronic component provided on a main surface of the main substrate, a frame body disposed so as to face the main surface of the main substrate, and a first connection terminal and a second connection terminal disposed on the main surface of the main substrate along a first side of the frame body. The second connection terminal is disposed on the first side of the frame body at a position facing a vicinity of a midpoint of a side of the first electronic component, and the second connection terminal has an area larger than an area of the first connection terminal.

Abstract: A semiconductor device is assembled from a lead frame. The device has a semiconductor die mounted on a flag of the lead frame. A mold compound forms a housing that covers the die. Lead fingers surround the die. Each lead finger has an inner lead length that is covered by the housing and an outer lead length that protrudes from the housing. The inner lead length extends from an edge of the housing towards the die. The inner lead length has an intermediate region that has been bent to form a notch. Bond wires electrically connect electrodes of the die to respective inner lead lengths.

Abstract: A package (120), wherein the package (120) has at least one electronic chip (124), an encapsulation body (138) that encapsulates the electronic chip(s) (124), and a plurality of terminal pins (122) to connect the electronic chip(s) (124), wherein each of the said terminal pins (122) has an encapsulated section (126), which is encapsulated at least partially by the encapsulation body (138) and has an exposed section (128) that protrudes from the encapsulation body (138), and wherein at least a portion of the exposed sections (128) laterally extends from the encapsulation body (138) up to a reversal point (130) and laterally extends back from the reversal point (130) to the encapsulation body (138), so that a free end (132) of the exposed sections (128) is laterally aligned with or to a corresponding side wall (134) of the encapsulation body (138) or is spaced from the corresponding side wall (134) of the encapsulation body (138) laterally outwardly.

Abstract: Methods, systems, and apparatuses for semiconductor devices are provided herein. A semiconductor device includes an array of conductive pads for signals. One or more non-linear compliant springs may be present to route signals from the conductive pads to interconnect pads formed on the semiconductor device to attach bump interconnects. Each non-linear compliant spring may include one or more routing segments. The semiconductor device may be mounted to a circuit board by the bump interconnects. When the semiconductor device operates, heat may be generated by the semiconductor device, causing thermal expansion by the semiconductor device and the circuit board. The semiconductor device and circuit board may expand by different amounts due to differences in their thermal coefficients of expansion. The non-linear compliant springs provide for compliance between the conductive pads and bump interconnects to allow for the different rates of expansion.

Abstract: Packaged semiconductor devices and packaging methods are disclosed. In some embodiments, a packaged semiconductor device includes an integrated circuit die and through-vias disposed in a molding compound. A first redistribution layer (RDL) is disposed over a first side of the through-vias, the integrated circuit die, and the molding compound. A second RDL is disposed over a second side of the through-vias, the integrated circuit die, and the molding compound. Contact pads are disposed over the second RDL. An insulating material of the second RDL includes a recess around a perimeter of one of the contact pads.

Abstract: A light emitting diode (LED) package includes: a main body mounted on a substrate; a light emitting diode that is mounted in the main body and emits light; and a lead frame exposed to allow the main body to be selectively top-mounted or side-mounted. A backlight unit includes: a light guide plate configured to allow a light source to proceed to a liquid crystal panel; a light emitting diode (LED) mounted in a main body mounted on a substrate and generating a light source; and an LED package having a lead frame exposed to allow the main body to be selectively top-mounted or side-mounted, and being mounted on the light guide plate.

Abstract: A flexible chip set encapsulation structure includes a chip set. The chip set comprises a plurality of spaced chips and a fixing film. The fixing film is adapted to wrap and fix the chips. The fixing film has at least one bending portion at a predetermined position for the fixing film to have flexibility in a predetermined direction. Thus, the flexible chip set encapsulation structure is flexible for bending. When the user wears the flexible chip set, the movement of the user won't be confined. Besides, the chip set is completely attached to the body to provide a comfortable wear, and the chips provide a better far infrared radiation effect.

Abstract: A Quad Flat Package (QFP) semiconductor device has a multi-stepped lead frame for forming rows of external contacts. A semiconductor die is attached to a die pad of the lead frame and electrically connected to lead with bond wires. The die and bond wires are encapsulated with a mold compound and then multiple cuts are made to the lead frame to form the rows of external contacts.

Abstract: A lead frame package structure with low EMI includes at least a die holder each for supporting a die, and at least a lead frame each including a first terminal for connecting a printed circuit board, a second terminal for connecting the die, and a lead for connecting the first terminal and the second terminal, wherein the height of the lead is lower than the height of the first terminal and the second terminal.

Abstract: An integrated circuit that detects whether a through silicon via has defects or not, at a wafer level. The integrated circuit includes a semiconductor substrate, a through silicon via configured to be formed in the semiconductor substrate to extend to a certain depth from the surface of the semiconductor substrate, an output pad, and a current path providing unit configured to provide a current, flowing between the semiconductor substrate and the through silicon via, to the output pad during a test mode.

Abstract: An integrated circuit package system includes an in-line strip, attaching an integrated circuit die over the in-line strip, and applying a molding material with a molded segment having a molded strip protrusion formed therefrom over the in-line strip.

Abstract: A method for producing a component and device including a component is disclosed. A basic substrate having paper as substrate material is provided, at least one integrated circuit is applied to the basic substrate, the at least one integrated circuit applied on the basic substrate is enveloped with an encapsulant, and at least parts of the basic substrate are removed from the at least one enveloped integrated circuit.

Abstract: Some exemplary embodiments of high voltage cascoded III-nitride semiconductor package with a stamped leadframe have been disclosed. One exemplary embodiment comprises a III-nitride transistor having an anode of a diode stacked atop a source of the III-nitride transistor, and a stamped leadframe comprising a first bent lead coupled to a gate of the III-nitride transistor and the anode of the diode, and a second bent lead coupled to a drain of the III-nitride transistor. The bent leads expose respective flat portions that are surface mountable. In this manner, reduced package footprint, improved surge current capability, and higher performance may be achieved compared to conventional wire bonded packages. Furthermore, since multiple packages may be assembled at a time, high integration and cost savings may be achieved compared to conventional methods requiring individual package processing and externally sourced parts.

Abstract: Some exemplary embodiments of high voltage cascaded III-nitride semiconductor package with an etched leadframe have been disclosed. One exemplary embodiment comprises a III-nitride transistor having an anode of a diode stacked over a source of the III-nitride transistor, and a leadframe that is etched to form a first leadframe paddle portion coupled to a gate of the III-nitride transistor and the anode of the diode, and a second leadframe paddle portion coupled to a drain of the III-nitride transistor. The leadframe paddle portions enable the package to be surface mountable. In this manner, reduced package footprint, improved surge current capability, and higher performance may be achieved compared to conventional wire bonded packages. Furthermore, since multiple packages may be assembled at a time, high integration and cost savings may be achieved compared to conventional methods requiring individual package processing and externally sourced parts.

Abstract: In some examples, a semiconductor package can be configured to electrically couple to a printed circuit board. The semiconductor package can include: (a) a lid having one or more first electrically conductive leads; (b) a base having a top, a bottom and one or more sides between the top and the bottom, the base having one or more second electrically conductive leads electrically coupled to the one or more first electrically conductive leads; (c) one or more first semiconductor devices mechanically coupled to the lid and electrically coupled to the one or more first electrically conductive leads; and (d) one or more first micro-electrical-mechanical system devices mechanically coupled to the lid and electrically coupled to the one or more first electrically conductive leads. The lid can be coupled to the base and at least one of the lid or the base has at least one port hole.

Abstract: A semiconductor device featuring a semiconductor chip including a MOSFET and having a first main surface and a second, opposing main surface, a source electrode pad and a gate electrode pad over the first main surface, a drain electrode over the second main surface, a source external terminal and a gate external terminal, each having a first main surface electrically connected to the source electrode pad and gate electrode pad of the chip, respectively, and a drain external terminal having a first main surface and a second, opposing main surface and being electrically connected to the second main surface of the chip, each of the source, gate and drain external terminals having second main surfaces thereof in a same plane, and, in a plan view of the external terminals, the gate external terminal has a portion located between the source and drain external terminals in at least one direction.

Abstract: The invention relates to a power semiconductor chip (10) having at least one upper-sided potential surface and contacting thick wires (50) or strips, comprising a connecting layer (I) on the potential surfaces, and at least one metal moulded body (24, 25) on the connecting layer(s), the lower flat side thereof facing the potential surface being provided with a coating to be applied to the connecting layer (I) according to a connection method, and the material composition thereof and the thickness of the related thick wires (50) or strips arranged on the upper side of the moulded body used according to the method for contacting are selected corresponding to the magnitude.

Abstract: A wiring device for a semiconductor device, a composite wiring device for a semiconductor device and a resin-sealed semiconductor device are provided, each of which is capable of mounting thereon a semiconductor chip smaller than conventional chips and being manufactured at lower cost. The wiring device connects an electrode on a semiconductor chip with an external wiring device, and has an insulating layer, a metal substrate and a copper wiring layer. The wiring device has a semiconductor chip support portion provided on the side of the copper wiring layer with respect to the insulating layer. The copper wiring layer includes a first terminal, a second terminal and a wiring portion. The first terminal is connected with the electrode. The second terminal is connected with the external wiring device. The wiring portion connects the first terminal with the second terminal.

Abstract: To suppress the reduction in reliability of a resin-sealed semiconductor device. A first cap (member) and a second cap (member) with a cavity (space formation portion) are superimposed and bonded together to form a sealed space. A semiconductor including a sensor chip (semiconductor chip) and wires inside the space is manufactured in the following way. In a sealing step of sealing a joint part between the caps, a sealing member is formed of resin such that an entirety of an upper surface of the second cap and an entirety of a lower surface of the first cap are respectively exposed. Thus, in the sealing step, the pressure acting in the direction of crushing the second cap can be decreased.

Abstract: A semiconductor device which can prevent a deterioration in the electrical properties by preventing sputters generated by laser welding from adhering to a circuit pattern or a semiconductor chip and a method for fabricating such a semiconductor device are provided. A connection conductor is bonded to a copper foil formed over a ceramic by a solder and resin is injected to a level lower than a top of the connection conductor. Laser welding is then performed. After that, resin is injected. This prevents sputters generated by the laser welding from adhering to a circuit pattern or a semiconductor chip. As a result, a deterioration in the electrical properties can be prevented.

Abstract: A semiconductor unit of certain aspects of the invention includes electrically conductive plates in the shape of the letter L, each consisting of a horizontally disposed leg portion and a vertically disposed flat body portion that is perpendicular to a cooling plate adhered to the bottom of the semiconductor unit. A pair of the vertically disposed flat body portions sandwiches a semiconductor chip. Owing to this construction, the heat generated in the semiconductor chip can be conducted away through the both surfaces of the chip, thus improving cooling performance. Since the heat is conducted away through the leg portions of the L-shaped electrically conductive plates a projected planar area occupied by the cooling plate required for cooling the semiconductor unit is reduced. Therefore, the size of the semiconductor unit can be reduced.

Abstract: A circuit panel can include contacts exposed at a connection site of a major surface thereof and configured to be coupled to terminals of a microelectronic package. The connection site can define a peripheral boundary on the major surface surrounding a group of the contacts that is configured to be coupled to a single microelectronic package. The group of contacts can include first, second, third, and fourth sets of first contacts. Signal assignments of the first and third sets of first contacts can be symmetric about a theoretical plane normal to the major surface with signal assignments of the respective second and fourth sets of first contacts. Each of the sets of first contacts can be configured to carry identical signals. Each of the sets of first contacts can be configured to carry address information sufficient to specify a location within a memory storage array of the microelectronic package.

Abstract: A surface mount package of a semiconductor device, has: an encapsulation, housing at least one die including semiconductor material; and electrical contact leads, protruding from the encapsulation to be electrically coupled to contact pads of a circuit board; the encapsulation has a main face designed to face a top surface of the circuit board, which is provided with coupling features designed for mechanical coupling to the circuit board to increase a resonant frequency of the mounted package. The coupling features envisage at least a first coupling recess defined within the encapsulation starting from the main face, designed to be engaged by a corresponding coupling element fixed to the circuit board, thereby restricting movements of the mounted package.

Abstract: A device including a semiconductor chip and metal foils. One embodiment provides a device including a semiconductor chip having a first electrode on a first face and a second electrode on a second face opposite to the first face. A first metal foil is attached to the first electrode of the semiconductor chip in an electrically conductive manner. A second metal foil is attached to the second electrode of the semiconductor chip in an electrically conductive manner.

Abstract: Disclosed herein is a power module package including: a first substrate; a second substrate having a pad for connection to the first substrate formed on one side or both sides of one surface thereof and having external connection terminals for connection to the outside formed on the other surface thereof; and a lead frame having one end bonded to the first substrate and the other end bonded to the pad of the second substrate to thereby vertically connect the first and second substrates to each other.

Abstract: A method for fabricating a circuit apparatus includes forming a wiring layer, a conductive layer, and a first insulating layer on the wiring substrate, removing the conductive layer in an opening of the first insulating layer so as to expose the wiring layer, forming a gold plating layer on the wiring layer, removing the first insulating layer and the conductive layer, forming a second insulating layer on the wiring substrate, the second insulating layer having an opening through which the gold plating and adjacent wiring layers are exposed, and electrically connecting a circuit element to the gold plating layer.

Abstract: A contactless communication medium which can prevent invasion of static electricity and has an outer surface which can satisfy requirements on the flatness thereof. The contactless communication medium has a sealing member including an insulating layer and a conductive layer provided in a stacked manner and having a shape covering an IC module is located such that the insulating layer is on the IC module side. Owing to this, static electricity coming from outside is diffused by the conductive layer and blocked by the insulating layer. Thus, adverse influence of the static electricity on the IC module is prevented. The contactless communication medium can also satisfy the requirements on the flatness of an outer surface thereof.

Abstract: A packaged semiconductor die has a die support mounting surface mounted to a die support having external connectors. A die connection pad surface opposite to die supporting mount surface has associated die connection pads that are circuit nodes of the semiconductor die. The die connection pad surface also has a power rail pad. The power rail pad has a surface area larger than surface areas of the die connection pads. Bond wires electrically couple the power rail pad to two or more of the die connection pads.

Abstract: A process for assembling a semiconductor device includes providing a lead frame having a native plane and a plurality of leads having a native lead pitch. The process includes trimming and forming a first subset of the plurality of leads to provide a first row of leads. The process includes trimming and forming a second subset of the plurality of leads to provide a second row of leads. At least one subset of leads is formed with an obtuse angle relative to the native plane such that lead pitch associated with the first or second subset of leads is greater than the native lead pitch.

Abstract: A microelectronic component package includes a plurality of electrical leads which are coupled to a microelectronic component and which have exposed lengths extending outwardly beyond a peripheral edge of an encapsulant. A plurality of terminals may be positioned proximate a terminal face of the encapsulant and these terminals may be electrically coupled to the same leads. This can facilitate connection of the microelectronic component to a substrate using the leads as a conventional leaded package. The terminals, however, can facilitate stacking of the leaded package with one or more additional microelectronic components, e.g., a BGA package.

Abstract: A method and apparatus of packaging a semiconductor device with a clip is disclosed. The clip defines a first contact region and a second contact region on a same face of the at least one clip. The chip defines a first face, and a second face opposite to the first face, the first contact region being attached to the first face of the chip and the second contact region being located within a same plane with the second face of the clip.

Abstract: The invention relates to a high power LED package, in which a package body is integrally formed with resin to have a recess for receiving an LED chip. A first sheet metal member is electrically connected with the LED chip, supports the LED chip at its upper partial portion in the recess, is surrounded by the package body extending to the side face of the package body, and has a heat transfer section for transferring heat generated from the LED chip to the metal plate of the board and extending downward from the inside of the package body so that a lower end thereof is exposed at a bottom face of the package body thus to contact the board. A second sheet metal member is electrically connected with the LED chip spaced apart from the first sheet metal member for a predetermined gap, and extends through the inside of the package body to the side face of the package body in a direction opposite to the first sheet metal member. A transparent sealant is sealingly filled up into the recess.