Bent (e.g., J-shaped) Lead Patents (Class 257/696)
  • Patent number: 10443819
    Abstract: A lighting device includes a light source and a light distributor disposed on a light emission side of the light source. The light distributor includes an entrance surface through which light enters and an exit surface through which the light that enters through the entrance surface exits. At least one of the entrance surface and the exit surface includes concave regions. Each of the concave regions includes a smooth concave surface. The concave regions control distribution of light from the light source that is refracted or reflected by an optical lens or a reflective component.
    Type: Grant
    Filed: October 18, 2017
    Date of Patent: October 15, 2019
    Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.
    Inventor: Kazuyuki Yamae
  • Patent number: 10372024
    Abstract: An electronic unit is provided including a heat dissipating device having a projecting heat transfer portion, a substrate on one surface side of which the heat dissipating device is disposed and in which an opening portion where the heat transfer portion is inserted is formed, an electronic part disposed on the other surface side of the substrate so that a heat dissipating surface is positioned in the opening portion and connected to the substrate via a frame-shaped connecting portion disposed with a gap between the substrate and itself, and a heat conductive member provided between the heat transfer portion and the heat dissipating surface and between an outer circumference of the heat transfer portion and an inner circumference of the connecting portion, wherein an end portion of the heat conductive member is positioned closer to the heat dissipating device than the gap between the connecting portion and the substrate.
    Type: Grant
    Filed: March 10, 2016
    Date of Patent: August 6, 2019
    Assignee: CASIO COMPUTER CO., LTD.
    Inventors: Toshifumi Kase, Hirofumi Fujikura
  • Patent number: 10297391
    Abstract: A composite electronic component includes a substrate with a first main surface and a side end surface, a first electronic component including external electrodes and mounted on the first main surface of the substrate, a second electronic component including external electrodes and being different in electrical function from the first electronic component mounted on the first main surface of the substrate, and a conductive pattern on the first main surface of the substrate, electrically connecting the first electronic component and the second electronic component to each other, and including one end reaching a side of one side end of the substrate, one external electrode of the first electronic component and one external electrode of the second electronic component being located on the side of the one side end of the substrate, another external electrode of the first electronic component and another external electrode of the second electronic component being connected to the conductive pattern, and the compos
    Type: Grant
    Filed: December 27, 2016
    Date of Patent: May 21, 2019
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventors: Koki Shibuya, Hirokazu Takashima, Akio Masunari, Tomoyuki Nakamura
  • Patent number: 10115870
    Abstract: A method of manufacturing a light emitting device having a resin package which provides an optical reflectivity equal to or more than 70% at a wavelength between 350 nm and 800 nm after thermal curing, and in which a resin part and a lead are formed in a substantially same plane in an outer side surface, includes a step of sandwiching a lead frame provided with a notch part, by means or an upper mold and a lower mold, a step of transfer-molding a thermosetting resin containing a light reflecting material in a mold sandwiched by the upper mold and the lower mold to form a resin-molded body in the lead frame and a step of cutting the resin-molded body and the lead frame along the notch part.
    Type: Grant
    Filed: November 23, 2016
    Date of Patent: October 30, 2018
    Assignee: NICHIA CORPORATION
    Inventors: Hirofumi Ichikawa, Masaki Hayashi, Shimpei Sasaoka, Tomohide Miki
  • Patent number: 10098224
    Abstract: Reinforcement components for electrical connections with limited accessibility Shield structures with reduced spacing between adjacent insulation components and systems and methods for making the same are provided. In some embodiments, a reinforcement component may be compressed between two portions of a first electronic component in order to deform the reinforcement component for filling in a void between the reinforcement component and a coupling formed between the first electronic component and a second electronic component. The first electronic component may be a flexible circuit component that may be folded over the reinforcement component prior to the reinforcement component being compressed. This may enable the reinforcement component to be effectively positioned with respect to the first electronic component prior to being deformed for reinforcing one or more couplings made between the first electronic component and the second electronic component.
    Type: Grant
    Filed: January 15, 2018
    Date of Patent: October 9, 2018
    Assignee: APPLE INC.
    Inventors: Yindar Chuo, Nathan K. Gupta, Po-Jui Chen, Wei Lin, Wei-Hao Sun, Jui-Ming Yang
  • Patent number: 10032647
    Abstract: A component such as an interposer or microelectronic element can be fabricated with a set of vertically extending interconnects of wire bond structure. Such method may include forming a structure having wire bonds extending in an axial direction within one of more openings in an element and each wire bond spaced at least partially apart from a wall of the opening within which it extends, the element consisting essentially of a material having a coefficient of thermal expansion (“CTE”) of less than 10 parts per million per degree Celsius (“ppm/° C.”). First contacts can then be provided at a first surface of the component and second contacts provided at a second surface of the component facing in a direction opposite from the first surface, the first contacts electrically coupled with the second contacts through the wire bonds.
    Type: Grant
    Filed: May 5, 2017
    Date of Patent: July 24, 2018
    Assignee: Invensas Corporation
    Inventors: Rajesh Katkar, Cyprian Emeka Uzoh
  • Patent number: 9966350
    Abstract: Wafer-level package semiconductor devices are described that have a smallest distance between two adjacent attachment bumps smaller than about twenty-five percent (25%) of a pitch between the two adjacent attachment bumps. The smallest distance between the two adjacent attachment bumps allows for an increase in the number of attachment bumps per area without reducing the size of the bumps, which increases solder reliability. The increased solder reliability may reduce stress to the attachment bumps, particularly stress caused by CTE mismatch during thermal cycling tests, dynamic deformation during drop tests or cyclic bending tests, and so on.
    Type: Grant
    Filed: June 6, 2011
    Date of Patent: May 8, 2018
    Assignee: Maxim Integrated Products, Inc.
    Inventors: Vijay Ullal, Arkadii V. Samoilov
  • Patent number: 9711439
    Abstract: A printed wiring board includes an insulating layer including insulating material, and a conductor layer formed on a surface of the insulating layer and including conductor pads and conductor patterns such that the conductor pads are positioned to connect one or more electronic components and that the conductor patterns are formed between the conductor pads. The conductor patterns are formed such that each conductor pattern has a pattern width of 3 ?m or less and that the conductor patterns have a pattern interval of 3 ?m or less between adjacent conductor patterns, and the insulating layer has recess portions formed on the surface between the conductor patterns at least along the conductor patterns such that the recess portions have a depth in a range of 0.1 ?m to 2.0 ?m relative to a contact interface at which the conductor patterns and the insulating layer are in contact with each other.
    Type: Grant
    Filed: September 1, 2015
    Date of Patent: July 18, 2017
    Assignee: IBIDEN CO., LTD.
    Inventors: Hajime Sakamoto, Nobuya Takahashi
  • Patent number: 9679873
    Abstract: An integrated circuit (IC) package that includes a first die, a wire bond coupled to the first die, a first encapsulation layer that at least partially encapsulates the first die and the wire bond, a second die, a redistribution portion coupled to the second die, and a second encapsulation layer that at least partially encapsulates the second die. In some implementations, the wire bond is coupled to the redistribution portion. In some implementations, the integrated circuit (IC) package further includes a package interconnect that is at least partially encapsulated by the second encapsulation layer. In some implementations, the integrated circuit (IC) package further includes a via that is at least partially encapsulated by the second encapsulation layer. In some implementations, the integrated circuit (IC) package has a height of about 500 microns (?m) or less.
    Type: Grant
    Filed: July 28, 2015
    Date of Patent: June 13, 2017
    Assignee: QUALCOMM Incorporated
    Inventors: Lizabeth Ann Keser, David Fraser Rae, Piyush Gupta
  • Patent number: 9526172
    Abstract: A wiring substrate includes an insulating substrate having a quadrangular planar outline; a quadrangular frame positioned on the surface of the insulating substrate along the periphery, and including an upper surface, a corner portion, and an adjacent portion, the corner portion including a width-expanded portion defining a via hole extending through the frame, the width-expanded portion including an inner wall surface having a rectilinear edge in a plan view, the adjacent portion including an inner wall surface, the inner wall surface of the width-expanded portion forming an obtuse angle with the inner wall surface of the adjacent portion; a via conductor filling the via hole and not exposed from the inner wall surface of the width-expanded portion; and a sealing metallization layer formed on the upper surface of the frame and electrically connected to the via conductor.
    Type: Grant
    Filed: August 4, 2015
    Date of Patent: December 20, 2016
    Assignee: NGK SPARK PLUG CO., LTD.
    Inventor: Kazushige Akita
  • Patent number: 9474179
    Abstract: Provided is an electronic component package that does not lower reliability while enabling miniaturization and high performance of the electronic component package. The electronic component package includes a main substrate, a first electronic component provided on a main surface of the main substrate, a frame body disposed so as to face the main surface of the main substrate, and a first connection terminal and a second connection terminal disposed on the main surface of the main substrate along a first side of the frame body. The second connection terminal is disposed on the first side of the frame body at a position facing a vicinity of a midpoint of a side of the first electronic component, and the second connection terminal has an area larger than an area of the first connection terminal.
    Type: Grant
    Filed: August 7, 2015
    Date of Patent: October 18, 2016
    Assignee: PANASONIC CORPORATION
    Inventors: Yukitoshi Ota, Fumito Itou, Kiyomi Hagihara
  • Patent number: 9299645
    Abstract: A semiconductor device is assembled from a lead frame. The device has a semiconductor die mounted on a flag of the lead frame. A mold compound forms a housing that covers the die. Lead fingers surround the die. Each lead finger has an inner lead length that is covered by the housing and an outer lead length that protrudes from the housing. The inner lead length extends from an edge of the housing towards the die. The inner lead length has an intermediate region that has been bent to form a notch. Bond wires electrically connect electrodes of the die to respective inner lead lengths.
    Type: Grant
    Filed: November 23, 2014
    Date of Patent: March 29, 2016
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Lei Wang, Liping Guo, Jinsheng Wang
  • Patent number: 9293400
    Abstract: A package (120), wherein the package (120) has at least one electronic chip (124), an encapsulation body (138) that encapsulates the electronic chip(s) (124), and a plurality of terminal pins (122) to connect the electronic chip(s) (124), wherein each of the said terminal pins (122) has an encapsulated section (126), which is encapsulated at least partially by the encapsulation body (138) and has an exposed section (128) that protrudes from the encapsulation body (138), and wherein at least a portion of the exposed sections (128) laterally extends from the encapsulation body (138) up to a reversal point (130) and laterally extends back from the reversal point (130) to the encapsulation body (138), so that a free end (132) of the exposed sections (128) is laterally aligned with or to a corresponding side wall (134) of the encapsulation body (138) or is spaced from the corresponding side wall (134) of the encapsulation body (138) laterally outwardly.
    Type: Grant
    Filed: January 6, 2015
    Date of Patent: March 22, 2016
    Assignee: Infineon Technologies AG
    Inventor: Sergey Ananiev
  • Patent number: 9287189
    Abstract: Methods, systems, and apparatuses for semiconductor devices are provided herein. A semiconductor device includes an array of conductive pads for signals. One or more non-linear compliant springs may be present to route signals from the conductive pads to interconnect pads formed on the semiconductor device to attach bump interconnects. Each non-linear compliant spring may include one or more routing segments. The semiconductor device may be mounted to a circuit board by the bump interconnects. When the semiconductor device operates, heat may be generated by the semiconductor device, causing thermal expansion by the semiconductor device and the circuit board. The semiconductor device and circuit board may expand by different amounts due to differences in their thermal coefficients of expansion. The non-linear compliant springs provide for compliance between the conductive pads and bump interconnects to allow for the different rates of expansion.
    Type: Grant
    Filed: December 13, 2012
    Date of Patent: March 15, 2016
    Assignee: Broadcom Corporation
    Inventors: Milind S. Bhagavat, Javed Iqbal Sandhu, Rezaur Rahman Khan, Teck Yang Tan
  • Patent number: 9035461
    Abstract: Packaged semiconductor devices and packaging methods are disclosed. In some embodiments, a packaged semiconductor device includes an integrated circuit die and through-vias disposed in a molding compound. A first redistribution layer (RDL) is disposed over a first side of the through-vias, the integrated circuit die, and the molding compound. A second RDL is disposed over a second side of the through-vias, the integrated circuit die, and the molding compound. Contact pads are disposed over the second RDL. An insulating material of the second RDL includes a recess around a perimeter of one of the contact pads.
    Type: Grant
    Filed: January 30, 2013
    Date of Patent: May 19, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yen-Chang Hu, Ching-Wen Hsiao, Chen-Shien Chen
  • Patent number: 9022632
    Abstract: A light emitting diode (LED) package includes: a main body mounted on a substrate; a light emitting diode that is mounted in the main body and emits light; and a lead frame exposed to allow the main body to be selectively top-mounted or side-mounted. A backlight unit includes: a light guide plate configured to allow a light source to proceed to a liquid crystal panel; a light emitting diode (LED) mounted in a main body mounted on a substrate and generating a light source; and an LED package having a lead frame exposed to allow the main body to be selectively top-mounted or side-mounted, and being mounted on the light guide plate.
    Type: Grant
    Filed: July 3, 2009
    Date of Patent: May 5, 2015
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Geun-Young Kim, Tomohisa Onishi, Jung-Hun Lee, Young-Taek Kim, Jong-Jin Park, Mi-Jeong Yun, Young-Sam Park, Hun-Joo Hahm, Hyung-Suk Kim, Seong-Yeon Han, Do-Hun Kim, Dae-Yeon Kim, Dae-Hyun Kim, Jung-Kyu Park
  • Patent number: 8987890
    Abstract: A flexible chip set encapsulation structure includes a chip set. The chip set comprises a plurality of spaced chips and a fixing film. The fixing film is adapted to wrap and fix the chips. The fixing film has at least one bending portion at a predetermined position for the fixing film to have flexibility in a predetermined direction. Thus, the flexible chip set encapsulation structure is flexible for bending. When the user wears the flexible chip set, the movement of the user won't be confined. Besides, the chip set is completely attached to the body to provide a comfortable wear, and the chips provide a better far infrared radiation effect.
    Type: Grant
    Filed: September 10, 2013
    Date of Patent: March 24, 2015
    Assignee: Ghi Fu Technology Co., Ltd.
    Inventor: Li-Chi Lin
  • Patent number: 8981541
    Abstract: A Quad Flat Package (QFP) semiconductor device has a multi-stepped lead frame for forming rows of external contacts. A semiconductor die is attached to a die pad of the lead frame and electrically connected to lead with bond wires. The die and bond wires are encapsulated with a mold compound and then multiple cuts are made to the lead frame to form the rows of external contacts.
    Type: Grant
    Filed: July 10, 2013
    Date of Patent: March 17, 2015
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Kong Bee Tiu, Ruzaini B. Ibrahim, Wai Yew Lo
  • Patent number: 8975539
    Abstract: A lead frame package structure with low EMI includes at least a die holder each for supporting a die, and at least a lead frame each including a first terminal for connecting a printed circuit board, a second terminal for connecting the die, and a lead for connecting the first terminal and the second terminal, wherein the height of the lead is lower than the height of the first terminal and the second terminal.
    Type: Grant
    Filed: March 8, 2012
    Date of Patent: March 10, 2015
    Assignee: NOVATEK Microelectronics Corp.
    Inventor: Yu-Chang Pai
  • Patent number: 8946869
    Abstract: An integrated circuit that detects whether a through silicon via has defects or not, at a wafer level. The integrated circuit includes a semiconductor substrate, a through silicon via configured to be formed in the semiconductor substrate to extend to a certain depth from the surface of the semiconductor substrate, an output pad, and a current path providing unit configured to provide a current, flowing between the semiconductor substrate and the through silicon via, to the output pad during a test mode.
    Type: Grant
    Filed: March 4, 2011
    Date of Patent: February 3, 2015
    Assignee: SK Hynix Inc.
    Inventors: Dae-Suk Kim, Jong-Chern Lee, Chul Kim
  • Patent number: 8937372
    Abstract: An integrated circuit package system includes an in-line strip, attaching an integrated circuit die over the in-line strip, and applying a molding material with a molded segment having a molded strip protrusion formed therefrom over the in-line strip.
    Type: Grant
    Filed: March 21, 2007
    Date of Patent: January 20, 2015
    Assignee: STATS ChipPAC Ltd.
    Inventors: Jae Hak Yee, Junwoo Myung
  • Patent number: 8872314
    Abstract: A method for producing a component and device including a component is disclosed. A basic substrate having paper as substrate material is provided, at least one integrated circuit is applied to the basic substrate, the at least one integrated circuit applied on the basic substrate is enveloped with an encapsulant, and at least parts of the basic substrate are removed from the at least one enveloped integrated circuit.
    Type: Grant
    Filed: June 18, 2013
    Date of Patent: October 28, 2014
    Assignee: Infineon Technologies AG
    Inventors: Horst Theuss, Albert Auburger, Jochen Dangelmaier, Josef Hirtreiter
  • Patent number: 8853706
    Abstract: Some exemplary embodiments of high voltage cascoded III-nitride semiconductor package with a stamped leadframe have been disclosed. One exemplary embodiment comprises a III-nitride transistor having an anode of a diode stacked atop a source of the III-nitride transistor, and a stamped leadframe comprising a first bent lead coupled to a gate of the III-nitride transistor and the anode of the diode, and a second bent lead coupled to a drain of the III-nitride transistor. The bent leads expose respective flat portions that are surface mountable. In this manner, reduced package footprint, improved surge current capability, and higher performance may be achieved compared to conventional wire bonded packages. Furthermore, since multiple packages may be assembled at a time, high integration and cost savings may be achieved compared to conventional methods requiring individual package processing and externally sourced parts.
    Type: Grant
    Filed: February 1, 2012
    Date of Patent: October 7, 2014
    Assignee: International Rectifier Corporation
    Inventors: Chuan Cheah, Dae Keun Park
  • Patent number: 8853707
    Abstract: Some exemplary embodiments of high voltage cascaded III-nitride semiconductor package with an etched leadframe have been disclosed. One exemplary embodiment comprises a III-nitride transistor having an anode of a diode stacked over a source of the III-nitride transistor, and a leadframe that is etched to form a first leadframe paddle portion coupled to a gate of the III-nitride transistor and the anode of the diode, and a second leadframe paddle portion coupled to a drain of the III-nitride transistor. The leadframe paddle portions enable the package to be surface mountable. In this manner, reduced package footprint, improved surge current capability, and higher performance may be achieved compared to conventional wire bonded packages. Furthermore, since multiple packages may be assembled at a time, high integration and cost savings may be achieved compared to conventional methods requiring individual package processing and externally sourced parts.
    Type: Grant
    Filed: February 1, 2012
    Date of Patent: October 7, 2014
    Assignee: International Rectifier Corporation
    Inventors: Chuan Cheah, Dae Keun Park
  • Patent number: 8853564
    Abstract: In some examples, a semiconductor package can be configured to electrically couple to a printed circuit board. The semiconductor package can include: (a) a lid having one or more first electrically conductive leads; (b) a base having a top, a bottom and one or more sides between the top and the bottom, the base having one or more second electrically conductive leads electrically coupled to the one or more first electrically conductive leads; (c) one or more first semiconductor devices mechanically coupled to the lid and electrically coupled to the one or more first electrically conductive leads; and (d) one or more first micro-electrical-mechanical system devices mechanically coupled to the lid and electrically coupled to the one or more first electrically conductive leads. The lid can be coupled to the base and at least one of the lid or the base has at least one port hole.
    Type: Grant
    Filed: April 30, 2010
    Date of Patent: October 7, 2014
    Assignee: Ubotic Intellectual Property Co. Ltd.
    Inventors: Chi Kwong Lo, Lik Hang Wan, Ming Wa Tam
  • Patent number: 8816411
    Abstract: A semiconductor device featuring a semiconductor chip including a MOSFET and having a first main surface and a second, opposing main surface, a source electrode pad and a gate electrode pad over the first main surface, a drain electrode over the second main surface, a source external terminal and a gate external terminal, each having a first main surface electrically connected to the source electrode pad and gate electrode pad of the chip, respectively, and a drain external terminal having a first main surface and a second, opposing main surface and being electrically connected to the second main surface of the chip, each of the source, gate and drain external terminals having second main surfaces thereof in a same plane, and, in a plan view of the external terminals, the gate external terminal has a portion located between the source and drain external terminals in at least one direction.
    Type: Grant
    Filed: May 31, 2013
    Date of Patent: August 26, 2014
    Assignees: Renesas Electronics Corporation, Renesas Eastern Japan Semiconductor, Inc.
    Inventors: Ryoichi Kajiwara, Masahiro Koizumi, Toshiak Morita, Kazuya Takahashi, Munehisa Kishimoto, Shigeru Ishii, Toshinori Hirashima, Yasushi Takahashi, Toshiyuki Hata, Hiroshi Sato, Keiichi Ookawa
  • Publication number: 20140225247
    Abstract: The invention relates to a power semiconductor chip (10) having at least one upper-sided potential surface and contacting thick wires (50) or strips, comprising a connecting layer (I) on the potential surfaces, and at least one metal moulded body (24, 25) on the connecting layer(s), the lower flat side thereof facing the potential surface being provided with a coating to be applied to the connecting layer (I) according to a connection method, and the material composition thereof and the thickness of the related thick wires (50) or strips arranged on the upper side of the moulded body used according to the method for contacting are selected corresponding to the magnitude.
    Type: Application
    Filed: September 10, 2012
    Publication date: August 14, 2014
    Applicant: DANFOSS SILICON POWER GMBH
    Inventors: Martin Becker, Ronald Eisele, Frank Osterwald, Jacek Rudzki
  • Patent number: 8796832
    Abstract: A wiring device for a semiconductor device, a composite wiring device for a semiconductor device and a resin-sealed semiconductor device are provided, each of which is capable of mounting thereon a semiconductor chip smaller than conventional chips and being manufactured at lower cost. The wiring device connects an electrode on a semiconductor chip with an external wiring device, and has an insulating layer, a metal substrate and a copper wiring layer. The wiring device has a semiconductor chip support portion provided on the side of the copper wiring layer with respect to the insulating layer. The copper wiring layer includes a first terminal, a second terminal and a wiring portion. The first terminal is connected with the electrode. The second terminal is connected with the external wiring device. The wiring portion connects the first terminal with the second terminal.
    Type: Grant
    Filed: February 23, 2012
    Date of Patent: August 5, 2014
    Assignee: Dai Nippon Printing Co., Ltd.
    Inventors: Susumu Baba, Masachika Masuda, Hiromichi Suzuki
  • Patent number: 8742559
    Abstract: To suppress the reduction in reliability of a resin-sealed semiconductor device. A first cap (member) and a second cap (member) with a cavity (space formation portion) are superimposed and bonded together to form a sealed space. A semiconductor including a sensor chip (semiconductor chip) and wires inside the space is manufactured in the following way. In a sealing step of sealing a joint part between the caps, a sealing member is formed of resin such that an entirety of an upper surface of the second cap and an entirety of a lower surface of the first cap are respectively exposed. Thus, in the sealing step, the pressure acting in the direction of crushing the second cap can be decreased.
    Type: Grant
    Filed: March 14, 2012
    Date of Patent: June 3, 2014
    Assignee: Renesas Electronics Corporation
    Inventor: Noriyuki Takahashi
  • Patent number: 8710666
    Abstract: A semiconductor device which can prevent a deterioration in the electrical properties by preventing sputters generated by laser welding from adhering to a circuit pattern or a semiconductor chip and a method for fabricating such a semiconductor device are provided. A connection conductor is bonded to a copper foil formed over a ceramic by a solder and resin is injected to a level lower than a top of the connection conductor. Laser welding is then performed. After that, resin is injected. This prevents sputters generated by the laser welding from adhering to a circuit pattern or a semiconductor chip. As a result, a deterioration in the electrical properties can be prevented.
    Type: Grant
    Filed: June 16, 2010
    Date of Patent: April 29, 2014
    Assignees: Aisin AW Co., Ltd., Fuji Electric Co., Ltd.
    Inventors: Junji Tsuruoka, Kazuo Aoki, Masaki Ono, Katsuhiko Yoshihara
  • Patent number: 8710644
    Abstract: A semiconductor unit of certain aspects of the invention includes electrically conductive plates in the shape of the letter L, each consisting of a horizontally disposed leg portion and a vertically disposed flat body portion that is perpendicular to a cooling plate adhered to the bottom of the semiconductor unit. A pair of the vertically disposed flat body portions sandwiches a semiconductor chip. Owing to this construction, the heat generated in the semiconductor chip can be conducted away through the both surfaces of the chip, thus improving cooling performance. Since the heat is conducted away through the leg portions of the L-shaped electrically conductive plates a projected planar area occupied by the cooling plate required for cooling the semiconductor unit is reduced. Therefore, the size of the semiconductor unit can be reduced.
    Type: Grant
    Filed: May 16, 2011
    Date of Patent: April 29, 2014
    Assignee: Fuji Electric Co., Ltd.
    Inventor: Kenichiro Sato
  • Publication number: 20140110832
    Abstract: A circuit panel can include contacts exposed at a connection site of a major surface thereof and configured to be coupled to terminals of a microelectronic package. The connection site can define a peripheral boundary on the major surface surrounding a group of the contacts that is configured to be coupled to a single microelectronic package. The group of contacts can include first, second, third, and fourth sets of first contacts. Signal assignments of the first and third sets of first contacts can be symmetric about a theoretical plane normal to the major surface with signal assignments of the respective second and fourth sets of first contacts. Each of the sets of first contacts can be configured to carry identical signals. Each of the sets of first contacts can be configured to carry address information sufficient to specify a location within a memory storage array of the microelectronic package.
    Type: Application
    Filed: March 15, 2013
    Publication date: April 24, 2014
    Applicant: INVENSAS CORPORATION
    Inventor: Invensas Corporation
  • Publication number: 20140091443
    Abstract: A surface mount package of a semiconductor device, has: an encapsulation, housing at least one die including semiconductor material; and electrical contact leads, protruding from the encapsulation to be electrically coupled to contact pads of a circuit board; the encapsulation has a main face designed to face a top surface of the circuit board, which is provided with coupling features designed for mechanical coupling to the circuit board to increase a resonant frequency of the mounted package. The coupling features envisage at least a first coupling recess defined within the encapsulation starting from the main face, designed to be engaged by a corresponding coupling element fixed to the circuit board, thereby restricting movements of the mounted package.
    Type: Application
    Filed: September 19, 2013
    Publication date: April 3, 2014
    Applicants: STMicroelectronics Pte Ltd, STMicroelectronics (Malta) Ltd
    Inventors: Roseanne Duca, Kim-Yong Goh, Xueren Zhang, Kevin Formosa
  • Patent number: 8680668
    Abstract: A device including a semiconductor chip and metal foils. One embodiment provides a device including a semiconductor chip having a first electrode on a first face and a second electrode on a second face opposite to the first face. A first metal foil is attached to the first electrode of the semiconductor chip in an electrically conductive manner. A second metal foil is attached to the second electrode of the semiconductor chip in an electrically conductive manner.
    Type: Grant
    Filed: February 28, 2012
    Date of Patent: March 25, 2014
    Assignee: Infineon Technologies AG
    Inventors: Georg Meyer-Berg, Andreas Schloegl
  • Patent number: 8664755
    Abstract: Disclosed herein is a power module package including: a first substrate; a second substrate having a pad for connection to the first substrate formed on one side or both sides of one surface thereof and having external connection terminals for connection to the outside formed on the other surface thereof; and a lead frame having one end bonded to the first substrate and the other end bonded to the pad of the second substrate to thereby vertically connect the first and second substrates to each other.
    Type: Grant
    Filed: September 28, 2011
    Date of Patent: March 4, 2014
    Assignee: Samsung Electro-Mechanics Co., Ltd
    Inventors: Chang Hyun Lim, Young Ki Lee, Kwang Soo Kim, Seog Moon Choi
  • Patent number: 8656581
    Abstract: A method for fabricating a circuit apparatus includes forming a wiring layer, a conductive layer, and a first insulating layer on the wiring substrate, removing the conductive layer in an opening of the first insulating layer so as to expose the wiring layer, forming a gold plating layer on the wiring layer, removing the first insulating layer and the conductive layer, forming a second insulating layer on the wiring substrate, the second insulating layer having an opening through which the gold plating and adjacent wiring layers are exposed, and electrically connecting a circuit element to the gold plating layer.
    Type: Grant
    Filed: September 21, 2009
    Date of Patent: February 25, 2014
    Assignee: Sanyo Electric Co., Ltd.
    Inventors: Makoto Murai, Yasuhiro Kohara, Ryosuke Usui
  • Patent number: 8653636
    Abstract: A contactless communication medium which can prevent invasion of static electricity and has an outer surface which can satisfy requirements on the flatness thereof. The contactless communication medium has a sealing member including an insulating layer and a conductive layer provided in a stacked manner and having a shape covering an IC module is located such that the insulating layer is on the IC module side. Owing to this, static electricity coming from outside is diffused by the conductive layer and blocked by the insulating layer. Thus, adverse influence of the static electricity on the IC module is prevented. The contactless communication medium can also satisfy the requirements on the flatness of an outer surface thereof.
    Type: Grant
    Filed: August 25, 2010
    Date of Patent: February 18, 2014
    Assignee: Toppan Printing Co., Ltd.
    Inventors: Junsuke Tanaka, Yoshiyuki Mizuguchi
  • Patent number: 8643189
    Abstract: A packaged semiconductor die has a die support mounting surface mounted to a die support having external connectors. A die connection pad surface opposite to die supporting mount surface has associated die connection pads that are circuit nodes of the semiconductor die. The die connection pad surface also has a power rail pad. The power rail pad has a surface area larger than surface areas of the die connection pads. Bond wires electrically couple the power rail pad to two or more of the die connection pads.
    Type: Grant
    Filed: July 17, 2012
    Date of Patent: February 4, 2014
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Boon Yew Low, Navas Khan Oratti Kalandar, Lan Chu Tan
  • Patent number: 8643153
    Abstract: A process for assembling a semiconductor device includes providing a lead frame having a native plane and a plurality of leads having a native lead pitch. The process includes trimming and forming a first subset of the plurality of leads to provide a first row of leads. The process includes trimming and forming a second subset of the plurality of leads to provide a second row of leads. At least one subset of leads is formed with an obtuse angle relative to the native plane such that lead pitch associated with the first or second subset of leads is greater than the native lead pitch.
    Type: Grant
    Filed: May 2, 2012
    Date of Patent: February 4, 2014
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Shunan Qiu, Zhigang Bai, Xuesong Xu, Beiyue Yan, You Ge
  • Patent number: 8637977
    Abstract: A method and apparatus of packaging a semiconductor device with a clip is disclosed. The clip defines a first contact region and a second contact region on a same face of the at least one clip. The chip defines a first face, and a second face opposite to the first face, the first contact region being attached to the first face of the chip and the second contact region being located within a same plane with the second face of the clip.
    Type: Grant
    Filed: June 27, 2013
    Date of Patent: January 28, 2014
    Assignee: Infineon Technologies AG
    Inventors: Boon Huat Lim, Chee Chian Lim, Yoke Chin Goh
  • Patent number: 8637973
    Abstract: A microelectronic component package includes a plurality of electrical leads which are coupled to a microelectronic component and which have exposed lengths extending outwardly beyond a peripheral edge of an encapsulant. A plurality of terminals may be positioned proximate a terminal face of the encapsulant and these terminals may be electrically coupled to the same leads. This can facilitate connection of the microelectronic component to a substrate using the leads as a conventional leaded package. The terminals, however, can facilitate stacking of the leaded package with one or more additional microelectronic components, e.g., a BGA package.
    Type: Grant
    Filed: March 27, 2007
    Date of Patent: January 28, 2014
    Assignee: Micron Technology, Inc.
    Inventors: Eng Meow Koon, Low Siu Waf, Chan Min Yu, Chia Yong Poo, Ser Bok Leng, Zhou Wei
  • Patent number: 8610138
    Abstract: Disclosed is a light emitting diode (LED) package having an array of light emitting cells coupled in series. The LED package comprises a package body and an LED chip mounted on the package body. The LED chip has an array of light emitting cells coupled in series. Since the LED chip having the array of light emitting cells coupled in series is mounted on the LED package, it can be driven directly using an AC power source.
    Type: Grant
    Filed: November 15, 2011
    Date of Patent: December 17, 2013
    Assignee: Seoul Semiconductor Co., Ltd.
    Inventors: Chung Hoon Lee, Keon Young Lee, Hong San Kim, Dae Won Kim, Hyuok Jung Choi
  • Patent number: 8598709
    Abstract: A method and a system for routing electrical connections are disclosed. A semiconductor device includes a first semiconductor chip and a routing plane having a plurality of routing lines. A first connecting line is electrically coupled to the first semiconductor chip and one of the plurality of routing lines and a second connecting line is electrically coupled to the one of the plurality of routing lines and to one of a second semiconductor chip or a first external contact element.
    Type: Grant
    Filed: August 31, 2010
    Date of Patent: December 3, 2013
    Assignee: Infineon Technologies AG
    Inventors: Thorsten Meyer, Gottfried Beer, Christian Geissler, Thomas Ort, Klaus Pressel, Bernd Waidhas, Andreas Wolter
  • Patent number: 8592967
    Abstract: A semiconductor apparatus comprising an integrated semiconductor circuit device having pluralities of electrode pads, pluralities of first external terminals connected to the electrode pads of the integrated semiconductor circuit device, an inductor disposed in a region surrounded by the first external terminals, and a resin portion sealing them, the integrated semiconductor circuit device being arranged on an upper surface of the inductor, and the inductor being exposed from a lower surface of the resin portion together with the first external terminals.
    Type: Grant
    Filed: January 28, 2010
    Date of Patent: November 26, 2013
    Assignee: Hitachi Metals, Ltd.
    Inventor: Tohru Umeno
  • Patent number: 8586857
    Abstract: A combined diode, lead assembly incorporating two expansion joints. The combined diode, lead assembly incorporating two expansion joints includes a diode having a first diode terminal and a second diode terminal, a first conductor and a second conductor. The first conductor includes a first terminal that is electrically coupled to the diode at the first diode terminal and a second terminal that is configured as a first expansion joint, which is configured to electrically couple to a first interconnecting-conductor and is configured to reduce a stress applied to the diode by the first conductor. The second conductor includes a first terminal that is electrically coupled to the diode at the second diode terminal and a second terminal that is configured as a second expansion joint, which is configured to electrically couple to a second interconnecting-conductor and is configured to reduce a stress applied to the diode by the second conductor.
    Type: Grant
    Filed: November 4, 2008
    Date of Patent: November 19, 2013
    Assignee: Miasole
    Inventors: Shawn Everson, Steven T. Croft, Whitfield G. Halstead, Jason S. Corneille
  • Patent number: 8586417
    Abstract: An electronic device package includes a substrate and wire columns arranged in groups about a neutral stress point of the substrate. The height of the wire columns is substantially uniform for the plural groups of wire columns, and a length of at least one of the wire columns is greater than the uniform height. A method of fabricating an electronic device package having a column grid array includes applying two templates on wire columns of the column grid array and bending at least one wire column to increase its length while maintaining a uniform height for the column grid array. In another aspect, an electronic device package substrate includes wire columns having at least one non-uniformity in lengths of the columns, and the length of a wire column corresponds to a distance of that wire column from the neutral stress point of the substrate.
    Type: Grant
    Filed: July 26, 2013
    Date of Patent: November 19, 2013
    Assignee: BAE Systems Information and Electronic Systems Integration Inc.
    Inventors: John A. Hughes, Christy A. Hagerty, Santos Nazario-Camacho, Keith K. Sturcken
  • Patent number: 8575742
    Abstract: A semiconductor device or semiconductor package (e.g., a QFP package) including a uniquely configured leadframe sized and configured to maximize the available number of exposed leads in the semiconductor package, and further to provide one or more power bars in the semiconductor package. More particularly, the semiconductor package of the present invention includes a generally planar die paddle or die pad defining multiple peripheral edge segments. In addition, the semiconductor package includes a plurality of leads. Some of these leads include exposed bottom surface portions which are provided in at least two concentric rows or rings which at least partially circumvent the die pad, with other leads including portions which protrude from respective side surfaces of a package body of the semiconductor package. Connected to the top surface of the die pad is at least one semiconductor die which is electrically connected to at least some of the leads.
    Type: Grant
    Filed: April 6, 2009
    Date of Patent: November 5, 2013
    Assignee: Amkor Technology, Inc.
    Inventors: Wan Jong Kim, Young Tak Do, Byong Woo Cho
  • Publication number: 20130285232
    Abstract: Disclosed herein is a semiconductor package module, including: a circuit board having connection pads formed on one surface thereof; a semiconductor package including lead terminals protruded out of a housing; and an interposer positioned between the circuit board and the semiconductor package, the interposer including a body allowing the circuit board and the semiconductor package to be spaced apart from each other and elastic members contacted with the connection pads and the lead terminals.
    Type: Application
    Filed: July 11, 2012
    Publication date: October 31, 2013
    Applicant: SAMSUNG ELECTRO-MECHANICS CO., LTD.
    Inventor: Job Ha
  • Patent number: 8559238
    Abstract: Embodiments of the present invention relate to configurable inputs and/or outputs for memory and memory stacking applications in processor-based systems. More specifically, embodiments of the present invention include processor-based systems with volatile-memory having memory devices that include a die having a circuit configured for enablement by a particular signal, an input pin configured to receive the particular signal, and a path selector configured to selectively designate a signal path to the circuit from the input pin.
    Type: Grant
    Filed: January 12, 2012
    Date of Patent: October 15, 2013
    Assignee: Round Rock Research, LLC
    Inventor: Jeffrey W. Janzen
  • Patent number: RE44811
    Abstract: The invention relates to a high power LED package, in which a package body is integrally formed with resin to have a recess for receiving an LED chip. A first sheet metal member is electrically connected with the LED chip, supports the LED chip at its upper partial portion in the recess, is surrounded by the package body extending to the side face of the package body, and has a heat transfer section for transferring heat generated from the LED chip to the metal plate of the board and extending downward from the inside of the package body so that a lower end thereof is exposed at a bottom face of the package body thus to contact the board. A second sheet metal member is electrically connected with the LED chip spaced apart from the first sheet metal member for a predetermined gap, and extends through the inside of the package body to the side face of the package body in a direction opposite to the first sheet metal member. A transparent sealant is sealingly filled up into the recess.
    Type: Grant
    Filed: December 19, 2011
    Date of Patent: March 18, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Seon Goo Lee, Chang Wook Kim, Kyung Taeg Han