Abstract: A semiconductor device package and a method of fabricating the same are provided. The semiconductor device package includes a substrate, a first chip, a jumper chip, a plurality of first bonding wires and a plurality of second bonding wires. The substrate has a plurality of contact pads. The first chip is disposed and electrically connected to the substrate via the first bonding wires. The jumper chip is disposed on the first chip and has a plurality of metal pads. Each of the metal pads is electrically connected to two contact pads of the substrate via two second bonding wires, respectively.

Abstract: A method of testing integrated circuit chips. The method includes: attaching integrated circuit chips to an interposer of a temporary carrier, the carrier comprising: a substrate, a first interconnects on a bottom surface and a second array of interconnects on a top surface of the substrate, corresponding first and second interconnects electrically connected by wires in the substrate; the interposer, first pads on a top surface and a second pads on a bottom surface of the interposer, corresponding first and second pads electrically connected by wires in the interposer, and the second pads in physical and electrical contact with corresponding second interconnects; and the interposer including an interposer substrate comprising a same material as a substrate of the integrated circuit chip; connecting interconnects of the first array of interconnects to a tester; and testing the one or more integrated circuit chips.

Abstract: A leadframe design for a diode or other semiconductor device that reduces stress on the device and provides increased heat dissipation is provided. According to various embodiments, the leadframe has a contoured profile including a recessed area and a raised surface within the recessed area. The surface supports the device such that the edges of the device extend past the surface. Also provided are device assemblies including the novel leadframes. In certain embodiments, the assemblies include one or more leadframes attached via a solder joint to a device. According to various embodiments, the leadframes are attached to the front side of the device, back side of the device or both. In particular embodiments, the device is a bypass diode for one or more solar cells in a solar module.

Abstract: Provided is a simplified structure of a circuit device in which a power element generating a large amount of heat is incorporated. The circuit device according to the present invention includes: a circuit board whose surface is covered with an insulating layer; a conductive pattern formed on the surface of the insulating layer; a circuit element electrically connected to the conductive pattern; and a lead connected to a pad formed of the conductive pattern. Furthermore, a power element is fixed to the top surface of a land portion formed of a part of the lead. Accordingly, the land portion serves as a heat sink, thereby contributing to heat dissipation.

Abstract: A semiconductor die package, and methods of making the same. The package includes a leadframe and a clip structure. The clip structure is formed, such that a portion of the clip structure points towards the semiconductor die and is coplanar with the leadframe. The semiconductor die package further includes a housing material covering at least a portion of the leadframe, the semiconductor die, and the clip structure. The housing material has an external recess that holds a portion of the clip structure.

Abstract: A semiconductor device features a semiconductor chip including a MOSFET, a first electrode of the MOSFET disposed on an obverse surface of the chip, a second, control electrode of the MOSFET disposed on the obverse surface, a third electrode of the MOSFET disposed on a second, opposing surface of the chip, first, second, and third conductive members, each having top surface and opposing bottom surface, the first, second, and third conductive members connecting with the first, second, and third electrodes electrically, respectively, a sealing body having top and bottom surfaces and sealing parts of the first, second, and third conductive members, the first conductive member having first, second, and third contiguous portions, the first portion is positioned over the first electrode, the second is positioned between the first and second portions and the third portion is positioned under the obverse surface of the chip.

Abstract: Stacked die assemblies are electrically connected to connection sites on any support, without electrical connection to any interposed substrate or leadframe, and without solder.

Abstract: A board includes a board body; a first conductor provided at a first surface of the board body; and an electrically conductive connection terminal having a spring property. The connection terminal includes a first end part fixed to the first conductor; a second end part to be connected to a first object of connection to be placed opposite the first surface of the board body; and a projection part provided on the first end part so as to project toward the first conductor.

Abstract: The present invention provides a semiconductor device that includes semiconductor packages arranged in a stacked configuration. A plurality of leads are drawn from the stacked semiconductor packages and folded around the outer shape of each semiconductor package such that the leads extend over the upper surfaces of the semiconductor package. Holders affix the stacked semiconductor packages so that first and second leads contact each other, the first leads being drawn from a first one of the stacked semiconductor packages at a lower stacking stage, and the second leads being drawn from a second one of the stacked semiconductor packages at an adjacent, upper stacking stage.

Abstract: A semiconductor arrangement includes first and second integrated circuits (dies), an electrically conductive intermediate element, and one or more bond conductors. The first and the second integrated circuits are arranged in a package. The first integrated circuit has a first contact pad. The second integrated circuit has a second contact pad. The intermediate element is disposed on the second contact pad. The conductors electrically connect the first and the second integrated circuits. At least one of the bond conductors has a first end electrically connected to the first contact pad, and a second wedge shaped end electrically connected to the intermediate element. The bond conductor is made of a first material and the intermediate element is made of a second material which is softer than the first material.

Abstract: An electric sub-assembly has an integrated circuit, which contains at least one power semi-conductor component and additional electronic components, the latter being interconnected and linked to connections by the conductors of a lead frame (1, 2, 3). The lead frame (1, 2, 3) has at least one cooling surface (3), which is connected in a thermally conductive manner to a thermal contact (4) of the integrated circuit or circuits. The cooling surface has a greater surface area than the thermal contact surface (4) of the integrated circuit or circuits and is wider than the parts (1) of the lead frame that are used as electric conductors.

Abstract: When U-shape formed electronic components having an axial lead shape are mounted upright on a printed board, two U-shape formed electronic components having an axial lead shape are arranged so as not to be in the same straight line, and a wiring pattern is formed in a state where bent-side lead wires have the same electric potential, and the electronic components are inclined so as to place the bent-side lead wires close to each other, whereby the electronic components that tend to fall in the inclined direction can be mutually supported by the bent-side lead wires. Thus, the electronic components can be prevented from falling without spoiling a heat dissipation performance of the electronic component and the board, and without greatly deteriorating an assembly performance of the board.

Abstract: A substrate of a micro-BGA package is revealed, primarily comprising a substrate core, a first trace, and a second trace where the substrate core has a slot formed between a first board part and a second board part. The first trace is disposed on the first board part and has a suspended inner lead extended into the slot where the inner lead has an assumed broken point. The second trace is disposed on the second board part and is integrally connected to the inner lead at the assumed broken point. More particularly, a non-circular through hole is formed at the assumed broken point and has two symmetric V-notches away from each other and facing toward two opposing external sides of the inner lead so that the inner lead at two opposing external sides does not have the conventional V-notches cutting into the inner lead from outside. Moreover, the inner lead will not unexpectedly be broken and the inner lead can easily and accurately be broken at the assumed broken point during thermal compression processes.

Abstract: A wiring device for a semiconductor device, a composite wiring device for a semiconductor device and a resin-sealed semiconductor device are provided, each of which is capable of mounting thereon a semiconductor chip smaller than conventional chips and being manufactured at lower cost. The wiring device electrically connects an electrode provided on a semiconductor chip with an external wiring device, and has an insulating layer, a metal substrate and a copper wiring layer. The metal substrate is provided on one side of the insulating layer. The copper wiring layer is provided on another side of the insulating layer. The wiring device has a semiconductor chip support portion provided on the side of the copper wiring layer with respect to the insulating layer. The copper wiring layer includes a first terminal, a second terminal and a wiring portion. The first terminal is connected with the electrode provided on the semiconductor chip. The second terminal is connected with the external wiring device.

Abstract: Provided are a semiconductor package and method of fabricating the same. The package includes an interconnection substrate, a semiconductor chip mounted on the interconnection substrate, a lateral wire bonded on the interconnection substrate and configured to enclose a side surface of the semiconductor chip, and a metal layer disposed on the semiconductor chip and electrically connected to the lateral wire.

Abstract: A semiconductor package and related methods are described. In one embodiment, the package includes a die pad, multiple leads, a chip, a package body, and a protective layer. The die pad includes an upper sloped portion, a lower sloped portion, and a peripheral edge region defining a cavity with a cavity bottom. Each lead includes an upper sloped portion and a lower sloped portion. The chip is disposed on the cavity bottom and is coupled to the leads. The package body is formed over the chip and the leads, substantially fills the cavity, and substantially covers the upper sloped portions of the die pad and the leads. The lower sloped portions of the die pad and the leads at least partially extend outwardly from a lower surface of the package body. The protective layer substantially covers the lower sloped portion and the lower surface of at least one lead.

Abstract: An integrated circuit package system includes: fabricating a lead frame including: providing inner leads having an inner lead pitch of progressive length, forming a lead shoulder, on the inner leads, having a shoulder height of a progressive height, and forming outer leads coupled to the lead shoulder and the inner leads; mounting an integrated circuit die on the lead frame; and molding a package body on the lead frame and the integrated circuit die.

Abstract: A semiconductor device includes a semiconductor chip, a first substrate, and a second substrate. The first substrate includes a plurality of wires and a plurality of first electrodes, each first electrode being connected with each wire. The second substrate includes the semiconductor chip that is mounted thereon, and a plurality of second electrodes with, each second electrode being connected with the each first electrode of the first substrate. The widths of the wires of the first substrate are different depending on the lengths of the wires. By changing the widths of the wires depending on their lengths, it is possible to reduce variation in stiffness of the electrodes and vicinities of electrodes, whereby variation in ultrasonic bonding strength can be reduced.

Abstract: A light emitting device includes a first lead and a second lead. The first lead has a top surface which a light emitting element is mounted thereon and a bottom surface opposed to the top surface. The second lead has a lead peripheral region where a wire connected to an electrode of the light emitting element is bonded therewith. The first lead includes a lead middle region where the semiconductor light emitting element is mounted thereon to thermally conduct therewith. A bottom surface of the lead middle region is exposed from a package. The second lead has an outer lead region that is projected outwardly from the both side surfaces of the package. The bottom surface of the first lead middle region is substantially coplanar with a bottom surface of the outer lead region.

Abstract: A method of manufacture of an integrated circuit packaging system includes: forming an external interconnect; forming a first planar terminal adjacent to the external interconnect and non-planar to a portion the external interconnect; mounting a first integrated circuit over the first planar terminal; connecting the first integrated circuit with the external interconnect; and forming an encapsulation over the first planar terminal covering the first integrated circuit and with the external interconnect extending from a non-horizontal side of the encapsulation and with the first planar terminal coplanar with the adjacent portion of the encapsulation exposing the first planar terminal.

Abstract: Embodiments of the present invention relate to the use of stamping to form features on a lead frame of a semiconductor device package. In one embodiment, portions of the lead frame such as pins are moved out of the horizontal plane of a diepad by stamping. In certain embodiments, indentations or a complex cross-sectional profile, such as chamfered, may be imparted to portions of the pins and/or diepad by stamping. The complexity offered by such a stamped cross-sectional profile serves to enhance mechanical interlocking of the lead frame within the plastic molding of the package body. Other techniques such as selective electroplating and/or formation of a brown oxide guard band to limit spreading of adhesive material during die attach, may be employed alone or in combination to facilitate fabrication of a package having such stamped features.

Abstract: Embodiments of the present invention relate to an improved die layout for a bi-directional and reverse blocking battery switch. According to one embodiment, two switches are oriented side-by-side, rather than end-to-end, in a die package. This configuration reduces the total switch resistance for a given die area, often reducing the resistance enough to avoid the use of backmetal in order to meet resistance specifications. Elimination of backmetal reduces the overall cost of the die package and removes the potential failure modes associated with the manufacture of backmetal. Embodiments of the present invention may also allow for more pin connections and an increased pin pitch. This results in redundant connections for higher current connections, thereby reducing electrical and thermal resistance and minimizing the costs of manufacture or implementation of the die package.

Abstract: Embodiments of the present invention relate to configurable inputs and/or outputs for memory and memory stacking applications. More specifically, embodiments of the present invention include memory devices that include a die having a circuit configured for enablement by a particular signal, an input pin configured to receive the particular signal, and a path selector configured to selectively designate a signal path to the circuit from the input pin.

Abstract: A mounting structure includes: at least one semiconductor device having solder bumps as outer terminals and a flexible wiring board with wiring formed thereon. The semiconductor device is structured to be wrapped by the flexible wiring board, the mounting structure is provided with outer electrodes on both sides of the flexible wiring board, one side being a side where outer terminals of the semiconductor device are formed, and the other side being an opposite side thereof. At least one wiring layer is formed on the flexible wiring board. A supporting member is provided covering side faces and a surface of the semiconductor device opposite to the side where the outer terminals are formed and protruding from the side faces of the semiconductor device and extending toward the surface on which the outer terminals are formed.

Abstract: A non-leaded integrated circuits package system is provided including etching differential height lead structures having inner leads at a paddle height, providing mold locks at the bending points of the differential height lead structures, etching an elevated paddle at a same height as the inner leads, mounting a first integrated circuit on the elevated paddle, and electrically connecting first electrical interconnects between the first integrated circuit and the inner leads.

Abstract: In accordance with the present invention, there is provided a semiconductor package (e.g., a QFP package) including a uniquely configured leadframe sized and configured to maximize the available number of exposed leads in the semiconductor package. More particularly, the semiconductor package of the present invention includes a generally planar die pad or die paddle defining multiple peripheral edge segments. In addition, the semiconductor package includes a plurality of leads. Some of these leads are provided in two concentric rows or rings which at least partially circumvent the die pad, with other leads including portions which protrude from respective side surfaces of a package body of the semiconductor package. Connected to the top surface of the die pad is at least one semiconductor die which is electrically connected to at least some of the leads. At least portions of the die pad, the leads, and the semiconductor die are encapsulated by the package body.

Abstract: A housing for an optoelectronic component is disclosed, having a plastic base body that has a front side with an assembly region for at least one radiation emitting or radiation detecting body, wherein the plastic base body is formed from at least one first plastic component and at least one second plastic component. The second plastic component is disposed on the front side of the plastic base body, and is formed from a material that differs from the first plastic component in at least one optical property, and forms an optically functional region of the plastic base body. Further, a method for producing a housing for an optoelectronic component and a light emitting diode component is disclosed.

Abstract: A housing for a semiconductor component, in which the housing has a plurality of pins which are provided at the edge of the housing at distances, the pins each having a width, a thickness and a length. In order to create a housing for a semiconductor component whose characteristic frequencies are outside a range in which the characteristic frequencies of the housing negatively influence the semiconductor component, either at least one of the distances lies outside the range of 1.24 mm to 1.30 mm, at least one of the widths lies outside the range of 0.33 mm to 0.51 mm, at least one of the thicknesses lies outside the range of 0.23 to 0.32 mm, or at least one of the lengths lies outside the range of 2.05 to 4.12 mm.

Abstract: Semiconductor devices having redundant through-die vias (TDVs) and methods of fabricating the same are described. A substrate is provided having conductive interconnect formed on an active side thereof. Through die vias (TDVs) are formed in the substrate between a backside and the active side thereof. The TDVs include signal TDVs, redundant TDVs (i.e., redundant signal TDVs), and power supply TDVs. The signal TDVs are spaced apart from the redundant TDVs to form a pattern of TDV pairs. The power supply TDVs are interspersed among the TDV pairs. The conductive interconnect includes first signal conductors electrically coupling each of the signal TDVs to a respective one of the redundant TDVs defining a respective one of the TDV pairs.

Abstract: A power block includes an insulating substrate, a conductive pattern formed on the insulating substrate, a power semiconductor chip bonded onto the conductive pattern by lead-free solder, a plurality of electrodes electrically connected to the power semiconductor chip and extending upwardly away from the insulating substrate, and a transfer molding resin covering the conductive pattern, the lead-free solder, the power semiconductor chip, and the plurality of electrodes, wherein surfaces of the plurality of electrodes are exposed at an outer surface of the transfer molding resin and lie in the same plane as the outer surface, the outer surface being located directly above the conductive pattern.

Abstract: A printed circuit board includes a core layer, an insulation layer formed on the core layer and having a cavity formed on a part of the insulation layer, and a circuit pattern formed on the insulation layer, wherein the circuit pattern comprises one or more external terminals positioned above the cavity.

Abstract: A package includes a pad chip having contact pads, a spring chip having micro-springs in contact with the contact pads to form interconnects, the area in which the micro-springs contact the contact pads forming an interconnect area, an assembly material between the pad chip and the spring chip arranged to form a gap between the pad chip and the spring chip, and an underfill material in a portion of the gap to form a mold from the pad chip and the spring chip. A package includes a pad chip having contact pads, a spring chip having micro-springs in contact with the contact pads to form interconnects, the area in which the micro-springs contact the contact pads forming an interconnect area, an assembly material between the pad chip and the spring chip arranged to form a gap between the pad chip and the spring chip, an underfill material in the gap to form a mold from the pad chip and the spring chip, and at least one wall between the underfill material and the interconnect area.

Abstract: An integrated circuit package system is provided including forming a first inner lead having a first inner bottom side and a first outer lead, forming a first side lock of the first inner lead above the first inner bottom side, connecting an integrated circuit die with the first inner lead and the first outer lead, and encapsulating the integrated circuit die and the first side lock.

Abstract: In a power semiconductor module, a semiconductor device including electrode surfaces for connection on its front side and back side is connected on its back side to a first extraction electrode through soldering; a metal surface of one side of a laminated conductor having a laminated structure in which at least two types of metals are laminated is directly, intermetallically connected to the front side of the semiconductor device; a second extraction electrode is connected to a metal surface of another side of the laminated conductor through soldering; and the laminated conductor includes a plurality of arch-like protrusions and a straight section connecting the arch-like protrusions, the straight section is connected with the front side of the semiconductor device, and the protrusions are connected with the second extraction electrode.

Abstract: An IC package primarily includes a chip, a plurality of electrical connecting components, and a chip carrier including a substrate, a die-attaching layer, and at least one bonding wire. The substrate has a top surface and a bottom surface wherein the top surface includes a die-attaching area for being disposed with the die-attaching layer. The chip is attached to the die-attaching area by the die-attaching layer and is electrically connected to the substrate by the electrical connecting components. Both ends of the bonding wire are bonded respectively to two interconnecting fingers on the top surface of the substrate, and at least a portion of the bonding wire is encapsulated in the die-attaching layer such that some wirings or vias formed on a conventional substrate are not needed. Therefore, the substrate can have a simpler structure and fewer numbers of wiring layers; consequently, the substrate cost can be reduced.

Abstract: A fabrication method for a BGA or LGA package includes a low-cost metal leadframe with internally extended leads. I/O attach lands can be placed at any location on the metal leadframe, including the center of the package. An I/O attach land can be fabricated at any position upon an extended lead (e.g., near the center of the package). During fabrication of the package, an isolation saw cut to the bottom of the package can be used to electrically disconnect the leadframe circuit from the peripheral extension traces to prevent tampering with the IC die by probing the edge metal traces.

Abstract: A method for making a premolded clip structure is disclosed. The method includes obtaining a first clip and a second clip, and forming a molding material around the first clip comprising a first surface and the second clip comprising a second surface. The first surface of the first clip structure and the second surface of the second clip structure are exposed through the molding material, and a premolded clip structure is then formed.

Abstract: A multichip module defining a dc to dc converter employs a monolithic chip containing at least two III-nitride switches (a monolithic CSC chip) mounted on a conductive lead frame. The CSC chip is copacked with an IC driver for the switches and with the necessary passives. The module defines a buck converter; a boost converter, a buck boost converter, a forward converter and a flyback converter. The drain, source and gate pads of the monolithic CSC chip are connected to a lead frame by solder or epoxy or by bumping attach and a conductive connector or wire bonds connect the switch terminal to lead frame.

Abstract: A semiconductor device features a semiconductor substrate with a MOSFET, an electrode for main current of the MOSFET disposed on a first major surface of the substrate, an electrode for control of the MOSFET disposed on the first major surface, a rear plane electrode of the MOSFET disposed on a second, opposing surface of the substrate, and an external connection terminal electrically connected to the rear plane electrode, the external electrode contains a first part, a second part and a third part, the first part is positioned over the rear plane electrode, the third part is positioned below the second major surface and the third part is connected via the second part to the first part.

Abstract: The semiconductor device includes a semiconductor element, a lead frame electrically connected to the semiconductor element, and a package having an opening in a front surface with a part of the lead frame protruding from a bottom surface. The protruding lead frame branches into a plurality of end portions, and the end portions are bent to be positioned respectively on a side surface and one of a back surface and a bottom surface of the package.

Abstract: A system and method is disclosed for allowing a solid substrate, such as a printed circuit board (PCB), to act as the support structure for an electronic circuit. In one embodiment, the LEDs which form a part of a scrambler assembly are constructed on a first substrate and the electrical connections are run to the edges of the substrate and end in electrical contacts positioned thereat. The substrate is then connected to the scrambler package by a series of electrical and mechanical connections to form the LED package. The electrical contacts which are part of the LED package extend from the LED package so as to enable electrical contact with a separate controller substrate.

Abstract: A semiconductor device having a plurality of chips is reduced in size. In HSOP (semiconductor device) for driving a three-phase motor, a first semiconductor chip including a pMISFET and a second semiconductor chip including an nMISFET are mounted over each of a first tab, second tab, and third tab. The drains of the pMISFET and nMISFET over each tab are electrically connected with each other. Thus, two of six MISFETs can be placed over each of three tabs divided in correspondence with the number of phases of the motor, and they can be packaged in one in a compact manner. As a result, the size of the HSOP for driving a three-phase motor, having a plurality of chips can be reduced.

Abstract: A method of fabricating a multi-chip package structure is provided. In the method, a number of cavities are formed on a predetermined cutting line of a first wafer by partly removing the first wafer and a first metal layer. Conductive walls of a first circuit layer are electrically connected to a cut cross-section of the first metal layer exposed by the cavities. In addition, conductive bumps of a second wafer are pressed into a cover layer and electrically connected to the first circuit layer. The first metal layer is then patterned to form a second circuit layer having a number of second pads. Next, the first wafer and the second wafer are cut along the predetermined cutting line to form a number of separated multi-chip package structures.

Abstract: A layered chip package has a main body including pairs of layer portions, and wiring disposed on a side surface of the main body. Each layer portion includes a semiconductor chip. The pairs of layer portions include at least one specific pair of layer portions including a first-type layer portion and a second-type layer portion. The first-type layer portion includes electrodes each connected to the semiconductor chip and each having an end face located at the side surface of the main body on which the wiring is disposed, whereas the second-type layer portion does not include such electrodes.

Abstract: A semiconductor package which includes a generally planar die paddle defining multiple peripheral edge segments and a plurality of leads which are segregated into at least two concentric rows. Connected to the top surface of the die paddle is at least one semiconductor die which is electrically connected to at least some of the leads of each row. At least portions of the die paddle, the leads, and the semiconductor die are encapsulated by a package body, the bottom surfaces of the die paddle and the leads of at least one row thereof being exposed in a common exterior surface of the package body.

Abstract: The present disclosure describes a unique pin configuration for mounting of circuit packages to corresponding host circuit boards. For example, an apparatus according to embodiments herein comprises a circuit, a substrate, and multiple conductive leads. The substrate has a surface on which the circuit (e.g., an integrated circuit) is mounted. The multiple conductive leads extend, in an orthogonal manner relative to the surface, through the substrate to electrically connect the circuit to a host circuit board. According to one embodiment, each respective conductive lead of the multiple conductive leads has been altered to produce a contact element (e.g., an L-shaped bend, J-shaped bend, etc.) at an axial end of the respective conductive lead opposite the substrate to solder the axial end of the respective conductive lead (i.e., contact element) to a surface mount pad of the host circuit board.

Abstract: Provided is a light emitting diode package and a method of manufacturing the same. The light emitting diode package includes a package main body with a cavity, a plurality of light emitting diode chips, a wire, and a plurality of lead frames. The plurality of light emitting diode chips are mounted in the cavity. The wire is connected to an electrode of at least one light emitting diode chip. The plurality of lead frames are formed in the cavity, and at least one lead frame is electrically connected to the light emitting diode chip or a plurality of wires.

Abstract: A semiconductor device comprising a plurality of semiconductor chips and a plurality of through-line groups is disclosed. Each of the through-line groups consists of a unique number of through-lines. The numbers associated with the through-line groups are mutually coprime to each other. When one of the through-lines is selected for the each through-line group, one of the semiconductor chip is designated by a combination of the selected through-lines of the plurality of the through-line groups.

Abstract: Two groups of interconnection devices and methods are described. Both provide columns between electronic packages and boards or between chips and substrates or the like. In the first group, called Thermal Flex Contact Carrier (TFCC), the column elements are carved out of a flat laminated structure and then formed to suit. In the second group, the carrier, which carries the connecting elements, is made out of a soluble or removable material, which acts at the same time, as a solder mask, to prevent the solder from wicking along the stem of the elements.

Abstract: The invention relates to a high power LED package, in which a package body is integrally formed with resin to have a recess for receiving an LED chip. A first sheet metal member is electrically connected with the LED chip, supports the LED chip at its upper partial portion in the recess, is surrounded by the package body extending to the side face of the package body, and has a heat transfer section for transferring heat generated from the LED chip to the metal plate of the board and extending downward from the inside of the package body so that a lower end thereof is exposed at a bottom face of the package body thus to contact the board. A second sheet metal member is electrically connected with the LED chip spaced apart from the first sheet metal member for a predetermined gap, and extends through the inside of the package body to the side face of the package body in a direction opposite to the first sheet metal member. A transparent sealant is sealingly filled up into the recess.