Abstract: A cooling device includes a heat sink having a top plate, a bottom plate spaced from the top plate and fins between the top and bottom plates, a first metal member laminated to the side of the top plate that is opposite from the fins, and a first insulator laminated to the first metal member. The top plate, the bottom plate and the first metal member are each made of a clad metal that is composed of a base metal and a brazing metal, so that the fins are brazed to the top and bottom plates, the first metal member is brazed to the top plate, and the first insulator is brazed to the first metal member.

Abstract: A thermal interface material for use in manufacturing a semiconductor component and a method for manufacturing the semiconductor component. The thermal interface material includes a metallic element in combination with either antimony or tin. Suitable metallic elements include gallium or indium. The concentration of antimony or tin is about 2 percent or less by weight of the thermal interface material. A semiconductor chip is mounted to a support substrate and the thermal interface material is disposed on the semiconductor chip. A lid or a heatsink is coupled to the semiconductor chip via the thermal interface material.

Abstract: A semiconductor apparatus includes a first stacked body including a first radiator plate, a first insulating layer, a first conductive layer and a first semiconductor element in this order; a second stacked body including a second radiator plate, a second insulating layer, a second conductive layer and a second semiconductor element in this order and configured to be made of a semiconductor material different from that of the first semiconductor element; and a connecting part configured to electrically connect the first conductive layer and the second conductive layer, wherein the first stacked body and the second stacked body are thermally insulated.

Abstract: A side view light emitting diode (LED) package structure includes a package housing, a side view LED chip and a thermal conductive member. The side view LED chip is enclosed by the package housing and an emitting direction of the side view LED chip is perpendicular to a thickness direction of a substrate. The thermal conductive member connected with the side view LED chip is disposed inside the package housing and a portion of which extends out of a dissipation opening of the package housing to be exposed so that heat of the side view LED chip is dissipated.

Abstract: A multiple element emitter package is disclosed for increasing color fidelity and heat dissipation, improving current control, increasing rigidity of the package assembly. In one embodiment, the package comprises a surface-mount device a casing with a cavity extending into the interior of the casing from a first main surface is provided. A lead frame is at least partially encased by the casing, the lead frame comprising a plurality of electrically conductive parts carrying a linear array of light emitting devices (LEDs). Electrically conductive parts, separate from parts carrying the LEDs have a connection pad, wherein the LEDs are electrically coupled to a connection pad, such as by a wire bond. This lead frame arrangement allows for a respective electrical signal can be applied to each of the LEDs. The emitter package may be substantially waterproof, and an array of the emitter packages may be used in an LED display such as an indoor and/or outdoor LED screen.

Abstract: An integrated circuit package includes a thermally and electrically conductive package lid. The package lid may be in electrical communication with an electrically conductive pad connected to a power plane, ground plane, or signal route in the integrated circuit. The electrically conductive package lid may provide an electrical connection for electrical power or electrical signals or may serve as an electrical ground. In some embodiments, the package lid may include a thermally and electrically conductive material. In other embodiments, the package lid may include an electrically insulative substrate coated on at least one surface with a layer of metal or another conductive material. The conductive layer may be electrically connected to electrical ground, a reference voltage, or a signal pay by at least one electrically conductive via.

Abstract: Embodiments of the present disclosure provide window ball grid array semiconductor packages. A semiconductor package includes a substrate having (i) a first surface, (ii) a second surface that is opposite to the first surface, and (iii) an opening formed between the first surface of the substrate and the second surface of the substrate. The semiconductor package further includes a semiconductor die having (i) a first surface and (ii) a second surface that is opposite to the first surface, the first surface of the semiconductor die being electrically coupled to the second surface of the substrate by one or more interconnect bumps; one or more bonding wires that electrically couple the first surface of the semiconductor die to the first surface of the substrate through the opening of the substrate; and a first electrically insulative structure disposed to substantially fill an area between the first surface of the semiconductor die, the second surface of the substrate, and the one or more interconnect bumps.

Abstract: A semiconductor chip assembly includes a semiconductor device, a heat spreader, a conductive trace and dual adhesives. The heat spreader includes a bump, a base and a ledge. The conductive trace includes a pad and a terminal. The semiconductor device is mounted on the bump in a cavity in the bump, is electrically connected to the conductive trace and is thermally connected to the heat spreader. The bump extends into an opening in the first adhesive and is aligned with and spaced from an opening in the second adhesive. The base and the ledge extend laterally from the bump. The first adhesive is sandwiched between the base and the ledge, the second adhesive is sandwiched between the conductive trace and the ledge and the ledge is sandwiched between the adhesives. The conductive trace is located outside the cavity and provides signal routing between the pad and the terminal.

Abstract: An electric power converter has a semiconductor module having a semiconductor element integrally and at least a pair of semiconductor terminals, a capacitor electrically connected to the semiconductor module, and a cooler that thermally contacts to at least one of a plurality of capacitor terminals provided in the capacitor. The capacitor terminals that thermally contact the cooler are arranged between the cooler and the capacitor.

Abstract: A method of making a semiconductor chip assembly includes providing a bump and a ledge, mounting a first adhesive on the ledge including inserting the bump into an opening in the first adhesive, mounting a conductive layer on the first adhesive including aligning the bump with an aperture in the conductive layer, then flowing the first adhesive between the bump and the conductive layer, solidifying the first adhesive, then providing a heat spreader that includes the bump, a base and the ledge, then mounting a second adhesive on the ledge, mounting a conductive trace that includes a pad and a terminal on the second adhesive, then mounting a semiconductor device on the bump in a cavity in the bump, electrically connecting the semiconductor device to the conductive trace and thermally connecting the semiconductor device to the heat spreader.

Abstract: According to an exemplary embodiment, a bondwireless power module includes a common output pad coupling an emitter/anode node of a high side device to a collector/cathode node of a low side device. The bondwireless power module also includes a high side conductive clip connecting a collector of the high side device to a cathode of the high side device, and causing current to traverse through the high side conductive clip to another high side conductive clip in another power module. The bondwireless power module further includes a low side conductive clip connecting an emitter of the low side device to an anode of the low side device, and causing current to traverse through the low side conductive clip to another low side conductive clip in the another power module. The bondwireless power module can be a motor drive inverter module.

Abstract: According to one embodiment, an electronic apparatus includes a housing, a circuit board in the housing, a heat sink, and a fixing portion. The circuit board includes a heating component. The heat sink has a plate shape and faces the heating component. The fixing portion is attached to the heat sink and fixed to the circuit board at least at two points.

Abstract: A semiconductor package includes a substrate, a stiffener ring coupled to the substrate and configured to form a well with the substrate, and a die positioned in the well. A thermal interface is positioned on the die. A heat spreader is coupled to the stiffener ring so that a portion of the heat spreader is positioned in the well and the thermal interface thermally couples the heat spreader to the die. The portion of the heat spreader positioned in the well adds rigidity to the semiconductor package and facilitates the use of thin dies.

Abstract: A semiconductor device includes a semiconductor module that has a joint surface, a first fitting portion and a second fitting portion provided on the joint surface of the semiconductor module, the second fitting portion having a shape different from the first fitting portion; and a radiating fin that has a joint surface, a third fitting portion and a fourth fitting portion provided on the joint surface of the radiating fin, the fourth fitting portion having a shape different from the third fitting portion. The semiconductor module is bonded to the radiating fin so that the first fitting portion is fitted into the third fitting portion or the third fitting portion is fitted into the first fitting portion, and the second fitting portion is fitted into the fourth fitting portion or the fourth fitting portion is fitted into the second fitting portion.

Abstract: A semiconductor device package is provided. The semiconductor device package includes a laminate comprising a first metal layer disposed on a dielectric film; a plurality of vias extending through the laminate according to a predetermined pattern; one or more semiconductor devices attached to the dielectric film such that the semiconductor device contacts one or more vias; a patterned interconnect layer disposed on dielectric film, said patterned interconnect layer comprising one or more patterned regions of the first metal layer and an electrically conductive layer, wherein a portion of the patterned interconnect layer extends through one or more vias to form an electrical contact with the semiconductor device. The patterned interconnect layer comprises a top interconnect region and a via interconnect region, wherein the package interconnect region has a thickness greater than a thickness of the via interconnect region.

Abstract: A multilayer printed wiring board including a core substrate, a built-up wiring layer having a first surface in contact with the substrate and a second surface, the second surface including a mounting area for mounting a semiconductor device, the built-up layer including circuits and insulating layers, first through-hole conductors formed in a first portion of the substrate which corresponds to the mounting area, second through-hole conductors formed in a second portion of the substrate which corresponds to an area of the second surface other than the mounting area, third through-hole conductors formed in a processor core area of the first portion of the substrate which corresponds to a processor core section of the device, and pads provided on the second surface. The first conductors have a pitch smaller than a pitch of the second conductors, and the third conductors have a pitch smaller than the pitch of the first conductors.

Abstract: A method of making a semiconductor chip assembly includes providing a post, a base, an ESD protection layer and a metal layer, wherein the post extends above the base and the ESD protection layer is sandwiched between the base and the metal layer, mounting an adhesive on the base including inserting the post into an opening in the adhesive, mounting a conductive layer on the adhesive including aligning the post with an aperture in the conductive layer, then flowing the adhesive upward between the post and the conductive layer, solidifying the adhesive, then providing a conductive trace that includes a pad, a terminal and a selected portion of the conductive layer, providing a heat spreader that includes the post, the base, the ESD protection layer and an underlayer that includes at least a portion of the metal layer, then mounting a semiconductor device on the post, electrically connecting the semiconductor device to the conductive trace and thermally connecting the semiconductor device to the heat spreader.

Abstract: A semiconductor chip assembly includes a semiconductor device, a heat spreader, a conductive trace and an adhesive. The heat spreader includes a bump that includes first, second and third bent corners that shape a cavity. The conductive trace includes a pad and a terminal. The semiconductor device is located within the cavity, is electrically connected to the conductive trace and is thermally connected to the bump. The bump extends into an opening in the adhesive and provides a recessed die paddle and a reflector for the semiconductor device. The conductive trace provides signal routing between the pad and the terminal.

Abstract: An LED assembly including a heat sink, a surface treatment dielectric layer, an electrically conductive layer, a thermally conductive layer and an LED chip. The surface treatment dielectric layer is disposed on an upper surface of the heat sink and defines at least one first through hole to expose a portion of the upper surface. The electrically conductive layer is formed on the surface treatment dielectric layer, includes a plurality of electrical traces and defines at least one second through hole corresponding to the first through hole. The thermally conductive layer is formed in the first and the second through holes and directly contacted with a portion of the upper surface exposed from the overlapped region of the first through hole and the second through hole. The LED chip includes a plurality of electrodes electrically connected to the electrical traces and is directly contacted with the thermally conductive layer.

Abstract: A semiconductor chip assembly includes a semiconductor device, a heat spreader, a conductive trace and an adhesive. The heat spreader includes a post, a base, an ESD protection layer and an underlayer. The conductive trace includes a pad and a terminal. The semiconductor device is electrically connected to the conductive trace, electrically isolated from the underlayer and thermally connected to the heat spreader. The post extends upwardly from the base into an opening in the adhesive, the base extends laterally from the post and the ESD protection layer is sandwiched between the base and the underlayer. The conductive trace provides signal routing between the pad and the terminal.

Abstract: A power semiconductor chip (first semiconductor chip) 41 is mounted on the main surface of a first radiator plate 31, and a control IC chip (second semiconductor chip) 42 is mounted on the main surface of a second radiator plate 32. The first radiator plate 31 has an extending portion 31A extending toward the side on which the second radiator plate 32 is provided in the arrangement direction of first lead terminals (lead terminals 21 to 24). The first lead terminals (lead terminals 21 to 24) are connected to a first side of the first radiator plate 31 to function as extraction electrodes of a rear side electrode (D: drain electrode) of the power semiconductor chip 41. A second lead terminal (lead terminal 25) is connected to a bonding pad 411 serving as a source electrode (S). The third lead terminals (lead terminals 26 to 28) are connected to an electrode of the control IC chip 42.

Abstract: A packaged semiconductor device includes a semiconductor die including a substrate having a topside including active circuitry and a bottomside with at least one backside metal layer directly attached. A package including a molding material having a die pad and a plurality of leads is encapsulated within the molding material, wherein the leads include an exposed portion that includes a bonding portion. The topside of the semiconductor die is attached to the die pad, and the package includes a gap that exposes the backside metal layer along a bottom surface of the package. Bond wires couple pads on the topside of the semiconductor die to the leads. The bonding portions, the molding material along the bottom surface of the package, and the backside metal layer are all substantially planar to one another.

Abstract: An electronic package 100 comprising a semiconductor device 105, a heat spreader layer 110, and a thermal interface material layer 115 located between the semiconductor device and the heat spreader layer. The thermal interface material layer includes a resin layer 120 having heat conductive particles 125 suspended therein. A portion of the particles are exposed on at least one non-planar surface 135 of the resin layer such that the portion of exposed particles 130 occupies a majority of a total area of a horizontal plane 140 of the non-planar surface.

Abstract: Various thermal interface structures and methods are disclosed. In one aspect, a method of manufacturing is provided. The method includes providing plural carbon nanotubes in a thermal interface structure. The thermal interface structure is soldered to a side of a semiconductor chip. In another aspect, an apparatus is provided. The apparatus includes a thermal interface structure that has plural carbon nanotubes. A semiconductor chip is soldered to the thermal interface structure.

Abstract: A semiconductor device is provided that may include an insulating substrate having a ceramic substrate and metal coating layers on opposite surfaces of the ceramic substrate, a semiconductor chip mounted on one surface of the insulating substrate, and a heat sink directly or indirectly fixed to the other surface of the insulating substrate and thermally connected to the semiconductor chip through the insulating substrate. The heat sink may include a housing that is made of a metal sheet and radiating fins that are fixed in the housing and made of aluminum. The metal sheet may have a coefficient of thermal expansion between those of the insulating substrate and the radiating fin.

Abstract: A semiconductor device includes a substrate, a semiconductor element disposed on the substrate, a heat radiating plate disposed on the substrate and covering the semiconductor element, and a connection member connecting an upper surface of the semiconductor element and a lower surface of the heat radiating plate, wherein the connection member includes a first member being in contact with the upper surface of the semiconductor element and having a first melting point, a second member being in contact with the first member, having a larger area than the first member, and having a second melting point higher than the first melting point, and a third member interposed between the second member and the heat radiating plate, having an area smaller than the second member, and having a third melting point lower than the second melting point.

Abstract: An integrated circuit package system is provided including forming a wafer having a back side and an active side, forming a recess in the wafer from the back side, forming a cover in the recess, and singulating the wafer at the recess filled with the cover.

Abstract: Embodiments of a microelectronic package are generally described herein. A microelectronic package may include a die having a first side and a second side, opposite the first side, a flange coupled to the first side of the die, and a lead frame proximately positioned relative to the die and coupled to the second side of the die. Other embodiments may be described and claimed.

Abstract: A semiconductor chip assembly includes a semiconductor device, a heat spreader, a conductive trace and first and second adhesives. The heat spreader includes a first post, a second post and a base. The conductive trace includes a pad and a terminal. The semiconductor device is electrically connected to the conductive trace and thermally connected to the heat spreader. The first post extends from the base in a first vertical direction into a first opening in the first adhesive, the second post extends from the base in a second vertical direction into a second opening in the second adhesive and the base is sandwiched between and extends laterally from the posts. The conductive trace provides signal routing between the pad and the terminal.

Abstract: The present invention provide a heat dissipation structure on the active surface of the die to increase the performance of the heat conduction in longitude direction of the semiconductor package device, so that the heat dissipating performance can be improved when the semiconductor package device is associated with the exterior heat dissipation mechanism.

Abstract: A semiconductor device including a semiconductor element 1 having an active element region 1a, a plurality of element electrodes 2 formed on a principal face of the semiconductor element, external terminals 6 and 7 connected to one or more element electrodes via connection members 8 and 9, one or more first heat-dissipation protrusions 4 formed on the principal face of the semiconductor element, an insulation resin layer 10 covering the principal face of the semiconductor element and the first heat-dissipation protrusions, and a heat-dissipation medium 11 contacting a face of the insulation resin layer on a side opposite to a side contacting front faces of the first heat-dissipation protrusions.

Abstract: A semiconductor device includes an insulating substrate having a ceramic substrate and metal coating layers on opposite surfaces of the ceramic substrate, a semiconductor chip mounted on one surface of the insulating substrate, a heat sink directly or indirectly fixed to the other surface of the insulating substrate and thermally connected to the semiconductor chip through the insulating substrate and at least one anti-warping sheet disposed on at least one surface of the heat sink. The anti-warping sheet is made of a metal sheet having a coating layer and has coefficient of thermal expansion between those of the insulating substrate and the heat sink.

Abstract: This invention is to provide an electronic substrate device which is capable of reliably and stably transferring heat generated by a heat generating component to a base member serving as a heat dissipater without intermediation of an electronic substrate.

Abstract: A semiconductor apparatus having a first surface and a second surface opposite to the first surface includes: a semiconductor chip having a front side and a backside; a first heat radiation member electrically and thermally coupled with the backside of the chip; a second heat radiation member electrically and thermally coupled with the front side of the chip; and a resin mold sealing the first and second heat radiation members together with the chip. At least one of the first and second heat radiation members is exposed on both of the first and second surfaces.

Abstract: A semiconductor package includes a semiconductor device 30 and a molded upper heat sink 10. The heat sink has an interior surface 16 that faces the semiconductor device and an exterior surface 15 that is at least partially exposed to the ambient environment of the packaged device. An annular planar base 11 surrounds a raised or protruding central region 12. That region is supported above the plane of the base 11 by four sloped walls 13.1-13.4. The walls slope at an acute angle with respect to the planar annular base and incline toward the center of the upper heat sink 10. Around the outer perimeter of the annular base 11 are four support arms 18.1-18.4. The support arms are disposed at an obtuse angle with respect to the interior surface 16 of the planar annular base 11.

Abstract: Provided is a resin-sealed electronic control device reduced in size, which includes a double-sided mounting board as at least one of a plurality of electronic boards obtained by division so that a large mounting surface with a small plane area is ensured. Each of a first electronic board (30A) and a second electronic board (40A) bonded onto an upper surface and a lower surface of each of a pair of separate beam members (20A) includes two surfaces on which outer circuit components (31, 32, 41, 42) and an inner circuit component (33, 43) are respectively mounted. A height of each of the inner circuit components is equal to or less than a thickness of each of the separate beam members (20A). Heat-generating components (32, 42) in the outer circuit components are provided to be adjacent to and opposed to the separate beam members (20A).

Abstract: A semiconductor package may include at least one semiconductor chip mounted on a substrate, a molding layer adapted to mold the at least one semiconductor chip, a heat slug, on the molding layer, having a structure in which a dielectric is provided between conductors, and a through mold via electrically connecting the heat slug to the substrate.

Abstract: Apparatus may be provided including a high power light emitting diode (LED) unit, at least one printed circuit board, and an interfacing portion of a heat sink structure. The high power LED unit includes at least one LED die, at least one first lead and at least one second lead, and a heat sink interface. The at least one printed circuit board includes a conductive pattern configured to connect both the at least one first lead and the at least one second lead to a current source. The interfacing portion of the heat sink structure is that portion through which a majority of heat of the heat sink interface is transmitted. The interfacing portion is directly in touching contact with a majority of a heat transfer area of the heat sink interface.

Abstract: A heat spreader or lid for a microelectronic package, in which the heat spreader has an underside surface that includes at least one curvilinear contour, in which the curvilinear contour is selected from at least one positive or protruding curvilinear feature, at least one negative or recessed curvilinear feature, and a combination thereof. A microelectronic package that includes the heat spreader/lid, in which there is improved heat dissipation or reduced mechanical stress in an interface between the heat spreader/lid and a circuit chip.

Abstract: A remote control apparatus for remotely operating an electronic device. The remote control apparatus including: an operation section having a plurality of operation keys; and a reader/writer configured to read and/or write information from or to an information storage medium, wherein in said operation section, at least one of the plurality of operation keys is arranged so as to overlap a read/write portion of said reader/writer, the read/write portion being used for the reading and/or writing of the information from or to the information storage medium.

Abstract: A module includes a substrate including a first copper surface and a semiconductor chip. The module includes a first sintered joint bonding the semiconductor chip directly to the first copper surface.

Abstract: The semiconductor assembly includes a first subassembly having a heat sink. Solder material is disposed on the exposed portion of a first surface of heat sink. A power semiconductor die is located on the first surface of the heat sink and is thermally coupled thereto by the solder material. A packaging patterned polymer layer is disposed on a second surface of the heat sink opposing the first surface and defines an interior surface portion of the heat sink. A semiconductor package is provided in which the first subassembly, solder material and die are located such that the interior surface portion of the second surface of the heat sink is not enclosed by the semiconductor package.

Abstract: A system to improve an in-line memory module may include an edging carried by the in-line memory module to stiffen, support, protect, and/or aid in handling the in-line memory module. The system may also include guide ribs carried by the edging to facilitate positioning of the in-line memory module during installation. In one embodiment, the system includes a heat spreader to aid in cooling a plurality of heat sources carried by the in-line memory module. The system may further include a compliant member to regulate the heat spreader's positioning relative to the plurality of heat sources.

Abstract: Disclosed is a heat dissipating circuit board, which includes a metal core including an insulating layer formed on the surface thereof, a circuit layer formed on the insulating layer and including a seed layer and a first circuit pattern, and a heat dissipating frame layer bonded onto the circuit layer using solder and having a second circuit pattern, and in which the heat dissipating frame layer is bonded onto the circuit layer not by a plating process but by using solder, thus reducing the cost and time of the plating process and relieving stress applied to the heat dissipating circuit board due to the plating process. A method of manufacturing the heat dissipating circuit board is also provided.

Abstract: A chip package structure includes a circuit substrate, a chip, at least one bonding wire, and an adhesive layer. The circuit substrate has a bonding surface and at least one pad disposed on the bonding surface. The chip is disposed on the bonding surface of the circuit substrate and has an active surface away from the circuit substrate and at least one contact pad disposed on the active surface. The bonding wire is connected between the contact pad and the pad, such that the chip is electrically connected to the circuit substrate through the bonding wire. The bonding wire includes a copper layer, a nickel layer covering the copper layer, and a gold layer covering the nickel layer. The adhesive layer is disposed between the pad and the bonding wire and between the contact pad and the bonding wire and respectively covers two terminals of the bonding wire.

Abstract: Microprocessor, miniprocessor and heat sink surfaces having increased surface areas and increased heat dissipation are femtosecond pulsed laser machined. Nano structures formed and created on surfaces by the femtosecond pulsed laser machining provide increased surface areas which radiate heat by intensified IR radiation.

Abstract: A frontside of a chip is bonded to a top surface of a chip carrier. Seal material is dispensed at a periphery of the top surface of the chip carrier. A solder TIM having a first side and a second side is provided. The first side of the TIM contacts a backside of the chip. A reflow is performed to melt the TIM. The second side of the TIM is bonded to a lid. The seal material is cured. The lid is attached to the top surface of the chip carrier. Backfill material is injected into a space between the top surface of the chip carrier and the lid. The backfill material abuts sides of the TIM. The backfill material is cured. TIM solder cracking and associated thermal degradation are mitigated.

Abstract: A semiconductor chip assembly includes a semiconductor device, a heat spreader, a conductive trace and an adhesive. The heat spreader includes a post, a base and a ceramic block. The post extends upwardly from the base into an opening in the adhesive, the base extends laterally from the post and the ceramic block is embedded in the post. The semiconductor device overlaps the ceramic block, is electrically connected to the conductive trace and is thermally connected to the ceramic block. The adhesive extends between the post and the conductive trace and between the base and the conductive trace. The conductive trace provides signal routing between a pad and a terminal.

Abstract: A power supply unit of an arc discharge device includes a semiconductor module 1 and a radiator fitted onto the semiconductor module 1. The semiconductor module 1 includes a module casing 2 and common units 3a to 3c retained by the module casing 2. Each of the common units 3a to 3c has: a ceramic substrate 50 having a circuit surface disposed with a semiconductor element 54 and a radiation surface on a side opposite to the circuit surface and a package 35 that exposes the radiation surface and seals the circuit surface with heat resistant resin. The radiator is fitted onto the module casing 2 to be thereby brought into abutting contact with all of the radiation surfaces of the common units 3a to 3c.

Abstract: In the semiconductor device, a control power MOSFET chip 2 is disposed on the input-side plate-like lead 5, and the drain terminal DT1 is formed on the rear surface of the chip 2, and the source terminal ST1 and gate terminal GT1 are formed on the principal surface of the chip 2, and the source terminal ST1 is connected to the plate-like lead for source 12. Furthermore, a synchronous power MOSFET chip 3 is disposed on the output-side plate-like lead 6, and the drain terminal DT2 is formed on the rear surface of the chip 3 and the output-side plate-like lead 6 is connected to the drain terminal DT2. Furthermore, source terminal ST2 and gate terminal GT2 are formed on the principal surface of the synchronous power MOSFET chip 3, and the source terminal ST2 is connected to the plate-like lead for source 13. The plate-like leads for source 12 and 13 are exposed, and therefore, it is possible to increase the heat dissipation capability of the MCM 1.