Directly Attached To Semiconductor Device Patents (Class 257/707)
  • Patent number: 8222729
    Abstract: An electric power converter includes: a heat sink having a heat receiving surface; a semiconductor module including a metal plate having a heat radiation surface, a switching element on the metal plate opposite to the heat radiation surface, and a resin member covering a part of the metal plate and the switching element; a heat radiation member between the heat receiving surface and the semiconductor module for transmitting heat of the switching element to the heat receiving surface via the metal plate. The heat receiving surface includes a concavity, and the heat radiation surface includes a convexity. The heat radiation member has a predetermined area sandwiched between the concavity and the convexity.
    Type: Grant
    Filed: May 19, 2011
    Date of Patent: July 17, 2012
    Assignee: Denso Corporation
    Inventor: Syuhei Miyachi
  • Patent number: 8222730
    Abstract: A semiconductor package is described. The semiconductor package includes a substrate and an integrated heat spreader disposed above and coupled with the substrate. A cavity is disposed between the substrate and the integrated heat spreader. A semiconductor die is disposed above the substrate and in the cavity. An array of first-level solder joints is disposed between the substrate and the semiconductor die. A layer of magnetic particle-based composite material is also disposed in the cavity.
    Type: Grant
    Filed: January 31, 2011
    Date of Patent: July 17, 2012
    Assignee: Intel Corporation
    Inventor: Rajasekaran Swaminathan
  • Patent number: 8217511
    Abstract: An integrated circuit assembly includes a panel including an semiconductor device at least partially surrounded by an encapsulant. A panel upper surface and a device active surface are substantially coplanar. The assembly further includes one or more interconnect layers overlying the panel upper surface. Each of the interconnect layers includes an insulating film having contacts formed therein an interconnect metallization formed thereon. A lower surface of the panel is substantially coplanar with either a backside of the device or a lower surface of a thermally and electrically conductive slab that has an upper surface in thermal contact with the device backside. The assembly may also include a set of panel vias. The panel vias are thermally and electrically conductive conduits extending through the panel between the interconnect layer and suitable for bonding with a land grid array (LGA) or other contact structure of an underlying circuit board.
    Type: Grant
    Filed: July 31, 2007
    Date of Patent: July 10, 2012
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Neil T. Tracht, Darrel R Frear, James R. Griffiths, Lizabeth Ann A. Keser, Tien Yu T. Lee, Elie A. Maalouf
  • Publication number: 20120168932
    Abstract: A semiconductor assembly includes a first subassembly comprising a heat sink and a first patterned polymer layer disposed on a surface of the heat sink to define an exposed portion of the first surface. The exposed portion of the first surface extends radially inward along the heat sink surface from the first layer. The subassembly also includes a second patterned polymer layer disposed on a radially outer portion of the first patterned polymer layer. The first and second layers define a cell for accommodating a power semiconductor die. Solder material is disposed on the exposed portion of the heat sink surface and in the cell. A power semiconductor die is located within the cell on a radially inward portion of the first layer and thermally coupled to the heat sink by the solder material.
    Type: Application
    Filed: March 16, 2012
    Publication date: July 5, 2012
    Applicant: Vishay General Semiconductor LLC
    Inventors: Wan-Lan Chiang, Kuang Hann Lin, Chih-Ping Peng
  • Patent number: 8212343
    Abstract: A semiconductor chip package comprises a lead frame having a chip carrier having a first surface and an opposite second surface. A first semiconductor chip is mounted on the first surface, having a plurality of bonding pads thereon, wherein the first semiconductor chip has an area larger that that of the chip carrier. A package substrate has a central region attached to the second surface of the chip carrier, having an area larger than that of the first semiconductor chip, wherein the package substrate comprises a plurality of fingers on a top surface thereof in a marginal region of the package substrate, which are arranged in an array with a row of inner fingers adjacent to the first semiconductor chip and a row of outer fingers adjacent to an edge of the package substrate, wherein the inner and outer fingers are electrically connected to the bonding pads of the first semiconductor chip and the lead frame respectively.
    Type: Grant
    Filed: September 24, 2010
    Date of Patent: July 3, 2012
    Assignee: Mediatek Inc.
    Inventor: Nan-Jang Chen
  • Patent number: 8207553
    Abstract: A semiconductor chip assembly includes a semiconductor device, a heat spreader, a conductive trace and an adhesive. The heat spreader includes a base. A cavity extends through the adhesive into the base. The semiconductor device extends into the cavity, is electrically connected to the conductive trace and is thermally connected to the heat spreader. The adhesive extends between the cavity and the conductive trace and between the base and the conductive trace. The conductive trace is located outside the cavity and provides signal routing between a pad and a terminal.
    Type: Grant
    Filed: February 26, 2010
    Date of Patent: June 26, 2012
    Assignee: Bridge Semiconductor Corporation
    Inventors: Charles W. C. Lin, Chia-Chung Wang, Sangwhoo Lim
  • Patent number: 8207554
    Abstract: System and method for LED packaging. The present invention is directed to optical devices. More specifically, embodiments of the presentation provide LED packaging having one or more reflector surfaces. In certain embodiments, the present invention provides LED packages that include thermal pad structures for dissipating heat generated by LED devices. In particular, thermal pad structures with large surface areas are used to allow heat to transfer. In certain embodiments, thick thermally conductive material is used to improve overall thermal conductivity of an LED package, thereby allowing heat generated by LED devices to dissipate quickly. Depending on the application, thermal pad structure, thick thermal conductive layer, and reflective surface may be individually adapted in LED packages or used in combinations. There are other embodiments as well.
    Type: Grant
    Filed: September 10, 2010
    Date of Patent: June 26, 2012
    Assignee: Soraa, Inc.
    Inventor: Frank Tin Chung Shum
  • Patent number: 8193633
    Abstract: Provided is a heat conductive sheet obtained by dispersing an inorganic filler in a thermosetting resin, in which the inorganic filler contains secondary aggregation particles formed by isotropically aggregating scaly boron nitride primary particles having an average length of 15 ?m or less, and the inorganic filler contains more than 20 vol % of the secondary aggregation particles each having a particle diameter of 50 ?m or more. The heat conductive sheet is advantageous in terms of productivity and cost and excellent in heat conductivity and electrical insulating properties.
    Type: Grant
    Filed: September 12, 2008
    Date of Patent: June 5, 2012
    Assignee: Mitsubishi Electric Corporation
    Inventors: Kenji Mimura, Hideki Takigawa, Hiroki Shiota, Kazuhiro Tada, Takashi Nishimura, Hiromi Ito, Seiki Hiramatsu, Atsuko Fujino, Kei Yamamoto, Motoki Masaki
  • Patent number: 8193556
    Abstract: A semiconductor chip assembly includes a semiconductor device, a heat spreader, a conductive trace and an adhesive. The heat spreader includes a post and a base. The semiconductor device extends into a cavity in the post, is electrically connected to the conductive trace and is thermally connected to the heat spreader. The post extends upwardly from the base into an opening in the adhesive, and the base extends laterally from the post. The adhesive extends between the post and the conductive trace and between the base and the conductive trace. The conductive trace is located outside the cavity and provides signal routing between a pad and a terminal.
    Type: Grant
    Filed: February 26, 2010
    Date of Patent: June 5, 2012
    Assignee: Bridge Semiconductor Corporation
    Inventors: Charles W. C. Lin, Chia-Chung Wang, Sangwhoo Lim
  • Patent number: 8188594
    Abstract: A high-speed I/O trace is part of an I/O package architecture for an integrated circuit package substrate. The integrated circuit package substrate includes an integrated heat spreader footprint on a die-side and the I/O trace to couple with an IC device to be disposed inside the IHS footprint. The I/O trace includes a pin-out terminal outside the IHS footprint to couple to an IC device to be disposed outside the IHS footprint. The high-speed I/O trace can sustain a data flow rate from a processor in a range from 5 gigabits per second (Gb/s) to 40 Gb/s.
    Type: Grant
    Filed: October 1, 2009
    Date of Patent: May 29, 2012
    Assignee: Intel Corporation
    Inventors: Sanka Ganesan, Kemal Aygun, Chandrashekhar Ramaswamy, Eric Palmer, Henning Braunisch
  • Patent number: 8174112
    Abstract: An integrated circuit device includes an integrated circuit formed in a semiconductor die and an integrated circuit package containing the semiconductor die. The integrated circuit package includes a thermal interface material substantially between the semiconductor die and a heat spreader of the integrated circuit device for conducting heat from the semiconductor die to the heat spreader. The thermal interface material includes diamond particles and has a thickness selected to reduce capacitance between the semiconductor die and the heat spreader over that of a conventional integrated circuit device without reducing the rate of thermal conduction from the semiconductor die to the heat spreader. As a result, the integrated circuit device has improved electrostatic discharge immunity.
    Type: Grant
    Filed: August 20, 2009
    Date of Patent: May 8, 2012
    Assignee: Xilinx, Inc.
    Inventors: James Karp, Vassili Kireev
  • Patent number: 8174832
    Abstract: A structure of a heat dissipation substrate of power LEDs and a device made by using the same overcomes drawbacks such as complex structure of power LEDs, strict manufacturing process, low production efficiency, high production cost, and unreliable product quality. The structure of the heat dissipation substrate includes a one-piece circuit board having a counterbore and metal lines thereon, wherein the counterbore is formed by a through hole and a blind hole communicating with each other. The through hole is smaller than the blind hole, and both of them share the same direction of axis. The heat sink has a one-piece terraced structure formed by a upper terrace and a lower terrace; the heat sink matches the counterbore to form a firm fit.
    Type: Grant
    Filed: October 15, 2008
    Date of Patent: May 8, 2012
    Assignee: Foshan Nationstar Optoelectronics Co., Ltd.
    Inventors: Binhai Yu, Junzheng Li, Xunli Xia
  • Patent number: 8174027
    Abstract: A semiconductor light emitting device, includes: a substrate including a first major surface and a second major surface, the first major surface including a recess and a protrusion, the second major surface being formed on a side opposite to the first major surface; a first electrode provided on the first major surface; a semiconductor light emitting element provided on the first electrode and electrically connected to the first electrode; a second electrode provided on the second major surface; and a through-electrode provided to pass through the substrate at the recess and electrically connect the first electrode and the second electrode.
    Type: Grant
    Filed: October 8, 2009
    Date of Patent: May 8, 2012
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Akihiro Kojima, Yoshiaki Sugizaki
  • Patent number: 8174113
    Abstract: Methods and associated structures of forming an indium containing solder material directly on an active region of a copper IHS is enabled. A copper indium containing solder intermetallic is formed on the active region of the IHS. The solder intermetallic improves the solder-TIM integration process for microelectronic packaging applications.
    Type: Grant
    Filed: September 17, 2008
    Date of Patent: May 8, 2012
    Assignee: Intel Corporation
    Inventors: Abhishek Gupta, Mike Boyd, Carl Deppisch, Jinlin Wang, Daewoong Suh, Brad Drew
  • Patent number: 8168997
    Abstract: Provided is an LED package including a printed circuit board (PCB); a conductive structure that is formed on the PCB and is composed of any one selected from a silicon structure and an aluminum structure; and an LED chip that is mounted on the PCB and is electrically connected to the PCB through the conductive structure.
    Type: Grant
    Filed: August 15, 2008
    Date of Patent: May 1, 2012
    Assignee: Samsung LED Co., Ltd.
    Inventors: Seong Ah Joo, Jung Kyu Park, Kun Yoo Ko, Young June Jeong, Seung Hwan Choi
  • Publication number: 20120098117
    Abstract: An apparatus and method of manufacture may be provided for a package that can be coupled to a common heat sink without external electrical isolation. The apparatus, for example, can include a semi-conductor die comprising at least one electronic device. The apparatus can also include a frame on which a bottom side of the die is mounted, a bottom side of the frame being configured to attach to a printed circuit board. The apparatus can further include a high thermal conductivity resin molded onto a top side of the die.
    Type: Application
    Filed: October 22, 2010
    Publication date: April 26, 2012
    Applicant: RENESAS TECHNOLOGY AMERICA, INC.
    Inventors: Tetsuo SATO, Nobuyoshi MATSUURA, Hiroki ANDO
  • Patent number: 8164182
    Abstract: A semiconductor package system is provided including mounting a semiconductor chip to a substrate having a substrate opening. A first heat slug is attached to a first surface of the semiconductor chip at least partially encapsulating the semiconductor chip. A second heat slug is attached to the second surface of the semiconductor chip through the substrate opening.
    Type: Grant
    Filed: November 14, 2005
    Date of Patent: April 24, 2012
    Assignee: Stats Chippac Ltd.
    Inventors: You Yang Ong, Zurina binti Zukiffly, Saat Shukri bin Embong
  • Patent number: 8159000
    Abstract: Disclosed is a light emitting diode (LED) package having an array of light emitting cells coupled in series. The LED package comprises a package body and an LED chip mounted on the package body. The LED chip has an array of light emitting cells coupled in series. Since the LED chip having the array of light emitting cells coupled in series is mounted on the LED package, it can be driven directly using an AC power source.
    Type: Grant
    Filed: June 14, 2011
    Date of Patent: April 17, 2012
    Assignee: Seoul Semiconductor Co., Ltd.
    Inventors: Chung Hoon Lee, Keon Young Lee, Hong San Kim, Dae Won Kim, Hyuck Jung Choi
  • Patent number: 8154116
    Abstract: A layered chip package includes: a plurality of layer portions stacked, each of the layer portions including a semiconductor chip; and a heat sink. Each of the plurality of layer portions has a top surface, a bottom surface, and four side surfaces. The heat sink has at least one first portion, and a second portion coupled to the at least one first portion. The at least one first portion is adjacent to the top surface or the bottom surface of at least one of the layer portions. The second portion is adjacent to one of the side surfaces of each of at least two of the plurality of layer portions.
    Type: Grant
    Filed: November 3, 2008
    Date of Patent: April 10, 2012
    Assignees: HeadwayTechnologies, Inc., TDK Corporation, SAE Magnetics (H.K.) Ltd.
    Inventors: Yoshitaka Sasaki, Hiroyuki Ito, Tatsuya Harada, Nobuyuki Okuzawa, Satoru Sueki, Hiroshi Ikejima
  • Patent number: 8154871
    Abstract: According to one embodiment, a cooling structure includes a first heat radiating member receiving heat generated by a first heat generating body, and including a plurality of first heat radiating fins projecting toward a second housing, a first flow-in portion provided to the first housing to be open in one of first directions, a second heat radiating member receiving heat generated by a second heat generating body, and including a plurality of second heat radiating fins projecting toward a first housing, and a first flow-out portion provided to the second housing to be open in one of second directions crossing the first directions. The cooling structure includes a cooling fan unit configured to supply the air that has flown from outside to the first heat radiating fins, thereafter supply the air to the second heat radiating fins and cause the air to flow to the outside.
    Type: Grant
    Filed: July 27, 2010
    Date of Patent: April 10, 2012
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Shinichi Kuwahara
  • Patent number: 8154873
    Abstract: A heat dissipation device removing heat from a memory module includes two conducting plate clipping the memory module and an elastic member. Each conducting plate includes a lower part and an upper part. The two lower parts of the two conducting plates abut against two opposite sides of the memory module, respectively. The two upper parts of the two conducting plates are pivotably connected together and located above the memory module. The elastic member is located between the two upper parts and urges the two lower parts towards the memory module. The upper part of each conducting plate is slantwise at an obtuse angle to the lower part to make the two upper parts of the two conducting plates splay upwardly.
    Type: Grant
    Filed: December 3, 2009
    Date of Patent: April 10, 2012
    Assignees: Fu Zhun Precision Industry (Shen Zhen) Co., Ltd., Foxconn Technology Co., Ltd.
    Inventors: Zhi-Sheng Lian, Gen-Ping Deng
  • Patent number: 8148812
    Abstract: A thermal resistor is a metal body having a contact surface to be partially in contact to form a void and is electrically conductive as a whole. The thermal body may be a layered body having a plurality of metal bodies layered so as to be partially in contact with one another to form a void between them, or a metal body having a plurality of convex and concave portions on the surface, or a metal body formed by a plurality of metal plates each having a plurality of creases and layered so that the creases of the adjacent metal plates intersect, or a layered metal body formed by metal plates each having elasticity in the thickness direction and having elasticity in the layered direction as a whole, or metal body having a film formed by a different metal. Also disclosed in a semiconductor device having the thermal resistor inserted between a heating semiconductor element and a case cover and between a heat spreader and the case cover. Also disclosed is an electric device using the device.
    Type: Grant
    Filed: May 10, 2007
    Date of Patent: April 3, 2012
    Assignee: Mitsubishi Electric Corporation
    Inventor: Koji Kise
  • Patent number: 8148805
    Abstract: In one embodiment, the present invention includes a semiconductor package having a substrate with a first surface to support a semiconductor die. A second surface of the substrate includes compliant conductive pads to provide electrical connections to the semiconductor die. In this way, improved connection between the semiconductor package and a socket is provided. Other embodiments are described and claimed.
    Type: Grant
    Filed: March 30, 2011
    Date of Patent: April 3, 2012
    Assignee: Intel Corporation
    Inventors: Qing Zhou, Wei Shi, Daoqiang Lu, Jiangqi He
  • Patent number: 8148747
    Abstract: A semiconductor chip assembly includes a semiconductor device, a heat spreader, a conductive trace and an adhesive. The semiconductor device is electrically connected to the conductive trace and thermally connected to the heat spreader. The heat spreader includes a post, a base and a cap. The post extends upwardly from the base into an opening in the adhesive, the base extends below and laterally from the post, and the cap extends above and laterally from the post. The adhesive extends between the post and the conductive trace and between the base and the conductive trace. The conductive trace provides signal routing between a pad and a terminal and the heat spreader provides thermal dissipation between the cap and the base.
    Type: Grant
    Filed: November 28, 2009
    Date of Patent: April 3, 2012
    Assignee: Bridge Semiconductor Corporation
    Inventors: Charles W. C. Lin, Chia-Chung Wang, David M. Sigmond
  • Publication number: 20120068186
    Abstract: An electronic device includes a carrier, a plurality of pins, and an electronic circuit that includes a first semiconductor chip and a second semiconductor chip. The first semiconductor chip is attached to the carrier and the second semiconductor chip is attached to one of the plurality of pins.
    Type: Application
    Filed: September 17, 2010
    Publication date: March 22, 2012
    Inventor: Ralf Otremba
  • Patent number: 8138597
    Abstract: A semiconductor assembly includes a first subassembly comprising a heat sink and a first patterned polymer layer disposed on a surface of the heat sink to define an exposed portion of the first surface. The exposed portion of the first surface extends radially inward along the heat sink surface from the first layer. The subassembly also includes a second patterned polymer layer disposed on a radially outer portion of the first patterned polymer layer. The first and second layers define a cell for accommodating a power semiconductor die. Solder material is disposed on the exposed portion of the heat sink surface and in the cell. A power semiconductor die is located within the cell on a radially inward portion of the first layer and thermally coupled to the heat sink by the solder material.
    Type: Grant
    Filed: November 4, 2010
    Date of Patent: March 20, 2012
    Assignee: Vishay General Semiconductor LLC
    Inventors: Wan-Lan Chiang, Kuang Hann Lin, Chih-Ping Peng
  • Patent number: 8134077
    Abstract: Disclosed is a heat dissipating circuit board, which includes a metal core including an insulating layer formed on the surface thereof, a circuit layer formed on the insulating layer and including a seed layer and a first circuit pattern, and a heat dissipating frame layer bonded onto the circuit layer using solder and having a second circuit pattern, and in which the heat dissipating frame layer is bonded onto the circuit layer not by a plating process but by using solder, thus reducing the cost and time of the plating process and relieving stress applied to the heat dissipating circuit board due to the plating process. A method of manufacturing the heat dissipating circuit board is also provided.
    Type: Grant
    Filed: November 7, 2009
    Date of Patent: March 13, 2012
    Assignee: Samsung Electro-Mechanics Co., Ltd.
    Inventors: Hye Sook Shin, Seog Moon Choi, Shan Gao, Chang Hyun Lim, Tae Hyun Kim, Young Ki Lee
  • Patent number: 8134231
    Abstract: A semiconductor chip, including: a substrate including an front surface; an integrated circuit formed on the front surface and including a plurality of semiconductor elements; and a heat-radiating plug formed in a region of the substrate corresponding to at least one of the semiconductor elements. The heat-radiating plug is made of a material having a thermal conductivity greater than that of the substrate formed in a non-penetrating hole having its opening on a reverse surface of the substrate.
    Type: Grant
    Filed: January 5, 2009
    Date of Patent: March 13, 2012
    Assignee: Panasonic Corporation
    Inventors: Hikari Sano, Yoshihiro Tomita, Takahiro Nakano
  • Patent number: 8129742
    Abstract: A semiconductor chip assembly includes a semiconductor device, a heat spreader, a conductive trace and an adhesive. The heat spreader includes a post and a base. The conductive trace includes a pad, a terminal and a plated through-hole. The semiconductor device is electrically connected to the conductive trace and thermally connected to the heat spreader. The post extends upwardly from the base into an opening in the adhesive, and the base extends laterally from the post. The conductive trace provides signal routing between the pad and the terminal using the plated through-hole.
    Type: Grant
    Filed: April 2, 2011
    Date of Patent: March 6, 2012
    Assignee: Bridge Semiconductor Corporation
    Inventors: Charles W. C. Lin, Chia-Chung Wang
  • Publication number: 20120050996
    Abstract: A semiconductor package includes a substrate, a stiffener ring coupled to the substrate and configured to form a well with the substrate, and a die positioned in the well. A thermal interface is positioned on the die. A heat spreader is coupled to the stiffener ring so that a portion of the heat spreader is positioned in the well and the thermal interface thermally couples the heat spreader to the die. The portion of the heat spreader positioned in the well adds rigidity to the semiconductor package and facilitates the use of thin dies.
    Type: Application
    Filed: August 31, 2010
    Publication date: March 1, 2012
    Applicant: STMICROELECTRONICS ASIA PACIFIC PTE LTD.
    Inventor: Kum Weng Loo
  • Patent number: 8125077
    Abstract: A semiconductor package includes an encapsulant, a semiconductor device within the encapsulant, and one or more terminals for electrically coupling the semiconductor device to a node exterior to the package. The package further includes bonding means coupling the semiconductor device to the one or more terminals. The semiconductor package is configured to dissipate heat through a top surface of the package. To directly dissipate heat via the top surface of the package, a thermally conductive layer is coupled to the semiconductor device, and the layer is exposed at a surface of the package.
    Type: Grant
    Filed: August 25, 2010
    Date of Patent: February 28, 2012
    Assignee: Utac Thai Limited
    Inventors: Saravuth Sirinorakul, Somchai Nondhasitthichai
  • Patent number: 8125076
    Abstract: A semiconductor package system is provided including: providing a substrate having substrate wiring and a cavity provided therein with a heat sink foil closing off the cavity; attaching a semiconductor die in the cavity to the heat sink foil; and bonding the semiconductor die to the substrate wiring.
    Type: Grant
    Filed: November 10, 2005
    Date of Patent: February 28, 2012
    Assignee: Stats Chippac Ltd.
    Inventors: Gwang Kim, Koo Hong Lee
  • Patent number: 8125075
    Abstract: A method, apparatus and system with a semiconductor package including a microchimney or thermosiphon using carbon nanotubes to modify the effective thermal conductivity of an integrated circuit die.
    Type: Grant
    Filed: January 15, 2008
    Date of Patent: February 28, 2012
    Assignee: Intel Corporation
    Inventors: James G. Maveety, Gregory M. Chrysler, Unnikrishnan Vadakkanmaruveedu
  • Patent number: 8120170
    Abstract: An integrated circuit package employs a stiffener layer that houses a passive electronic component to maintain mechanical properties when a thinner substrate is used. The use of either a retention wall or a stiffener allows for the manufacture of these integrated circuit package using strip, matrix, or array technology where a larger board with a plurality of integrated circuit packages is produced industrially and then cut to individual units.
    Type: Grant
    Filed: April 28, 2008
    Date of Patent: February 21, 2012
    Assignee: ATI Technologies ULC
    Inventors: Neil R. McLellan, Vincent K. Chan, Roden R. Topacio
  • Patent number: 8115303
    Abstract: Semiconductor package structures are provided which are designed to have liquid coolers integrally packaged with first level chip modules. In particular, apparatus for integrally packaging a liquid cooler device within a first level chip package structure include structures in which a liquid cooler device is thermally coupled directly to the back side of an integrated circuit chip flip-chip mounted on flexible chip carrier substrate. The liquid cooler device is mechanically coupled to the package substrate through a metallic stiffener structure that is bonded to the flexible package substrate to provide mechanical rigidity to the flexible package substrate.
    Type: Grant
    Filed: May 13, 2008
    Date of Patent: February 14, 2012
    Assignee: International Business Machines Corporation
    Inventors: Raschid Jose Bezama, Evan George Colgan, Michael Gaynes, John Harold Magerlein, Kenneth C. Marston, Xiaojin Wei
  • Patent number: 8115301
    Abstract: Methods for fabricating flip-chips are disclosed. In an exemplary method, a flip-chip is mounted, active-surface downward, onto a substrate such that a back-side of the flip-chip is facing upward and electrical connections are made between the chip and an upward-facing surface of the substrate. An adhesive is applied to selected regions not occupied by the flip-chip. A heat-spreader is applied to contact the applied adhesive without contacting the back-side of the flip-chip, leaving a gap between the heat-spreader and the back-side of the flip-chip. The heat-spreader defines at least one through-hole that, when the heat-spreader is placed, is within a perimeter of the flip-chip. The adhesive is cured, and a thermal-insulating material (TIM) is applied through the at least one through-hole so as to fill the gap with the TIM. The methods substantially reduce the probability of die damage that otherwise occurs during attachment of heat-spreaders.
    Type: Grant
    Filed: November 17, 2006
    Date of Patent: February 14, 2012
    Assignee: STATS ChipPAC, Inc.
    Inventors: KyungOe Kim, YoungJoon Kim, HyunSoo Shin
  • Patent number: 8115291
    Abstract: Provided is a semiconductor package including a first substrate including a first substrate pad and a second substrate pad spaced apart from each other, first semiconductor chips stacked on the first substrate and having a first side surface and a second side surface, first chip pads disposed on the first substrate pad and adjacent to the first side surface and provided to the respective first semiconductor chips in the peripheral circuit region and electrically connected to the first substrate pad, and a second semiconductor chip disposed toward the second side surface and including a second chip pad spaced apart from the first chip pad and electrically connected to the second substrate pad, and a heat insulation member provided to the first substrate between the at least one first substrate pad and the at least one second substrate pad.
    Type: Grant
    Filed: July 31, 2009
    Date of Patent: February 14, 2012
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Joonghyun Baek, Sungjun Im, Heejin Lee
  • Patent number: 8106501
    Abstract: A semiconductor die package. The semiconductor die package comprises a semiconductor die and a molded clip structure comprising a clip structure and a first molding material covering at least a portion of the clip structure. The first molding material exposes an outer surface of the clip structure. The clip structure is electrically coupled to the semiconductor die. The semiconductor die package further comprises a leadframe structure comprising a die attach pad and a plurality of leads extending from the die attach pad. The semiconductor die is on the die attach pad of the leadframe structure. A second molding material covers at least a portion of the semiconductor die and the leadframe structure. The semiconductor die package also includes a heat slug and a thermally conductive material coupling the heat slug to the exposed surface of the clip structure.
    Type: Grant
    Filed: December 12, 2008
    Date of Patent: January 31, 2012
    Assignee: Fairchild Semiconductor Corporation
    Inventors: Maria Clemens Y. Quinones, Maria Cristina B. Estacio
  • Patent number: 8102047
    Abstract: A load driving device includes: an output power device for driving a load; a driving IC for controlling the output power device, wherein the driving IC is electrically coupled with the output power device through a wire or a connection member; and a first electrode substrate. The output power device and the driving IC are mounted on the first electrode substrate. In this case, the output power device is controlled with high speed, and a mounting area of the output power device and the driving IC is reduced.
    Type: Grant
    Filed: May 27, 2010
    Date of Patent: January 24, 2012
    Assignee: DENSO CORPORATION
    Inventors: Satoshi Shiraki, Akira Yamada, Hiroyuki Ban
  • Patent number: 8097814
    Abstract: A mounting region is provided at an approximately center of one surface of an insulating layer. A conductive trace is formed so as to outwardly extend from inside of the mounting region. A cover insulating layer is formed in the periphery of the mounting region so as to cover the conductive trace. A terminal of the conductive trace is arranged in the mounting region, and a bump of an electronic component is bonded to the terminal. A metal layer made of copper, for example, is provided on the other surface of the insulating layer. A slit is formed in the metal layer so as to cross a region being opposite to the electronic component and to divide the metal layer.
    Type: Grant
    Filed: January 20, 2009
    Date of Patent: January 17, 2012
    Assignee: Nitto Denko Corporation
    Inventors: Yasuto Ishimaru, Hirofumi Ebe
  • Patent number: 8089146
    Abstract: A semiconductor device includes a semiconductor element mounted on a substrate; at least one electronic part arranged around the semiconductor element; and a heat radiation member bonded to a backside of the semiconductor element by a bonding material. The heat radiation member has an isolation part extending between an outer circumference of the semiconductor element and the electronic part.
    Type: Grant
    Filed: January 29, 2010
    Date of Patent: January 3, 2012
    Assignee: Fujitsu Limited
    Inventor: Kenji Fukuzono
  • Patent number: 8089085
    Abstract: An LED assembly can include a heat sink base, at least one LED die attached to the heat sink base, and a lens. One or more layers of phosphor can be formed upon the lens. A heat sink, such as a finned heat sink, can attach the heat sink base to the lens. Heat from the LED die can flow through the heat sink base to the heat sink, from which the heat can be dissipated. Similarly, heat from phosphors can flow through the lens to the heat sink, from which the heat can be dissipated. By removing heat from the LED die, more current can be used to drive the LED die, thus providing brighter light. By removing heat from the phosphors, desired colors can be more reliably provided.
    Type: Grant
    Filed: February 26, 2009
    Date of Patent: January 3, 2012
    Assignee: Bridgelux, Inc.
    Inventor: Wei Shi
  • Patent number: 8084856
    Abstract: In some embodiments, a thermal spacer for stacked die package thermal management is presented. In this regard, an apparatus is introduced having a top integrated circuit die, a bottom integrated circuit die, and a thermal spacer between the top and bottom integrated circuit dice, the thermal spacer comprising a heat conducting material and the thermal spacer overhanging and extending parallel with one outside edge of the bottom integrated circuit die. Other embodiments are also disclosed and claimed.
    Type: Grant
    Filed: March 26, 2010
    Date of Patent: December 27, 2011
    Assignee: Intel Corporation
    Inventor: Xuejiao Hu
  • Patent number: 8080870
    Abstract: A back-side lamination (BSL) is applied after thinning a microelectronic die. The BSL is configured to be a thermal-expansion complementary structure to a metal wiring interconnect layout that is disposed on the active side of the microelectronic die.
    Type: Grant
    Filed: June 18, 2009
    Date of Patent: December 20, 2011
    Assignee: Intel Corporation
    Inventor: Chuan Hu
  • Patent number: 8080866
    Abstract: In a three-dimensional chip configuration, a heat spreading material may be positioned between adjacent chips and also between a chip and a carrier substrate, thereby significantly enhancing heat dissipation capability. Furthermore, appropriately sized and positioned through holes in the heat spreading material may enable electrical chip-to-chip connections, while responding thermally conductive connectors may extend to the heat sink without actually contacting the corresponding chips.
    Type: Grant
    Filed: July 21, 2009
    Date of Patent: December 20, 2011
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Thomas Werner, Michael Grillberger, Frank Feustel
  • Patent number: 8081460
    Abstract: A liquid-cooled heat radiator 1 includes a heat radiation base 2 having a cooling-liquid channel 5, and an expansion tank 7 provided on the heat radiation base 2. The expansion tank 7 has a tank body 26 having an expanded portion 27, which expands upward and opens downward, and a bottom plate 28 joined to the lower end of the tank body 26 to thereby close a bottom opening of the expanded portion 27. A through-hole 29 is formed in the top wall of the expanded portion 27 of the tank body 26 and serves as a communication section for establishing communication between the interior and the exterior of the cooling-liquid channel 5. A hydrogen-permeable member 31 is fixedly fitted into the through-hole 29 so as to stop the through-hole 29. The hydrogen-permeable member 31 satisfies the relation B?50 A, where A and B are water-vapor permeability and hydrogen permeability, respectively, of the hydrogen-permeable member 31.
    Type: Grant
    Filed: January 23, 2007
    Date of Patent: December 20, 2011
    Assignees: NEC Corporation, Showa Denko K.K.
    Inventors: Tomotaka Ishida, Mitsuru Yamamoto, Sakae Kitajo, Kazuhiro Kumakura
  • Patent number: 8077466
    Abstract: A heat sink 109 is configured by a plate component having a combined structure composed of a recess and a projection formed thereon, wherein the recess is formed by allowing a part of the plate component to be set back from the surface level of the residual region, and the projection is formed on one surface of the plate component with the progress of formation of the recess, so as to be built up above the level of the residual region of the one surface.
    Type: Grant
    Filed: July 19, 2010
    Date of Patent: December 13, 2011
    Assignee: NEC Electronics Corporation
    Inventor: Harumi Mizunashi
  • Patent number: 8076771
    Abstract: In order to reduce a thermal stress applied by a metal cap to a semiconductor chip: a semiconductor chip (2) is bonded to a flat portion (11) of a metal cap (1); side wall portions of the metal cap (1) serve as external connection terminals (13); and a slit (7) is formed in the metal cap (1) so as to cross the semiconductor chip (2), so a bonding region between the semiconductor chip (2) and the metal cap (1) is divided into small bonding regions to reduce thermal stresses applied to the respective bonding regions. Therefore, peeling can be prevented in respective bonding regions, whereby a small-size semiconductor device in which the semiconductor chip is bonded to the metal cap with improved bonding reliability is obtained.
    Type: Grant
    Filed: June 26, 2008
    Date of Patent: December 13, 2011
    Assignee: Renesas Electronics Corporation
    Inventor: Hideko Ando
  • Patent number: 8076772
    Abstract: A printed circuit board, a memory module having the same, and a fabrication method thereof. The printed circuit board includes an interconnection substrate on which electronic components are mounted and in which a plurality of signal lines are arranged. The signal lines are electrically coupled to the electronic components. A heat sink is disposed on one surface of the interconnection substrate to dissipate heat of the electronic components, and in which no signal lines are arranged. The printed circuit board includes a bending substrate coupling the interconnection substrate to the heat sink, and formed of a flexible material configured to be bent.
    Type: Grant
    Filed: June 25, 2008
    Date of Patent: December 13, 2011
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Hyung-Mo Hwang, Yong-Hyun Kim, Jung-Chan Cho, Hyun-Seok Choi
  • Patent number: 8071997
    Abstract: An more efficient or higher luminance LED assembly may be formed from a high power LED chip having a first surface, and a second surface, the first surface being mounted to a substrate; the second surface being in intimate thermal contact with a light transmissive heat sink having a thermal conductivity greater than 30 watts per meter-Kelvin. The LED chip is otherwise in electrical contact with at least a first electrical connection and a second electrical connection for powering the LED chip. Providing light transmissive heat sink can double the heat conduction from the LED dies thereby increasing life, or efficiency or luminance or a balance of the three.
    Type: Grant
    Filed: October 6, 2006
    Date of Patent: December 6, 2011
    Assignee: OSRAM SYLVANIA Inc.
    Inventors: Adam M. Scotch, George C. Wei