Directly Attached To Semiconductor Device Patents (Class 257/707)
  • Patent number: 8064202
    Abstract: A sandwich structure and method thereof is disclosed for double-sided cooling, EMI noise shielding and current carrying in mini-modules. The proposed structure comprises a top structure and a bottom structure to achieve double-sided cooling. Meanwhile, the top structure is configured to shield EMI noises as well. The proposed structure further comprises a first set of connecting structures for connecting devices of the mini-modules with the top structure and a second set of connecting structure for connecting the top structure with the bottom structure. The connecting structures are capable of carrying current.
    Type: Grant
    Filed: February 24, 2010
    Date of Patent: November 22, 2011
    Assignee: Monolithic Power Systems, Inc.
    Inventors: Jian Yin, Hunt H. Jiang, Kaiwei Yao
  • Patent number: 8062933
    Abstract: A heat dissipating package structure includes a chip carrier; a semiconductor chip mounted and electrically connected to the chip carrier; an encapsulant formed on the chip carrier and for encapsulating the chip, with a non-active surface of the chip being exposed from the encapsulant; and a heat spreader having a hollow portion and attached to the encapsulant, wherein the chip is received in the hollow portion and the non-active surface of the chip is completely exposed to the hollow portion, such that heat generated by the chip can be directly dissipated out of the package structure. The present invention also provides a method for fabricating the heat dissipating package structure.
    Type: Grant
    Filed: December 12, 2007
    Date of Patent: November 22, 2011
    Assignee: Siliconware Precision Industries Co., Ltd.
    Inventors: Chien-Ping Huang, Cheng-Hsu Hsiao
  • Patent number: 8058724
    Abstract: Various semiconductor chip thermal management systems and methods are disclosed. In one aspect, a method of manufacturing is provided that includes coupling a semiconductor chip to a substrate and coupling a diamond heat spreader that has a thermoelectric cooler to the semiconductor chip. A vapor chamber is coupled to the diamond heat spreader.
    Type: Grant
    Filed: November 30, 2007
    Date of Patent: November 15, 2011
    Assignee: ATI Technologies ULC
    Inventor: Gamal Refai-Ahmed
  • Patent number: 8053814
    Abstract: An apparatus comprises a first layer within a semiconductor chip having active structures electrically connected to other active structures and having electrically isolated first inactive structures. A second layer within the semiconductor chip is physically connected to the first layer. The second layer comprises an insulator and has second inactive structures. The first inactive structures are physically aligned with the second inactive structures.
    Type: Grant
    Filed: April 8, 2009
    Date of Patent: November 8, 2011
    Assignee: International Business Machines Corporation
    Inventors: Fen Chen, Jeffrey P. Gambino, Alvin W. Strong
  • Patent number: 8053872
    Abstract: The present invention integrates a shield on a flat, no-lead (FN) semiconductor package, which has multiple rows of contact pads along any side. The FN semiconductor package will have at least one inner row and one outer row of contact pads on at least one side. The inner and outer rows of contact pads and a die attach pad form the foundation for the FN semiconductor package. A die is mounted on the die attach pad and connected by wirebonds to certain contact pads of the inner rows of contact pads. An overmold body is formed over the die, die attach pad, wirebonds, and inner row of contact pads, and substantially encompasses each contact pad of the outer row of contact pads. A conformal coating is applied over the overmold body, including the exposed surfaces of the contact pads of the outer row of contact pads, providing a shield.
    Type: Grant
    Filed: June 25, 2007
    Date of Patent: November 8, 2011
    Assignee: RF Micro Devices, Inc.
    Inventors: Geoff Swan, Waite R. Warren, Jr.
  • Patent number: 8050054
    Abstract: A base plate for a heat sink comprises a cooling plate and spacer elements, which are arranged on the surface of the cooling plate. The spacer elements and the cooling plate are made as one piece and the material in the surface region of the cooling plate and of the spacer elements being the same and formed in the same process.
    Type: Grant
    Filed: December 19, 2007
    Date of Patent: November 1, 2011
    Assignee: ABB Technology AG
    Inventors: Makan Chen, Daniel Schneider, Raymond Zehringer
  • Patent number: 8044427
    Abstract: This invention relates to the thermal management, extraction of light, and cost effectiveness of Light Emitting Diode, or LED, electrical circuits. An integrated circuit LED submount is described, for the packaging of high power LEDs. The LED submount provides high thermal conductivity while preserving electrical insulation. In particular, a process is described for anodizing a high thermal conductivity aluminum alloy sheet to form a porous aluminum oxide layer and a non-porous aluminum oxide layer. This anodized aluminum alloy sheet acts as a superior electrical insulator, and also provides surface morphology and mechanical properties that are useful for the fabrication of high-density and high-power multilevel electrical circuits.
    Type: Grant
    Filed: June 24, 2008
    Date of Patent: October 25, 2011
    Assignee: DiCon Fiberoptics, Inc.
    Inventors: Wen-Herng Su, Junying Lu, Ho-Shang Lee
  • Patent number: 8030756
    Abstract: A plastic ball grid array semiconductor package employs a metal heat spreader having supporting arms embedded in the molding cap, in which the embedded supporting arms are not directly affixed to the substrate or in which any supporting arm that is affixed to the substrate is affixed using a resilient material such as an elastomeric adhesive. Also, a process for forming the package includes steps of placing the heat spreader in a mold cavity, placing the substrate over the mold cavity such that the die support surface of the substrate contacts the supporting arms of the heat spreader, and injecting the molding material into the cavity to form the molding cap. The substrate is positioned in register over the mold cavity such that as the molding material hardens to form the mold cap the embedded heat spreader becomes fixed in the appropriate position in relation to the substrate.
    Type: Grant
    Filed: April 6, 2007
    Date of Patent: October 4, 2011
    Assignee: Chippac, Inc.
    Inventors: Taekeun Lee, Flynn Carson, Marcos Karnezos
  • Patent number: 8030758
    Abstract: A semiconductor module (10) includes a heat sink (1), an electronic component (2), a semiconductor device (3), and a thermally-conductive sheet member (4). The thermally-conductive sheet member (4) covers a part of the semiconductor device (3) and has a lower part (4b) and a side part (4c). The lower part (4b) is in contact with a mounting face (11a) of the heat sink (1). The side part (4c) extends from the lower part (4b) and covers a first side surface (3c) of the semiconductor device (3). The electronic component (2) is disposed across the side part (4c) of the thermally-conductive sheet member (4) from the semiconductor device (3).
    Type: Grant
    Filed: September 13, 2007
    Date of Patent: October 4, 2011
    Assignee: Panasonic Corporation
    Inventor: Makoto Kitabatake
  • Patent number: 8030759
    Abstract: A heat conductive plate structure includes a base metal plate having a seating portion; a coupling layer disposed above the base metal plate around the seating portion; an electric conduction layer disposed above the coupling layer around the seating portion to define a clearance therebetween; a coupling film disposed above the electric conduction layer and the seating portion to define an inner clearance in communication with the clearance of the electric conduction layer and an outer clearance surrounding the inner clearance; a non-weldable material for inserting into the inner clearance and the outer clearance in the coupling film; a heat conduction member disposed on a central portion of the coupling film; an electric conduction member disposed above the coupling film to surround the heat conduction member from an exterior thereof; and a high power element mounted above so as to be in direct contact with the heat conduction member and the electric conduction member simultaneously.
    Type: Grant
    Filed: April 17, 2009
    Date of Patent: October 4, 2011
    Inventors: Yu-Wei Wang, Hung-Sheng Lin
  • Patent number: 8022532
    Abstract: An interposer and a semiconductor device including the interposer, which can prevent thermal warpage of an insulative substrate. The interposer is provided with a semiconductor chip in a semiconductor device and may be disposed between the semiconductor chip and a mount board. The interposer includes: a substrate of an insulative resin; an island on one surface of the substrate to be bonded to a rear surface of the chip; a thermal pad on the other surface opposite the one surface opposed to the island with the intervention of the substrate; and a thermal via extending through the substrate from the one surface to the other surface to thermally connect the island to the thermal pad.
    Type: Grant
    Filed: June 2, 2006
    Date of Patent: September 20, 2011
    Assignee: Rohm Co., Ltd.
    Inventors: Yasumasa Kasuya, Sadamasa Fujii, Motoharu Haga
  • Patent number: 8022531
    Abstract: An integrated circuit package system includes a substrate having an integrated circuit die thereon; a heat slug having a tie bar, the tie bar having characteristics of singulation from an adjacent heat slug; and an encapsulant molded on the substrate, the heat slug, and the integrated circuit die includes the encapsulant which fills all of the space between the integrated circuit die and the heat slug.
    Type: Grant
    Filed: September 13, 2010
    Date of Patent: September 20, 2011
    Assignee: STATS ChipPAC Ltd.
    Inventors: Kyungsic Yu, Tae Keun Lee, Youngnam Choi
  • Patent number: 8018723
    Abstract: A heat dissipation system for use with an electronic module is provided. The electronic module includes a first side with a first plurality of electronic components mounted thereon and a second side with a second plurality of electronic components mounted thereon. The heat dissipation system includes a first segment mountable on the module to be in thermal communication with at least one electronic component of the first plurality of electronic components. The system further includes a second segment mountable on the module to be in thermal communication with at least one electronic component of the second plurality of electronic components. The system includes a third segment mountable on the module to be in thermal communication with the first segment and with the second segment, the third segment providing a path through which heat flows from the first segment to the second segment.
    Type: Grant
    Filed: April 29, 2009
    Date of Patent: September 13, 2011
    Assignee: Netlist, Inc.
    Inventors: Enchao Yu, Zhiyong An
  • Patent number: 8018072
    Abstract: A semiconductor device has a substrate. A die is attached to a first surface of the substrate. A heat sink is provided having an approximately planer member and support members extending from the planer member. The support members are attached to the first surface of the substrate to form a cavity over the die with the planer member positioned above the die. An encapsulant is provided for encapsulating the device, wherein an exterior surface of the planer member is exposed. A non-tapered opening is formed in the planer member. The encapsulant is injected through the opening to encapsulate the cavity and the encapsulant will partially fill the non-tapered opening.
    Type: Grant
    Filed: December 23, 2008
    Date of Patent: September 13, 2011
    Assignee: Amkor Technology, Inc.
    Inventors: Jeffrey A. Miks, Jui Min Lim
  • Patent number: 8018050
    Abstract: An IC package and methods for making the same are described. The IC package includes a die and a heat sink that is attached to the back surface of the die with a thermal interface material layer. The heat sink includes a base and a partition. The partition extends around the periphery of the base and is offset from the outer edge of the base such that a ledge region is formed that surrounds the periphery of the base. The inner surfaces of the partition define an inner region that includes heat dissipation structures. A molding material encapsulates at least portions of the die and the ledge region around the periphery of the heat sink while leaving the inner region of the heat sink unencapsulated by molding material and exposed. The molding material covering the ledge region provides a locking feature that secures the heat sink in the package.
    Type: Grant
    Filed: November 1, 2007
    Date of Patent: September 13, 2011
    Assignee: National Semiconductor Corporation
    Inventors: You Chye How, Shee Min Yeong
  • Patent number: 8018051
    Abstract: Disclosed are systems and methods for improving the thermal performance of integrated circuit packages. Aspects of the present invention include improved thermal package structures and methods for producing the same through the application of one or more thermal spreaders in the package. In embodiments, a thermal spreader is incorporated in a semiconductor chip package between a semiconductor die and its die pad. By including a thermal spreader in an IC package, the package can handle higher levels of power while maintaining approximately the same temperature of the package or can reduce the temperature of the package when operating at the same power level, as compared to a package without a thermal spreader.
    Type: Grant
    Filed: February 2, 2009
    Date of Patent: September 13, 2011
    Assignee: Maxim Integrated Products, Inc.
    Inventors: Tarak A. Railkar, Steven D. Cate
  • Patent number: 8013437
    Abstract: A semiconductor package includes an encapsulant, a semiconductor die within the encapsulant, and a terminal for electrically coupling the semiconductor die to a node exterior to the package. The package further includes solder coupling the semiconductor die to the terminal. The semiconductor package is configured to dissipate heat through a top surface of the package. To directly dissipate heat via the top surface of the package, a portion of the semiconductor die is preferably exposed at the top surface of the package. Alternatively, instead of having a semiconductor device or die directly exposed at a surface of the package, a layer of thermally conductive material is coupled to the semiconductor device, and the layer is exposed at a surface of the package.
    Type: Grant
    Filed: September 4, 2007
    Date of Patent: September 6, 2011
    Assignee: Utac Thai Limited
    Inventors: Saravuth Sirinorakul, Somchai Nondhasitthichai
  • Patent number: 8013438
    Abstract: A semiconductor package includes a substrate board and a semiconductor die attached to a top surface of that substrate board. A heat spreader is provided over the semiconductor die. A stiffening ring is positioned surrounding the semiconductor die, the stiffening ring being attached to the top surface of the substrate board and attached to a bottom surface of the plate portion of the heat spreader. Space is left on the board outside of the stiffening ring to support the installation of passive components to the substrate board. An external ring may be included, with that external ring being interconnected to the stiffening ring by a set of tie bars. Alternatively, the heat spreader includes an integrally formed peripheral sidewall portion.
    Type: Grant
    Filed: July 21, 2009
    Date of Patent: September 6, 2011
    Assignee: STMicroelectronics Asia Pacific Pte. Ltd.
    Inventors: Jing-En Luan, Kum-Weng Loo
  • Patent number: 8014152
    Abstract: This invention is to provide an electronic substrate device which is capable of reliably and stably transferring heat generated by a heat generating component to a base member serving as a heat dissipater without intermediation of an electronic substrate.
    Type: Grant
    Filed: June 8, 2009
    Date of Patent: September 6, 2011
    Assignee: Mitsubishi Electric Corporation
    Inventors: Yoshitake Nishiuma, Koji Hashimoto
  • Patent number: 8006747
    Abstract: A semiconductor die is constructed and arranged to have at least one conduit portion therein. At least a portion of the conduit portion is proximate to the localized area. The conduit portion is at least partially filled with a heat-dissipating material. The conduit portion absorbs heat from the localized area and dissipates at least a portion of the heat away from the localized area.
    Type: Grant
    Filed: January 8, 2009
    Date of Patent: August 30, 2011
    Assignee: Intel Corporation
    Inventors: Gregory M. Chrysler, James G. Maveety
  • Patent number: 8008131
    Abstract: The invention provides semiconductor chip packages, tools, and methods for preventing and for correcting leadfinger deformation caused during wirebonding in semiconductor chip package manufacturing. Disclosed are improved heat blocks and methods for their use in ensuring adequate clearance between leadfingers and adjacent heat spreaders, as well as semiconductor chip package assemblies wherein a selected clearance between leadfingers and parallel surfaces may be assured. Methods of the invention include steps for supporting the proximal ends of the leadfingers using the wirebonding cavity of a heat block. Thus supported, a plurality of bondwires are attached to couple bond pads of the semiconductor chip to the proximal ends of leadfingers. Thereafter, the clearance between the wirebonded proximal ends of the leadfingers and the adjacent parallel surface of the heat spreader is adjusted using a spacing cavity of the heat block.
    Type: Grant
    Filed: March 26, 2008
    Date of Patent: August 30, 2011
    Assignee: Texas Instruments Incorporated
    Inventors: Chien-Te Feng, Kevin Jin
  • Patent number: 8003496
    Abstract: A semiconductor device is made by forming a heat spreader over a temporary carrier. A semiconductor die is mounted to the heat spreader. A first polymer layer is formed over the semiconductor die and heat spreader. A first conductive layer is formed over the first polymer layer. The first conductive layer is connected to the heat spreader and contact pads on the semiconductor die. A second polymer layer is formed over the first conductive layer. A second conductive layer is formed over the second polymer layer. The second conductive layer is electrically connected to the first conductive layer. Bumps are formed through a solder masking layer on the second conductive layer. The temporary carrier is removed. The heat spreader dissipates heat from the semiconductor die and provides shielding from inter-device interference. The heat spreader is grounded through the first and second conductive layers.
    Type: Grant
    Filed: August 14, 2009
    Date of Patent: August 23, 2011
    Assignee: STATS ChipPAC, Ltd.
    Inventors: JiHoon Oh, SinJae Lee, JinGwan Kim
  • Patent number: 8004080
    Abstract: A module has a substrate, first and second integrated circuits, and a heat sink. The integrated circuits each have a first major surface, a second major surface, a first edge, a second edge, and a third edge and have optical circuits having ports on the first edge and electronic circuits having ports on the second edge. The second edges are connected to the substrate. The first major surface of the second integrated circuit is parallel with the second major surface of the first integrated circuit. The heat sink has a backplane adjacent to the third edge, a first portion along the first major surface of the first integrated circuit, a second portion along the second major surface of the second integrated circuit extending from the backplane, and an insert between the first major surface of the second integrated circuit and the second major surface of the first integrated circuit.
    Type: Grant
    Filed: September 4, 2009
    Date of Patent: August 23, 2011
    Assignee: Freescale Smeiconductor, Inc.
    Inventors: Michael B. McShane, Perry H. Pelley
  • Patent number: 8004079
    Abstract: A chip package structure includes a substrate, a chip, a thermal conductive layer, a plurality of signal contacts, and a molding compound. The substrate includes a plurality of first thermal conductive vias, a connecting circuit, and a plurality of signal vias electrically connected to the connecting circuit, and the substrate has a chip disposing region. The chip is disposed on the chip disposing region of the substrate and electrically connected to the signal vias through the connecting circuit. The thermal conductive layer is disposed over the substrate, connected to the first thermal conductive vias, and located above the chip disposing region. Besides, the thermal conductive layer has first openings exposing the signal vias. The signal contacts are respectively disposed in the first openings and connected to the signal vias. The molding compound encapsulates the chip.
    Type: Grant
    Filed: May 13, 2009
    Date of Patent: August 23, 2011
    Assignee: Industrial Technology Research Institute
    Inventors: Ra-Min Tain, Yu-Lin Chao, Shu-Jung Yang, Rong-Chang Fang, Wei Li, Chih-Yuan Cheng, Ming-Che Hsieh
  • Patent number: 7999372
    Abstract: Provided is an organic light emitting display device. An organic light emitting display device according to one embodiment of the present invention comprises a first substrate; a second substrate comprising an interior surface opposing the first substrate; an array of organic light emitting pixels formed between the first and second substrates, the array comprising a top surface facing the second substrate; a frit seal interposed between the first and second substrates while surrounding the array; and a film structure comprising one or more layered films, the film structure comprising a portion interposed between the array and the second substrate, the film structure contacting the interior surface and the top surface; and wherein the second substrate comprises a recess on interior surface.
    Type: Grant
    Filed: September 29, 2006
    Date of Patent: August 16, 2011
    Assignee: Samsung Mobile Display Co., Ltd.
    Inventor: Jin-Woo Park
  • Patent number: 7994635
    Abstract: To suppress warpage of a ceramic substrate, and to prevent a reduction in radiation efficiency. A power semiconductor module includes a module casing fitted with a radiator, and a common unit retained by the module casing. The common unit has: a ceramic substrate having a circuit surface disposed with a semiconductor element, and a radiation surface brought into abutting contact with the radiator; and a package formed by exposing the radiation surface and sealing the circuit surface with heat resistant resin. The circuit surface and the radiation surface are respectively formed of metal layers 51 formed on the ceramic substrate, and the metal layer 51 forming the radiation surface has: by forming a buffer pattern 512 including a groove part extending along a circumferential part thereof, a radiation pattern 510 formed on an inner side of the buffer pattern 512; and an outer peripheral pattern 511 formed on an outer side of the buffer pattern 512.
    Type: Grant
    Filed: May 18, 2007
    Date of Patent: August 9, 2011
    Assignee: Sansha Electric Manufacturing Co., Ltd.
    Inventors: Osamu Soda, Yuji Ohnishi, Kazunori Inami, Toshio Uchida
  • Patent number: 7991029
    Abstract: A cut-out portion of a ground conductor is located in a region where a header faces a flexible board from the junction of a signal pin and a signal line and faces the signal line. The size of the cut-out portion is determined so that the impedance of the signal pin is matched to the impedance of the signal line.
    Type: Grant
    Filed: August 12, 2008
    Date of Patent: August 2, 2011
    Assignee: Mitsubishi Electric Corporation
    Inventor: Hiroshi Aruga
  • Patent number: 7977162
    Abstract: A semiconductor device includes a semiconductor chip, and a multicomponent alloy layer formed on a face of the semiconductor chip, the multicomponent alloy layer being in a solid-liquid coexisting state in a specific temperature range, and including a surface having concavity and convexity caused by solidification segregation.
    Type: Grant
    Filed: July 9, 2008
    Date of Patent: July 12, 2011
    Assignee: Seiko Epson Corporation
    Inventor: Naoki Komukai
  • Patent number: 7968979
    Abstract: An integrated circuit package system includes: providing a substrate with an integrated circuit mounted thereover; mounting a structure, having ground pads, over the integrated circuit; encapsulating the integrated circuit with an encapsulation while leaving the structure partially exposed; and attaching a conformal shielding to the encapsulation and electrically connected to the grounding pads.
    Type: Grant
    Filed: June 25, 2008
    Date of Patent: June 28, 2011
    Assignee: Stats Chippac Ltd.
    Inventors: Reza Argenty Pagaila, Linda Pei Ee Chua, Byung Tai Do
  • Patent number: 7968999
    Abstract: A method of grounding a heat spreader/stiffener to a flip chip package comprising the steps of attaching an adhesive film to a substrate and attaching a stiffener to the adhesive film. The adhesive film may have a number of first holes corresponding with a number of grounding pads on the substrate. The grounding pads may be configured to provide electrical grounding. The stiffener may have a number of second holes corresponding with the number of first holes of the adhesive film and number the grounding pads of the substrate. The grounding pads are generally exposed through the first and the second holes.
    Type: Grant
    Filed: February 28, 2008
    Date of Patent: June 28, 2011
    Assignee: LSI Corporation
    Inventors: Zeki Z. Celik, Zafer S. Kutlu, Vishal Shah
  • Patent number: 7968982
    Abstract: A semiconductor package includes a semiconductor device 30 and a molded upper heat sink 10. The heat sink has an interior surface 16 that faces the semiconductor device and an exterior surface 15 that is at least partially exposed to the ambient environment of the packaged device. An annular planar base 11 surrounds a raised or protruding central region 12. That region is supported above the plane of the base 11 by four sloped walls 13.1-13.4. The walls slope at an acute angle with respect to the planar annular base and incline toward the center of the upper heat sink 10. Around the outer perimeter of the annular base 11 are four support arms 18.1-18.4. The support arms are disposed at an obtuse angle with respect to the interior surface 16 of the planar annular base 11.
    Type: Grant
    Filed: July 10, 2008
    Date of Patent: June 28, 2011
    Assignee: Fairchild Semiconductor Corporation
    Inventors: Chung-Lin Wu, Rajeev D. Joshi
  • Patent number: 7965508
    Abstract: A cooling device for cooling an electronic component (semiconductor module) includes a cooling tube adapted to be disposed in contact with the electronic component and having an internal coolant flow channel for the passage therethrough of a cooling medium, and a high-pressure tube disposed adjacent to a surface of the cooling tube that faces away from the electronic component, the high-pressure tube having a hollow interior that can be filled with a high-pressure fluid having a pressure higher than that of the cooling medium. An electric power conversion device comprised of a plurality of semiconductor modules and the cooling device as means for cooling the semiconductor modules is also disclosed.
    Type: Grant
    Filed: March 26, 2008
    Date of Patent: June 21, 2011
    Assignee: Denso Corporation
    Inventors: Takeshi Yamamoto, Seiji Inoue, Yoshiaki Fukatsu
  • Patent number: 7964951
    Abstract: A semiconductor device includes first and second stacked semiconductor dies on a substrate. A lid having a plurality of fins extending downwardly into the cavity is mounted on the substrate to encapsulate the semiconductor dies. At least some of the fins are longer than other ones of said fins. The lid is attached to the substrate, with the longer fins extending downwardly above a region of the substrate not occupied by the first die. The shorter fins extend downwardly above a region of said first die not covered by said second die. A thermal interface material fills the remainder of the cavity and is in thermal communication with both dies, the substrate and the fins. The lid may be molded from metal. The lid may be bonded to the topmost die, using a thermal bonding material that may be liquid metal, or the like.
    Type: Grant
    Filed: March 16, 2009
    Date of Patent: June 21, 2011
    Assignee: ATI Technologies ULC
    Inventor: Gamal Refai-Ahmed
  • Patent number: 7961469
    Abstract: Embodiments of the present invention provide a system for distributing a thermal interface material. The system includes: an integrated circuit chip; a heat sink; and a compliant thermal interface material (TIM) between the integrated circuit chip and the heat sink. During assembly of the system, a mating surface of the heat sink and a mating surface of the integrated circuit chip are shaped to distribute the TIM in the predetermined pattern as the TIM is pressed between the mating surface of heat sink and a corresponding mating surface of the integrated circuit chip.
    Type: Grant
    Filed: March 31, 2009
    Date of Patent: June 14, 2011
    Assignee: Apple Inc.
    Inventors: Chad C Schmidt, Richard Lidio Blanco, Jr., Douglas L Heirich, Michael D Hillman, Phillip L Mort, Jay S Nigen, Gregory L Tice
  • Publication number: 20110133328
    Abstract: A semiconductor device and a method of manufacturing the same are disclosed. The semiconductor device includes: a casing, a board and a semiconductor chip. The chip includes: an element part; a heat sink bonded to the element part; an insulting layer located on the heat sink so that the heat sink is located between the element part and the insulating layer; and a side wall insulating layer covering all of end faces of the heat sink. The semiconductor chip is located between the casing and the board, so that the insulating layer is directed to the casing to enable heat radiation from the heat sink toward the casing via the insulating layer.
    Type: Application
    Filed: February 10, 2011
    Publication date: June 9, 2011
    Applicant: DENSO CORPORATION
    Inventor: Takeshi MIYAJIMA
  • Patent number: 7956456
    Abstract: An electronic package comprising a semiconductor device, a heat spreader layer, and a thermal interface material layer located between the semiconductor device and the heat spreader layer. The thermal interface material layer includes a resin layer having heat conductive particles suspended therein. A portion of the particles are exposed on at least one non-planar surface of the resin layer such that the portion of exposed particles occupies a majority of a total area of a horizontal plane of the non-planar surface.
    Type: Grant
    Filed: February 27, 2008
    Date of Patent: June 7, 2011
    Assignee: Texas Instruments Incorporated
    Inventors: Siva Prakash Gurrum, Paul Joseph Hundt, Vikas Gupta
  • Patent number: 7948076
    Abstract: A semiconductor chip assembly includes a semiconductor device, a heat spreader, a substrate and an adhesive. The semiconductor device is electrically connected to the substrate and thermally connected to the heat spreader. The heat spreader includes a post and a base. The post extends upwardly through an opening in the adhesive into an aperture in the substrate, and the base extends laterally and supports the substrate. The adhesive extends between the post and the substrate and between the base and the substrate. The substrate includes first and second conductive layers and a dielectric layer therebetween, and the assembly provides vertical signal routing between a pad at the first conductive layer and a terminal below the adhesive.
    Type: Grant
    Filed: September 11, 2009
    Date of Patent: May 24, 2011
    Inventors: Chia-Chung Wang, Charles W. C. Lin
  • Patent number: 7944045
    Abstract: A semiconductor module and a method of manufacturing the same are disclosed including a semiconductor element having an electrode, a heat radiation plate placed in thermal contact with a main surface of the semiconductor element and electrically connected to the electrode thereof, an insulation body directly formed on an outside surface of the heat radiation plate, a metallic body directly formed on an outside surface of the insulation body and having a thickness lower than that of the insulation body, and a mold resin unitarily molding the heat radiation plate, the semiconductor element and the insulation body. The insulation body is covered with the metallic body and the mold resin and the metallic body has an outside surface exposed to an outside of the mold resin.
    Type: Grant
    Filed: March 4, 2009
    Date of Patent: May 17, 2011
    Assignee: Denso Corporation
    Inventors: Chikage Noritake, Takanori Teshima, Kuniaki Mamitsu
  • Patent number: 7943430
    Abstract: A semiconductor device and a method for manufacturing the same are described. The semiconductor device comprises: a heat sink having at least one opening passing through the heat sink; at least one semiconductor chip disposed in the opening, wherein the semiconductor chip includes a first side and a second side on opposite sides; an electricity conducting thin film filling in a first depth portion of the opening, wherein the second side of the semiconductor chip is embedded in the electricity conducting thin film; a heat conducting thick film filling in a second depth portion of the opening, wherein the electricity conducting thin film is directly connected with the heat conducting thick film; at least one wire electrically connecting the semiconductor chip and an external circuit; and an encapsulant covering a portion of the heat sink, the semiconductor chip, the wire and an exposed portion of the electricity conducting thin film.
    Type: Grant
    Filed: July 10, 2008
    Date of Patent: May 17, 2011
    Inventor: Kuan-Chun Chen
  • Patent number: 7939368
    Abstract: A wafer level chip scale package system is provided forming a wafer having an interconnect provided on an active side, forming a thermal sheet having a first thermal interface material layer and a thermal conductive layer, and attaching the thermal sheet on a non-active side of the wafer.
    Type: Grant
    Filed: March 7, 2006
    Date of Patent: May 10, 2011
    Assignee: Stats Chippac Ltd.
    Inventors: Seng Guan Chow, Byung Tai Do, Heap Hoe Kuan
  • Patent number: 7939922
    Abstract: In one embodiment, the present invention includes a semiconductor package having a substrate with a first surface to support a semiconductor die. A second surface of the substrate includes compliant conductive pads to provide electrical connections to the semiconductor die. In this way, improved connection between the semiconductor package and a socket is provided. Other embodiments are described and claimed.
    Type: Grant
    Filed: April 20, 2009
    Date of Patent: May 10, 2011
    Assignee: Intel Corporation
    Inventors: Qing Zhou, Wei Shi, Daoqiang Lu, Jiangqi He
  • Patent number: 7928564
    Abstract: A method for fabricating a multichip module package includes providing a first heat sink positioned for releasing heat from the package and providing a second heat sink positioned proximate the first heat sink. The heat sinks are thermally coupled and electrically isolated to and from one another. A first semiconductor device is attached to the first heat sink in thermal and electrical communication therewith and electrically insulated from the second heat sink. A second semiconductor device is attached to the second heat sink in thermal and electrical communication therewith and electrically insulated from the first heat sink.
    Type: Grant
    Filed: September 24, 2008
    Date of Patent: April 19, 2011
    Assignee: Stats Chippac Ltd.
    Inventors: Il Kwon Shim, Dario S. Filoteo, Jr., Tsz Yin Ho, Sebastian T. M. Soon
  • Patent number: 7928559
    Abstract: A semiconductor element is provided with a heat dissipating path defined by a non-through hole in a first principal surface and that is filled with a conductive material. The semiconductor element is bonded to a heat sink with the conductive material disposed therebetween. Solder can be used as the conductive material, for example. By introducing molten solder into the non-through hole while having solder disposed between the semiconductor element and the heat sink, the heat dissipating path is provided and the heat sink is bonded to the semiconductor element.
    Type: Grant
    Filed: November 25, 2008
    Date of Patent: April 19, 2011
    Assignee: Murata Manufacturing Co., Ltd.
    Inventor: Hideo Nakagoshi
  • Patent number: 7929307
    Abstract: A memory module assembly includes a plurality of memory modules and a heat sink assembly. Each of the memory modules includes at least one heat source. The heat sink assembly includes a heat dissipating plate and a plurality of heat transfer mediums. Each of the heat transfer mediums includes a base attached to the heat dissipating plate, and at least one resilient sheet extending from an end of the base. The base and the resilient sheet define an included angle which is non-right angle so that the resilient sheet can snugly clip to the respective heat source.
    Type: Grant
    Filed: November 29, 2009
    Date of Patent: April 19, 2011
    Inventor: Ming-Yang Hsieh
  • Patent number: 7930658
    Abstract: A semiconductor integrated circuit device and a fabrication method thereof are disclosed, for effective suppression of a temperature increase therein that is caused by heat generation of a semiconductor element. The semiconductor integrated circuit device includes a semiconductor element, a multi-layer wiring structure and a heat conduction part. The semiconductor element is formed on a support substrate. The multi-layer wiring structure is formed in an insulation film on the support substrate and includes at least one connection hole and at least one metal wiring layer. The heat conduction part is formed of the same conductive materials as the connection hole and the metal wiring layer and extends toward an upper layer side along a path different from a wiring path including a connection hole and a metal wiring for signal transmission.
    Type: Grant
    Filed: September 29, 2008
    Date of Patent: April 19, 2011
    Assignee: Ricoh Company, Ltd.
    Inventor: Keiichi Yoshioka
  • Patent number: 7928562
    Abstract: An apparatus to reduce a thermal penalty of a three-dimensional (3D) die stack for use in a computing environment is provided and includes a substrate installed within the computing environment, a first component to perform operations of the computing environment, which is coupled to the substrate in a stacking direction, a set of second components to perform operations of the computing environment, each of which is coupled to the first component and segmented with respect to one another to form a vacated region, a thermal interface material (TIM) disposed on exposed surfaces of the first and second components, and a lid, including a protrusion, coupled to the substrate to overlay the first and second components such that the protrusion extends into the vacated region and such that surfaces of the lid and the protrusion thermally communicate with the first and second components via the TIM.
    Type: Grant
    Filed: July 22, 2008
    Date of Patent: April 19, 2011
    Assignee: International Business Machines Corporation
    Inventors: Amilcar R. Arvelo, Evan G. Colgan, John H. Magerlein, Kenneth C. Marston, Kathryn C. Rivera, Kamal K. Sikka, Jamil A. Wakil, Xiaojin Wei, Jeffrey A. Zitz
  • Patent number: 7928565
    Abstract: A semiconductor device having a higher thermal dissipation efficiency includes a thermally conducting structure attached to a surface of the semiconductor device via soldering. The thermally conducting structure is essentially formed of a thermally conducting material and comprises an array of freestanding fins, studs or frames, or a grid of connected fins. A process for fabricating such a semiconductor device includes forming a thermally conducting structure on a carrier and attaching the thermally conducting structure formed on the carrier to a surface of the semiconductor device via soldering.
    Type: Grant
    Filed: February 22, 2010
    Date of Patent: April 19, 2011
    Assignee: International Business Machines Corporation
    Inventors: Thomas J. Brunschwiler, Michel Despont, Mark A. Lantz, Bruno Michel, Peter Vettiger
  • Patent number: 7929309
    Abstract: A clip is adapted for securing a heat sink on a printed circuit board (PCB). The clip includes a linking portion, an operating portion, a handle, and a pressing portion. The linking portion is located at a lateral side of the heat sink. The operating portion pivotally engages with the linking portion and the heat sink. The handle connects the operating portion. The pressing portion connects the linking portion. A fastener mounted on the PCB extends through the heat sink and the pressing portion. The pressing portion is slidable from a first position to a second position. When the pressing portion is in the second position the handle is operable to drive the operating portion to move upwardly and urge the pressing portion to move along the fastener until the pressing portion abuts against a top portion of the fastener and simultaneously presses the heat sink.
    Type: Grant
    Filed: December 7, 2009
    Date of Patent: April 19, 2011
    Assignees: Fu Zhun Precision Industry (Shen Zhen) Co., Ltd., Foxconn Technology Co., Ltd.
    Inventors: Pin-Qun Zhao, Dong-Bo Zheng, Meng Fu, Chun-Chi Chen
  • Patent number: 7923826
    Abstract: A semiconductor chip is mounted on a heat sink disposed inside a through-hole of a wiring board, electrodes of the semiconductor chip and connecting terminals of the wiring board are connected by bonding wires, a sealing resin is formed to cover the semiconductor chip and the bonding wires, and solder balls are formed on the lower surface of the wiring board, thereby constituting the semiconductor device. The heat sink is thicker than the wiring board. The heat sink has a protruded portion protruding to outside from the side surface of the heat sink, the protruded portion is located on the upper surface of the wiring board outside the through-hole, and the lower surface of the protruded portion contacts to the upper surface of the wiring board. When the semiconductor device is manufactured, the heat sink is inserted from the upper surface side of the wiring board.
    Type: Grant
    Filed: June 9, 2009
    Date of Patent: April 12, 2011
    Assignee: Renesas Electronics Corporation
    Inventors: Noriyuki Takahashi, Mamoru Shishido
  • Patent number: RE42653
    Abstract: A semiconductor package with a heat dissipating structure is provided. The heat dissipating structure includes a flat portion, and a plurality of support portions formed at edge corners of the flat portion for supporting the flat portion above a chip mounted on a substrate. The support portions are mounted at predetermined area on the substrate without interfering with arrangement of the chip and bonding wires that electrically connect the chip to the substrate. The support portions are arranged to form a space embraced by adjacent supports and the flat portion, so as to allow the bonding wires to pass through the space to reach area on the substrate outside coverage of the heat dissipating structure; besides, passive components or other electronic components can be mounted on the substrate at area within or outside the coverage of the heat dissipating structure, thereby improving flexibility in component arrangement in the semiconductor package.
    Type: Grant
    Filed: March 11, 2010
    Date of Patent: August 30, 2011
    Assignee: Siliconware Precision Industries Co., Ltd.
    Inventor: Chien-Ping Huang