Abstract: One or more electronic components can be mounted on the back side of a semiconductor die. The components can be passive components, active components, or combinations thereof. The components can be soldered to signal routes on the back side of the die, the signal routes being attached to the die using a metallization layer or using one or more dielectric layer sections. Placing components on the back side of the die can allow for incorporation of the components without necessarily increasing the form factor of the die's package.

Abstract: A submount for red, green, and blue LEDs is described where the submount has thermally isolated trenches and/or holes in the submount so that the high heat generated by the green/blue AlInGaN LEDs is not conducted to the red AlInGaP LEDs. The submount contains conductors to interconnect the LEDs in a variety of configurations. In one embodiment, the AlInGaP LEDs are recessed in the submount so all LEDs have the same light exit plane. The submount may be used for LEDs generating other colors, such as yellow, amber, orange, and cyan.

Abstract: A method of making 3D integrated circuits and a 3D integrated circuit structure. There is a first semiconductor structure joined to a second semiconductor structure. Each semiconductor structure includes a semiconductor wafer, a front end of the line (FEOL) wiring on the semiconductor wafer, a back end of the line (BEOL) wiring on the FEOL wiring, an insulator layer on the BEOL wiring and a metallic layer on the insulator layer. The first semiconductor structure is aligned with the second semiconductor structure such that the metallic layers of each of the semiconductor structures face each other. The metallic layers of each of the semiconductor structures are in contact with and bonded to each other by a metal to metal bond wherein the bonded metallic layers form an electrically isolated layer.

Abstract: Circuit board having conductor wiring and connection terminal; anisotropic conductive resin layer provided on one surface of circuit board; and plurality of electronic components respectively provided with electrode terminals in positions facing the connection terminal are included. The anisotropic conductive resin layer includes at least one kind of conductive particles selected from coiled conductive particles, fiber fluff conductive particles and conductive particles provided with a plurality of conductive protrusions, and resin binder; electrically couples electrode terminals of plurality of electronic components to connection terminals to each other with conductive particles; mechanically fixes electronic components and circuit board to each other; and protects conductor wiring.

Abstract: An apparatus to reduce a thermal penalty of a three-dimensional (3D) die stack for use in a computing environment is provided and includes a substrate installed within the computing environment, a first component to perform operations of the computing environment, which is coupled to the substrate in a stacking direction, a set of second components to perform operations of the computing environment, each of which is coupled to the first component and segmented with respect to one another to form a vacated region, a thermal interface material (TIM) disposed on exposed surfaces of the first and second components, and a lid, including a protrusion, coupled to the substrate to overlay the first and second components such that the protrusion extends into the vacated region and such that surfaces of the lid and the protrusion thermally communicate with the first and second components via the TIM.

Abstract: There is provided a system-in-package (SiP), which includes a substrate obtained by cutting a wafer for each unit system; one or more first electronic devices mounted on the substrate by a heat radiation plate; a plurality of interlayer dielectrics sequentially formed on the substrate; and one or more second electronic devices buried between or in the interlayer dielectrics on the substrate. A heat sink may be additionally attached to the bottom surface of the substrate. In this case, a thermal conduction path including heat pipes connecting the heat radiation plate on the substrate and the heat sink is formed. In the SiP, various types of devices are buried at a wafer level, so that a more integrated semiconductor device is implemented corresponding to demand for a fine pitch. Further, the heat radiation of a device required in high-speed operation and high heat generation is maximized due to the multi-stepped heat radiation structure, and thus the operation of the device is more stabilized.

Abstract: A plurality of LSI chips (1) are stacked on an interposer (2). Signal coils (1b) for signal transmission are formed on the circuit formation surfaces of LSI chips (1) that are formed using silicon substrates (1a). The signal coils (1b) connect to circuits formed in the LAI chips (1). Through-holes (1d) are formed in the centers of the signal coils (1b) of the silicon substrate (1a). Signal coils (2c) connected to solder balls (5) by way of through-conductors (2d) are formed on the interposer (2). Magnetic pins (3) that are composed of a magnetic material are inserted in the centers of the signal coils (1b and 2c).

Abstract: A semiconductor device is configured to provide current and voltage isolation inside an integrated circuit package. The semiconductor device includes first and second semiconductor dies, a first isolating block positioned on the first semiconductor die, and a second isolating block positioned on the second semiconductor die. The semiconductor device also includes a first interconnect coil having a plurality of wires connecting the first semiconductor die to the second isolating block, and a second interconnect coil having a plurality of wires connecting the second semiconductor die to the first isolating block.

Abstract: The semiconductor device includes a substrate, a first semiconductor element, a second semiconductor element, a first heat sink and a second heat sink. The first and the second semiconductor elements are provided on the substrate. The maximum power consumption of the first semiconductor element is lower than that of the second semiconductor element. The first heat sink is fixed to the first semiconductor element. The second heat sink is fixed to the second semiconductor element. The first heat sink is spaced apart from the second heat sink.

Abstract: An electrical device and method is disclosed. One embodiment provides a substrate, a sensor chip disposed completely above a plane section of a surface of the substrate. A structurally homogeneous material layer is disposed above the substrate and the sensor chip. A cavity is formed between the substrate and the material layer. The sensor chip is disposed inside the cavity.

Abstract: A semiconductor package includes a base substrate, a logic device with a serializer/deserializer (SerDes), a plurality of odd memory devices disposed on a lower surface of the logic device and operatively stack-connected with the SerDes, and a plurality of even memory devices disposed on an upper surface of the logic device and operatively stack-connected with the SerDes, such that the plurality of odd memory devices and the plurality of even memory devices are connected in parallel by the SerDes.

Abstract: A method of manufacturing a semiconductor device including a PMOS transistor and a NMOS transistor is described. The method facilitates obtaining a FUSI phase of a suitable composition for the NMOS transistor and the PMOS transistor respectively, with fewer mask layers and through a fewer number of manufacturing steps.

Abstract: A transceiver device includes a dielectric substrate, a ring member that is welded onto the dielectric substrate thereby forming a plurality of cavities, a cover that is welded onto the ring member, and at least one semiconductor device that is arranged in each of the cavities. The ring member has at least one passage that communicates between adjacent cavities. The passage is provided at a position shifted by substantially ?g/4 or substantially n×?g/2+?g/4 from a center axis of the cavities. If there are two or more passages, the passages are arranged at a ?g/2 interval, and one of the passages closest to the center axis is at a position shifted by substantially ?g/4 from the center axis.

Abstract: Methods for manufacturing microelectronic imaging units and microelectronic imaging units that are formed using such methods are disclosed herein. In one embodiment, a method includes providing a plurality of imaging dies on a microfeature workpiece. The individual imaging dies include an image sensor, an integrated circuit operably coupled to the image sensor, and a plurality of external contacts operably coupled to the integrated circuit. The method further includes attaching a plurality of covers to corresponding imaging dies, cutting the microfeature workpiece to singulate the imaging dies, and coupling the singulated dies to a support member. The covers can be attached to the imaging dies before or after the workpiece is cut.

Abstract: An electronic apparatus includes a semiconductor chip 15, a first substrate 10A having an antenna 12 formed on a first face 10a thereof and having the semiconductor chip 15 loaded on a second face 10b thereof, a second substrate 20A on which the first substrate 10A is provided so as to face the semiconductor chip 15, and which is connected to the outside, copper core solder balls 18 electrically connecting the first substrate 10A and the second substrate 20A, and a resin material 30 disposed between the first substrate 10A and the second substrate 20A. The second substrate 20A is provided with a thermal via 27 which radiates the heat in the semiconductor chip 15.

Abstract: A semiconductor device includes a first die, a substrate, and a first interconnect. The first die includes a first isolation region and a first contact at least partially overlapping the first isolation region. The substrate includes a second contact. The first interconnect couples the first contact to the second contact. The first interconnect is defined by a via through the first isolation region.

Abstract: An image sensing device and a packaging method thereof is disclosed. The packaging method includes the steps of providing an adhesive layer; placing a substrate, having an opening, on the adhesive layer; disposing an image sensor within the opening on the adhesive layer; adding a filler between the image sensor and the substrate; connecting the image sensor and the substrate via a plurality of bonding wires; and removing the adhesive layer.

Abstract: A portable electronic apparatus comprises a housing, a circuit board, a heat-conduction structure and a heat-dissipation structure. The circuit board is disposed in the housing and comprises a substrate and a first electronic device, wherein the first electronic device is disposed on the substrate. The heat-conduction structure is disposed on the circuit board, and dissipates heat from the first electronic device. The heat-dissipation structure is disposed on the housing and connected to the heat-conduction structure, wherein the heat passes the heat-conduction structure and the heat-dissipation structure, and is dissipated out of the housing.

Abstract: A semiconductor apparatus including built-in power supply circuits capable of supplying a large current with high voltage accuracy. The semiconductor apparatus includes a semiconductor chip including a circuit area and power supply circuits, coils and capacitors. The semiconductor chip, coils and capacitors are provided in a package. Each power supply circuit, a coil and a capacitor compose a switching regulator. The semiconductor chip and the package are connected such that a power supply voltage which will be produced by the switching regulator is supplied to the circuit area. The power supply circuit is supplied with a power supply voltage from the outside of the semiconductor apparatus.

Abstract: A method facilitates generally simultaneously fabricating a number of shallow trench isolation structures such that some selected ones of the shallow trench isolation structures have rounded corners and other selected ones of the shallow trench isolation structures do not have rounded corners. The method includes forming patterned photoresist over a hard mask so that portions of the hard mask are exposed over a portion of a cell region and over a portion of a periphery region, and then removing the exposed hard mask layer in the periphery region while removing a portion of the exposed hard mask layer in the cell region. A trench having rounded corners is then partially formed in the periphery region and more of the hard mask layer is removed in the cell region, before the trench in the periphery region is deepened while a trench in the cell region is formed.

Abstract: A disclosed integrated circuit (IC) module includes an IC panel and multi level circuit structure, referred to as an IPD structure, overlying an upper surface of the IC panel. The IC panel includes an electrically conductive embedded ground plane (EGP), an integrated circuit (IC) die, and an encapsulating material. The EGP is a substantially planar structure that includes or defines a plurality of cavities. The EGP may include or define an IC cavity and an IPD cavity. The IC die may be positioned within the IC cavity such that a perimeter of the IC cavity surrounds the IC die. The IPD structure may define or include a passive device such as an inductor. The passive device may be positioned or located overlying the void in the EGP.

Abstract: An electronic device (ICD) comprises an integrated circuit (AIC) and a capacitance element (PIC). The integrated circuit (AIC) is provided with a plurality of circuit contact pairs (CI). The capacitance element (PIC) is provided with a plurality of capacitance contact pairs (CC). A capacitance is present between each of at least part of the capacitance contact pairs (CC). The plurality of capacitance contact pairs (CC) faces the plurality of circuit contact pairs (CI). At least a part of the capacitance contact pairs (CC) is electrically coupled in a pair-by-pair manner to at least a part of the circuit contact pairs (CI).

Abstract: Packaged microelectronic devices and methods for manufacturing packaged microelectronic devices are disclosed herein. In one embodiment, a packaged microelectronic device can include a support member, a first die attached to the support member, and a second die attached to the first die in a stacked configuration. The device can also include an attachment feature between the first and second dies. The attachment feature can be composed of a dielectric adhesive material. The attachment feature includes (a) a single, unitary structure covering at least approximately all of the back side of the second die, and (b) a plurality of interconnect structures electrically coupled to internal active features of both the first die and the second die.

Abstract: Packages are joined together using an anisotropic conductive material that includes an electrically insulative component and a plurality of electrically conductive particles. The electrically conductive particles may complete electrical connection between inter-package connectors and bond pads that may otherwise fail. The electrically insulative component may be cured to act as an underfill to provide mechanical connection between the packages.

Abstract: A semiconductor packaging substrate with improved capability of electrostatic dissipation comprises a dielectric layer, a plurality of leads, a plurality of first electrostatic guiding traces, a plurality of second electrostatic guiding traces and a solder mask. The first electrostatic guiding traces and the second electrostatic guiding traces are formed in pairs in a plurality of electrostatic dissipation regions on the dielectric layer, where each pair of the first and second electrostatic guiding traces are disposed in equal line spacing and are electrically isolated from each other. The solder mask partially covers the leads but exposes the first electrostatic guiding traces and the second electrostatic guiding traces. The first electrostatic guiding traces are connected to some of the leads to enhance protection against electrostatic discharge.

Abstract: The present invention includes processes and packaging for high voltage integrated circuits (ICs), high voltage electronic devices and high voltage electronic circuits which operate over a wide range of voltages, e.g., from tens of volts to tens of thousands of volts. The inventive processes and packaging are particularly suitable for integrating low or lower voltage circuits or transistors to form high voltage ICs, high voltage electronic devices and high voltage electronic circuits. The inventive processes and packaging are also particularly suitable for isolating high voltage electronics to achieve high breakdown voltages and for supporting high voltage operation. The inventive processes may be used with any suitable semiconductor materials using conventional semiconductor fabrication and related facilities.

Abstract: A semiconductor multichip package includes a substrate having a top surface on which a bonding pad is formed, and a bottom surface opposing the top surface, on which an external connection terminal electrically connected with the bonding pad is formed, a first semiconductor chip mounted on a region of the top surface of the substrate excluding the bonding pad, a ceramic spacer disposed on a top surface of the first semiconductor chip and including a passive device therein, and at least one second semiconductor chip disposed on a top surface of the ceramic spacer. The ceramic spacer includes an interlayer circuit for an electrical connection between the first and second semiconductor chips, and the passive device is electrically connected to at least one of the first and second semiconductor chips. Accordingly, a package with a more compact structure can be realized.

Abstract: A power semiconductor module (1) has power semiconductor components (2, 4, 6, 8, 10, 12) arranged on a substrate (14), at least one portion of which components is connected in parallel and arranged symmetrically on the substrate (14). A second conduction plane (24, 26) is provided for making contact with the power semiconductor components (2, 4, 6, 8, 10, 12). The second conduction plane is arranged in a manner electrically insulated from the substrate surface (16) above the surfaces of the power semiconductor components (2, 4, 6, 8, 10, 12) that are remote from the substrate surface (16).

Abstract: A portable object connectable package for an electronic device comprises: semiconductor die package, having a top surface and an opposite bottom surface, and a connector body mechanically supported by the semiconductor die package. The bottom surface includes a plurality of connection elements for connecting to a printed circuit board. The connector body includes a plurality of resilient electrical connecting elements extending over the top surface for contacting with a portable object PO having a contacting area. The portable object connectable package is arranged to be coupled to a portable object positioner for removably positioning the contacting area of the portable object in contact with the plurality of resilient electrical connecting elements when the portable object is present in the portable object positioner.

Abstract: A semiconductor device is disclosed. One embodiment provides a device including a carrier, an electrically insulating layer arranged over the carrier and a first semiconductor chip arranged over the electrically insulating layer, wherein the first semiconductor chip has a first contact element on a first surface and a second contact element on a second surface.

Abstract: A radio frequency (RF) module and a multi RF module including the same include a base substrate, a first element capable of processing RF signals formed on the base substrate, a second element capable of processing RF signals separated from and disposed over the first element, a cap substrate coupled with the base substrate to encapsulate the first and second elements including a plurality of through electrodes that electrically connect the first and second elements to the outside, and a bonding pad that encapsulates and joins the base substrate and the cap substrate and electrically connects the first and second elements to the through electrodes.

Abstract: A semiconductor device is configured to provide current and voltage isolation inside an integrated circuit package. The semiconductor device includes first and second semiconductor dies, a first isolating block positioned on the first semiconductor die, and a second isolating block positioned on the second semiconductor die. The semiconductor device also includes a first interconnect coil having a plurality of wires connecting the first semiconductor die to the second isolating block, and a second interconnect coil having a plurality of wires connecting the second semiconductor die to the first isolating block.

Abstract: A semiconductor device in which chips are resin-molded, including: frames having front and back surfaces and die pads; power chips mounted on the surfaces of the die pads; an insulation resin sheet having a first and a second surfaces which are opposed against each other, the resin sheet being disposed such that the back surfaces of the die pads contact the first surface of the resin sheet; and a mold resin applied on the first surface of the resin sheet so as to seal up the power chips. The thermal conductivity of the resin sheet is larger than that of the mold resin.

Abstract: An integrated circuit package system includes: providing a substrate; attaching an integrated circuit over the substrate; attaching an integrated circuit subassembly system having a perforated interposer over the substrate with the perforated interposer having a slot; and forming a package encapsulation over the integrated circuit subassembly system, the perforated interposer, the integrated circuit, and the substrate with the slot filled with the package encapsulation.

Abstract: A semiconductor chip includes a semiconductor substrate having an opening portion and a frame portion defining a periphery of the opening portion. At least one electric element is provided on the frame portion, and has at least one electrode terminal. A first insulation film is formed on the frame portion so that the electrode terminal is partially exposed at the first insulation film to form a plurality of electrode pads.

Abstract: This invention provides an image sensor module with a three-dimensional die-stacking structure. By filling a conductive material into through silicon vias within at least one image sensor die, and into via holes within an insulating layer, vertical electrical connections are formed between the image sensor die and an image processor buried in the insulating layer. A plurality of solder bumps is formed on a backside of the image sensor module so that the module can be directly assembled onto a circuit board. The image sensor module of this invention is characterized by a wafer-level packaging architecture and a three-dimensional die-stacking structure, which reduces electrical connection lengths within the module and thus reduces an area and height of the whole packaged module.

Abstract: Light emitting LEDs devices comprised of LED chips that emit light at a first wavelength, and a thin film layer over the LED chip that changes the color of the emitted light. For example, a blue LED chip can be used to produce white light. The thin film layer beneficially consists of a florescent material, such as a phosphor, and/or includes tin. The thin film layer is beneficially deposited using chemical vapor deposition.

Abstract: A semiconductor device is provided that includes wiring patterns on a substrate formed of an organic insulating film, and a semiconductor chip mounted on the substrate. A liquid crystal display panel and a PW board are electrically connected to each other with an anisotropic conductive adhesive. At least one surface of the insulating film is treated with a silicon coupling material. The silicon coupling material contains silicon (Si) at a surface element density of 0.5 atomic percent to 12.0 atomic percent on a surface of the insulating film.

Abstract: A semiconductor device includes a first substrate having a first surface for mounting an electronic component and a second surface substantially parallel to the first surface. The first substrate includes a first region for mounting the electronic component, a second region including a plurality of first communication units for transmitting and receiving signals to and from a second substrate, input-output circuits disposed on the first region or the second region, the input-out circuits corresponding to the first communication units, and a control circuit for controlling input to and output from the input-output circuits disposed on the first region or the second region of the first substrate. Each of the input-output circuits includes an output circuit for outputting a signal to a second communication unit of the second substrate corresponding to the first communication unit and an input unit for receiving a signal sent from the corresponding second communication unit.

Abstract: A stacked electronic component comprises a first electronic component adhered on a substrate via a first adhesive layer, and a second electronic component adhered by using a second adhesive layer thereon. The second adhesive layer has a two-layer structure formed by a same material and having different modulus of elasticity. The second adhesive layer of the two-layer structure has a first layer disposed at the first electronic component side and a second layer disposed at the second electronic component side. The first layer softens or melts at an adhesive temperature. The second layer maintains a layered shape at the adhesive temperature. According to the stacked electronic component, occurrences of an insulation failure and a short circuiting are prevented, and in addition, a peeling failure between the electronic components, an increase of a manufacturing cost, and so on, can be suppressed.

Abstract: One or more electronic components can be mounted on the back side of a semiconductor die. The components can be passive components, active components, or combinations thereof. The components can be soldered to signal routes on the back side of the die, the signal routes being attached to the die using a metallization layer or using one or more dielectric layer sections. Placing components on the back side of the die can allow for incorporation of the components without necessarily increasing the form factor of the die's package.

Abstract: Multiple semiconductor device components and passive device components fixed to a substrate are embedded within an electroconductive-film/insulating-resin-film structure, and are thermally bonded to an insulating resin film.

Abstract: A multi-chip semiconductor package that includes two power semiconductor devices arranged in a half-bridge configuration between two opposing circuit boards.

Abstract: Application of underfill material may be controlled to minimize the formation of voids between a plurality of integrated circuit (“IC”) dice and a substrate in an IC package. One or more elements are located in a gap between two dice to control the flow of underfill material and minimize the formation of voids within the underfill material. In an embodiment, an element may be an active electrical component, a passive electrical component, or a non-functional electrical component. Methods of fabrication, as well as application of the package to an electronic assembly and to an electronic system, are also described.

Abstract: A semiconductor chip comprises a semiconductor substrate having integrated circuits formed on a cell region and a peripheral circuit region adjacent to each other. A bond pad-wiring pattern is formed on the semiconductor substrate. A pad-rearrangement pattern is electrically connected to the bond pad-wiring pattern. The pad-rearrangement pattern includes a bond pad disposed over at least a part of the cell region. The bond pad-wiring pattern is formed substantially in a center region of the semiconductor substrate. Thus, with the embodiments of the present invention, the overall chip size can thereby be substantially reduced and an MCP can be fabricated without the problems mentioned above.

Abstract: A semiconductor device includes: a first semiconductor chip face-down mounted on a substrate; a second semiconductor chip face-up mounted on the first semiconductor chip; an electromagnetic shielding plate inserted between the first semiconductor chip and the second semiconductor chip; and a bonding wire bonded on the substrate so as to be astride of the electromagnetic shielding plate.

Abstract: A power semiconductor die is sandwiched between upper and lower heat conducting laminate structures to form a surface mount component that is configured for double-sided cooling. The upper heat conducting laminate structure electrically couples top-side die terminal(s) to conductors formed on the inboard face of the lower heat conducting laminate structure, and all of the die terminals are electrically coupled to conductors formed on the outboard face of the lower heat conducting laminate structure. The die package can be placed in a test fixture for full power testing, and when installed in an electronic assembly including a circuit board and upper and lower heatsinks, the die is thermally coupled to the upper heatsink through the upper heat conducting laminate structure, and to the lower heatsink through the circuit board and the lower heat conducting laminate structure.

Abstract: A power electronic package includes: first and second high thermal conductivity insulating non-planar substrates; and a plurality of electronic components mounted on each of the substrates. The substrates are coupled each other at a plurality of bonding regions so that mechanical separation between the substrates is controlled by the number of the bonding regions, an arrangement of the bonding regions, a shape of each bonding region, and a material of the bonding regions. The mechanical separation provides a net axially-directed compressive force in the electronic components.

Abstract: Polymerized materials for forming the underfill and encapsulation structures for semiconductor package are disclosed. A filler constituent, such as boron nitride, silicates, elemental metals, or alloys, may be added to a liquid photopolymer resin to tailor the physical properties thereof upon curing. The filler constituents may be employed to alter the coefficient of thermal expansion, thermal conductivity, or electrical conductivity of the polymerized material. A number of different embodiments are disclosed that employ the above materials in selected regions of the underfill and encapsulation structures of the semiconductor package. The polymerized materials may also be used to form support structures and covers for optically interactive semiconductor devices. Methods for forming the above structures using stereolithography are also disclosed.

Abstract: A semiconductor chip has one or more peripheral bond pads. The semiconductor chip comprises a semiconductor substrate having a cell region and a peripheral circuit region adjacent to each other. A bond pad-wiring pattern is formed on at least a part of the peripheral region of the semiconductor substrate. A passivation layer is formed on the bond pad-wiring pattern and exposed portions of the semiconductor substrate; a pad-rearrangement pattern disposed over the passivation layer and electrically connected to the bond pad-wiring pattern; and an insulating layer formed over the pad-rearrangement pattern. The insulating layer has an opening therein that exposes a portion of the pad-rearrangement pattern to define a bond pad. The bond pad is disposed over at least a part of the cell region.