With Electrical Isolation Means Patents (Class 257/725)
  • Patent number: 7776640
    Abstract: An image sensing device and a packaging method thereof is disclosed. The packaging method includes the steps of providing an adhesive layer; placing a substrate, having an opening, on the adhesive layer; disposing an image sensor within the opening on the adhesive layer; adding a filler between the image sensor and the substrate; connecting the image sensor and the substrate via a plurality of bonding wires; and removing the adhesive layer.
    Type: Grant
    Filed: September 26, 2008
    Date of Patent: August 17, 2010
    Assignee: Tong Hsing Electronic Industries Ltd.
    Inventors: Cheng-Lung Chuang, Chi-Cheng Lin
  • Patent number: 7772670
    Abstract: A method facilitates generally simultaneously fabricating a number of shallow trench isolation structures such that some selected ones of the shallow trench isolation structures have rounded corners and other selected ones of the shallow trench isolation structures do not have rounded corners. The method includes forming patterned photoresist over a hard mask so that portions of the hard mask are exposed over a portion of a cell region and over a portion of a periphery region, and then removing the exposed hard mask layer in the periphery region while removing a portion of the exposed hard mask layer in the cell region. A trench having rounded corners is then partially formed in the periphery region and more of the hard mask layer is removed in the cell region, before the trench in the periphery region is deepened while a trench in the cell region is formed.
    Type: Grant
    Filed: December 20, 2006
    Date of Patent: August 10, 2010
    Assignee: Macronix International Co., Ltd.
    Inventor: Hsu-Sheng Yu
  • Patent number: 7763976
    Abstract: A disclosed integrated circuit (IC) module includes an IC panel and multi level circuit structure, referred to as an IPD structure, overlying an upper surface of the IC panel. The IC panel includes an electrically conductive embedded ground plane (EGP), an integrated circuit (IC) die, and an encapsulating material. The EGP is a substantially planar structure that includes or defines a plurality of cavities. The EGP may include or define an IC cavity and an IPD cavity. The IC die may be positioned within the IC cavity such that a perimeter of the IC cavity surrounds the IC die. The IPD structure may define or include a passive device such as an inductor. The passive device may be positioned or located overlying the void in the EGP.
    Type: Grant
    Filed: September 30, 2008
    Date of Patent: July 27, 2010
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Jinbang Tang, Darrel R. Frear, Robert J. Wenzel
  • Patent number: 7750436
    Abstract: An electronic device (ICD) comprises an integrated circuit (AIC) and a capacitance element (PIC). The integrated circuit (AIC) is provided with a plurality of circuit contact pairs (CI). The capacitance element (PIC) is provided with a plurality of capacitance contact pairs (CC). A capacitance is present between each of at least part of the capacitance contact pairs (CC). The plurality of capacitance contact pairs (CC) faces the plurality of circuit contact pairs (CI). At least a part of the capacitance contact pairs (CC) is electrically coupled in a pair-by-pair manner to at least a part of the circuit contact pairs (CI).
    Type: Grant
    Filed: July 7, 2005
    Date of Patent: July 6, 2010
    Assignee: NXP B.V.
    Inventor: Joop Van Lammeren
  • Patent number: 7745920
    Abstract: Packaged microelectronic devices and methods for manufacturing packaged microelectronic devices are disclosed herein. In one embodiment, a packaged microelectronic device can include a support member, a first die attached to the support member, and a second die attached to the first die in a stacked configuration. The device can also include an attachment feature between the first and second dies. The attachment feature can be composed of a dielectric adhesive material. The attachment feature includes (a) a single, unitary structure covering at least approximately all of the back side of the second die, and (b) a plurality of interconnect structures electrically coupled to internal active features of both the first die and the second die.
    Type: Grant
    Filed: June 10, 2008
    Date of Patent: June 29, 2010
    Assignee: Micron Technology, Inc.
    Inventors: Choon Kuan Lee, Chin Hui Chong, David J. Corisis
  • Publication number: 20100148359
    Abstract: Packages are joined together using an anisotropic conductive material that includes an electrically insulative component and a plurality of electrically conductive particles. The electrically conductive particles may complete electrical connection between inter-package connectors and bond pads that may otherwise fail. The electrically insulative component may be cured to act as an underfill to provide mechanical connection between the packages.
    Type: Application
    Filed: December 14, 2008
    Publication date: June 17, 2010
    Inventors: Nanette Quevedo, Myung Jin Yim
  • Patent number: 7732911
    Abstract: A semiconductor packaging substrate with improved capability of electrostatic dissipation comprises a dielectric layer, a plurality of leads, a plurality of first electrostatic guiding traces, a plurality of second electrostatic guiding traces and a solder mask. The first electrostatic guiding traces and the second electrostatic guiding traces are formed in pairs in a plurality of electrostatic dissipation regions on the dielectric layer, where each pair of the first and second electrostatic guiding traces are disposed in equal line spacing and are electrically isolated from each other. The solder mask partially covers the leads but exposes the first electrostatic guiding traces and the second electrostatic guiding traces. The first electrostatic guiding traces are connected to some of the leads to enhance protection against electrostatic discharge.
    Type: Grant
    Filed: May 4, 2007
    Date of Patent: June 8, 2010
    Assignee: ChipMOS Technologies Inc.
    Inventors: Tsung-Lung Chen, Ming-Hsun Li
  • Patent number: 7709292
    Abstract: The present invention includes processes and packaging for high voltage integrated circuits (ICs), high voltage electronic devices and high voltage electronic circuits which operate over a wide range of voltages, e.g., from tens of volts to tens of thousands of volts. The inventive processes and packaging are particularly suitable for integrating low or lower voltage circuits or transistors to form high voltage ICs, high voltage electronic devices and high voltage electronic circuits. The inventive processes and packaging are also particularly suitable for isolating high voltage electronics to achieve high breakdown voltages and for supporting high voltage operation. The inventive processes may be used with any suitable semiconductor materials using conventional semiconductor fabrication and related facilities.
    Type: Grant
    Filed: September 29, 2006
    Date of Patent: May 4, 2010
    Inventors: Laurence P. Sadwick, Mohammad M. Mojarradi, Ruey-Jen Hwu, Jehn-Huar Chern
  • Publication number: 20100102430
    Abstract: A semiconductor multichip package includes a substrate having a top surface on which a bonding pad is formed, and a bottom surface opposing the top surface, on which an external connection terminal electrically connected with the bonding pad is formed, a first semiconductor chip mounted on a region of the top surface of the substrate excluding the bonding pad, a ceramic spacer disposed on a top surface of the first semiconductor chip and including a passive device therein, and at least one second semiconductor chip disposed on a top surface of the ceramic spacer. The ceramic spacer includes an interlayer circuit for an electrical connection between the first and second semiconductor chips, and the passive device is electrically connected to at least one of the first and second semiconductor chips. Accordingly, a package with a more compact structure can be realized.
    Type: Application
    Filed: June 1, 2009
    Publication date: April 29, 2010
    Applicant: SAMSUNG ELECTRO-MECHANICS CO., LTD.
    Inventors: Tae Soo LEE, Yun Hwi Park, Yun Hee Cho
  • Patent number: 7701051
    Abstract: A power semiconductor module (1) has power semiconductor components (2, 4, 6, 8, 10, 12) arranged on a substrate (14), at least one portion of which components is connected in parallel and arranged symmetrically on the substrate (14). A second conduction plane (24, 26) is provided for making contact with the power semiconductor components (2, 4, 6, 8, 10, 12). The second conduction plane is arranged in a manner electrically insulated from the substrate surface (16) above the surfaces of the power semiconductor components (2, 4, 6, 8, 10, 12) that are remote from the substrate surface (16).
    Type: Grant
    Filed: September 26, 2005
    Date of Patent: April 20, 2010
    Assignee: Infineon Technologies AG
    Inventors: Reinhold Bayerer, Markus Thoben
  • Patent number: 7692280
    Abstract: A portable object connectable package for an electronic device comprises: semiconductor die package, having a top surface and an opposite bottom surface, and a connector body mechanically supported by the semiconductor die package. The bottom surface includes a plurality of connection elements for connecting to a printed circuit board. The connector body includes a plurality of resilient electrical connecting elements extending over the top surface for contacting with a portable object PO having a contacting area. The portable object connectable package is arranged to be coupled to a portable object positioner for removably positioning the contacting area of the portable object in contact with the plurality of resilient electrical connecting elements when the portable object is present in the portable object positioner.
    Type: Grant
    Filed: March 21, 2006
    Date of Patent: April 6, 2010
    Assignee: ST-Ericsson SA
    Inventors: Stefan Marco Koch, Heinz-Peter Wirtz, Alexander M. Jooss
  • Patent number: 7683477
    Abstract: A semiconductor device is disclosed. One embodiment provides a device including a carrier, an electrically insulating layer arranged over the carrier and a first semiconductor chip arranged over the electrically insulating layer, wherein the first semiconductor chip has a first contact element on a first surface and a second contact element on a second surface.
    Type: Grant
    Filed: June 26, 2007
    Date of Patent: March 23, 2010
    Assignee: Infineon Technologies AG
    Inventor: Ralf Otremba
  • Patent number: 7675154
    Abstract: A radio frequency (RF) module and a multi RF module including the same include a base substrate, a first element capable of processing RF signals formed on the base substrate, a second element capable of processing RF signals separated from and disposed over the first element, a cap substrate coupled with the base substrate to encapsulate the first and second elements including a plurality of through electrodes that electrically connect the first and second elements to the outside, and a bonding pad that encapsulates and joins the base substrate and the cap substrate and electrically connects the first and second elements to the through electrodes.
    Type: Grant
    Filed: December 6, 2006
    Date of Patent: March 9, 2010
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Seog-woo Hong, In-sang Song, Byeong-ju Ha, Hae-seok Park, Jun-sik Hwang, Joo-ho Lee
  • Publication number: 20100052120
    Abstract: A semiconductor device is configured to provide current and voltage isolation inside an integrated circuit package. The semiconductor device includes first and second semiconductor dies, a first isolating block positioned on the first semiconductor die, and a second isolating block positioned on the second semiconductor die. The semiconductor device also includes a first interconnect coil having a plurality of wires connecting the first semiconductor die to the second isolating block, and a second interconnect coil having a plurality of wires connecting the second semiconductor die to the first isolating block.
    Type: Application
    Filed: September 2, 2008
    Publication date: March 4, 2010
    Inventor: David Alan PRUITT
  • Patent number: 7671453
    Abstract: A semiconductor device in which chips are resin-molded, including: frames having front and back surfaces and die pads; power chips mounted on the surfaces of the die pads; an insulation resin sheet having a first and a second surfaces which are opposed against each other, the resin sheet being disposed such that the back surfaces of the die pads contact the first surface of the resin sheet; and a mold resin applied on the first surface of the resin sheet so as to seal up the power chips. The thermal conductivity of the resin sheet is larger than that of the mold resin.
    Type: Grant
    Filed: September 22, 2004
    Date of Patent: March 2, 2010
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Kenichi Hayashi, Hisashi Kawafuji, Tatsuyuki Takeshita, Nobuhito Funakoshi, Hiroyuki Ozaki, Kazuhiro Tada
  • Patent number: 7667314
    Abstract: An integrated circuit package system includes: providing a substrate; attaching an integrated circuit over the substrate; attaching an integrated circuit subassembly system having a perforated interposer over the substrate with the perforated interposer having a slot; and forming a package encapsulation over the integrated circuit subassembly system, the perforated interposer, the integrated circuit, and the substrate with the slot filled with the package encapsulation.
    Type: Grant
    Filed: September 30, 2007
    Date of Patent: February 23, 2010
    Assignee: STATS ChipPAC Ltd.
    Inventors: In Sang Yoon, Sungmin Song
  • Patent number: 7667315
    Abstract: A semiconductor chip includes a semiconductor substrate having an opening portion and a frame portion defining a periphery of the opening portion. At least one electric element is provided on the frame portion, and has at least one electrode terminal. A first insulation film is formed on the frame portion so that the electrode terminal is partially exposed at the first insulation film to form a plurality of electrode pads.
    Type: Grant
    Filed: March 1, 2006
    Date of Patent: February 23, 2010
    Assignee: Oki Semiconductor Co., Ltd.
    Inventor: Takashi Ohsumi
  • Patent number: 7663231
    Abstract: This invention provides an image sensor module with a three-dimensional die-stacking structure. By filling a conductive material into through silicon vias within at least one image sensor die, and into via holes within an insulating layer, vertical electrical connections are formed between the image sensor die and an image processor buried in the insulating layer. A plurality of solder bumps is formed on a backside of the image sensor module so that the module can be directly assembled onto a circuit board. The image sensor module of this invention is characterized by a wafer-level packaging architecture and a three-dimensional die-stacking structure, which reduces electrical connection lengths within the module and thus reduces an area and height of the whole packaged module.
    Type: Grant
    Filed: January 28, 2008
    Date of Patent: February 16, 2010
    Assignee: Industrial Technology Research Institute
    Inventors: Shu-Ming Chang, Tzu-Ying Kuo, Chia-Wen Chiang, Hsiang-Hung Chang
  • Patent number: 7649210
    Abstract: Light emitting LEDs devices comprised of LED chips that emit light at a first wavelength, and a thin film layer over the LED chip that changes the color of the emitted light. For example, a blue LED chip can be used to produce white light. The thin film layer beneficially consists of a florescent material, such as a phosphor, and/or includes tin. The thin film layer is beneficially deposited using chemical vapor deposition.
    Type: Grant
    Filed: October 30, 2007
    Date of Patent: January 19, 2010
    Assignee: LG Electronics Inc.
    Inventor: Myung Cheol Yoo
  • Patent number: 7638854
    Abstract: A semiconductor device is provided that includes wiring patterns on a substrate formed of an organic insulating film, and a semiconductor chip mounted on the substrate. A liquid crystal display panel and a PW board are electrically connected to each other with an anisotropic conductive adhesive. At least one surface of the insulating film is treated with a silicon coupling material. The silicon coupling material contains silicon (Si) at a surface element density of 0.5 atomic percent to 12.0 atomic percent on a surface of the insulating film.
    Type: Grant
    Filed: January 17, 2006
    Date of Patent: December 29, 2009
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Yasuhiko Tanaka, Kenji Toyosawa
  • Patent number: 7633155
    Abstract: A semiconductor device includes a first substrate having a first surface for mounting an electronic component and a second surface substantially parallel to the first surface. The first substrate includes a first region for mounting the electronic component, a second region including a plurality of first communication units for transmitting and receiving signals to and from a second substrate, input-output circuits disposed on the first region or the second region, the input-out circuits corresponding to the first communication units, and a control circuit for controlling input to and output from the input-output circuits disposed on the first region or the second region of the first substrate. Each of the input-output circuits includes an output circuit for outputting a signal to a second communication unit of the second substrate corresponding to the first communication unit and an input unit for receiving a signal sent from the corresponding second communication unit.
    Type: Grant
    Filed: February 6, 2008
    Date of Patent: December 15, 2009
    Assignee: Sony Corporation
    Inventors: Shunichi Sukegawa, Takeo Sekino, Kenichi Shigenami, Shinichi Toi, Tatsuo Shimizu
  • Patent number: 7629695
    Abstract: A stacked electronic component comprises a first electronic component adhered on a substrate via a first adhesive layer, and a second electronic component adhered by using a second adhesive layer thereon. The second adhesive layer has a two-layer structure formed by a same material and having different modulus of elasticity. The second adhesive layer of the two-layer structure has a first layer disposed at the first electronic component side and a second layer disposed at the second electronic component side. The first layer softens or melts at an adhesive temperature. The second layer maintains a layered shape at the adhesive temperature. According to the stacked electronic component, occurrences of an insulation failure and a short circuiting are prevented, and in addition, a peeling failure between the electronic components, an increase of a manufacturing cost, and so on, can be suppressed.
    Type: Grant
    Filed: May 19, 2005
    Date of Patent: December 8, 2009
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Atsushi Yoshimura, Naoyuki Komuta, Hideo Numata
  • Patent number: 7622805
    Abstract: Multiple semiconductor device components and passive device components fixed to a substrate are embedded within an electroconductive-film/insulating-resin-film structure, and are thermally bonded to an insulating resin film.
    Type: Grant
    Filed: March 9, 2006
    Date of Patent: November 24, 2009
    Assignee: Sanyo Electric Co., Ltd.
    Inventors: Ryosuke Usui, Yasunori Inoue
  • Patent number: 7622811
    Abstract: One or more electronic components can be mounted on the back side of a semiconductor die. The components can be passive components, active components, or combinations thereof. The components can be soldered to signal routes on the back side of the die, the signal routes being attached to the die using a metallization layer or using one or more dielectric layer sections. Placing components on the back side of the die can allow for incorporation of the components without necessarily increasing the form factor of the die's package.
    Type: Grant
    Filed: September 14, 2006
    Date of Patent: November 24, 2009
    Assignee: Stats Chippac, Inc.
    Inventors: Seng Guan Chow, Francis Heap Hoe Kuan
  • Patent number: 7592688
    Abstract: A multi-chip semiconductor package that includes two power semiconductor devices arranged in a half-bridge configuration between two opposing circuit boards.
    Type: Grant
    Filed: January 16, 2007
    Date of Patent: September 22, 2009
    Assignee: International Rectifier Corporation
    Inventor: Martin Standing
  • Patent number: 7589395
    Abstract: Application of underfill material may be controlled to minimize the formation of voids between a plurality of integrated circuit (“IC”) dice and a substrate in an IC package. One or more elements are located in a gap between two dice to control the flow of underfill material and minimize the formation of voids within the underfill material. In an embodiment, an element may be an active electrical component, a passive electrical component, or a non-functional electrical component. Methods of fabrication, as well as application of the package to an electronic assembly and to an electronic system, are also described.
    Type: Grant
    Filed: June 30, 2006
    Date of Patent: September 15, 2009
    Assignee: Intel Corporation
    Inventors: Ajit V. Sathe, Mathew J. Manusharow, Sung-Won Moon
  • Patent number: 7576440
    Abstract: A semiconductor chip comprises a semiconductor substrate having integrated circuits formed on a cell region and a peripheral circuit region adjacent to each other. A bond pad-wiring pattern is formed on the semiconductor substrate. A pad-rearrangement pattern is electrically connected to the bond pad-wiring pattern. The pad-rearrangement pattern includes a bond pad disposed over at least a part of the cell region. The bond pad-wiring pattern is formed substantially in a center region of the semiconductor substrate. Thus, with the embodiments of the present invention, the overall chip size can thereby be substantially reduced and an MCP can be fabricated without the problems mentioned above.
    Type: Grant
    Filed: November 2, 2006
    Date of Patent: August 18, 2009
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Young-Hee Song, Il-Heung Choi, Jeong-Jin Kim, Hae-Jeong Sohn, Chung-Woo Lee
  • Patent number: 7569922
    Abstract: A semiconductor device includes: a first semiconductor chip face-down mounted on a substrate; a second semiconductor chip face-up mounted on the first semiconductor chip; an electromagnetic shielding plate inserted between the first semiconductor chip and the second semiconductor chip; and a bonding wire bonded on the substrate so as to be astride of the electromagnetic shielding plate.
    Type: Grant
    Filed: August 8, 2007
    Date of Patent: August 4, 2009
    Assignee: Seiko Epson Corporation
    Inventor: Yoshiharu Ogata
  • Patent number: 7564128
    Abstract: A power semiconductor die is sandwiched between upper and lower heat conducting laminate structures to form a surface mount component that is configured for double-sided cooling. The upper heat conducting laminate structure electrically couples top-side die terminal(s) to conductors formed on the inboard face of the lower heat conducting laminate structure, and all of the die terminals are electrically coupled to conductors formed on the outboard face of the lower heat conducting laminate structure. The die package can be placed in a test fixture for full power testing, and when installed in an electronic assembly including a circuit board and upper and lower heatsinks, the die is thermally coupled to the upper heatsink through the upper heat conducting laminate structure, and to the lower heatsink through the circuit board and the lower heat conducting laminate structure.
    Type: Grant
    Filed: November 8, 2007
    Date of Patent: July 21, 2009
    Assignee: Delphi Technologies, Inc.
    Inventor: Todd P. Oman
  • Patent number: 7557434
    Abstract: A power electronic package includes: first and second high thermal conductivity insulating non-planar substrates; and a plurality of electronic components mounted on each of the substrates. The substrates are coupled each other at a plurality of bonding regions so that mechanical separation between the substrates is controlled by the number of the bonding regions, an arrangement of the bonding regions, a shape of each bonding region, and a material of the bonding regions. The mechanical separation provides a net axially-directed compressive force in the electronic components.
    Type: Grant
    Filed: August 29, 2006
    Date of Patent: July 7, 2009
    Assignees: DENSO CORPORATION, University of Cambridge, The University of Sheffield
    Inventors: Rajesh Kumar Malhan, C. Mark Johnson, Jeremy Rashid
  • Patent number: 7547978
    Abstract: Polymerized materials for forming the underfill and encapsulation structures for semiconductor package are disclosed. A filler constituent, such as boron nitride, silicates, elemental metals, or alloys, may be added to a liquid photopolymer resin to tailor the physical properties thereof upon curing. The filler constituents may be employed to alter the coefficient of thermal expansion, thermal conductivity, or electrical conductivity of the polymerized material. A number of different embodiments are disclosed that employ the above materials in selected regions of the underfill and encapsulation structures of the semiconductor package. The polymerized materials may also be used to form support structures and covers for optically interactive semiconductor devices. Methods for forming the above structures using stereolithography are also disclosed.
    Type: Grant
    Filed: June 14, 2004
    Date of Patent: June 16, 2009
    Assignee: Micron Technology, Inc.
    Inventors: David R. Hembree, Warren M. Farnworth
  • Patent number: 7541682
    Abstract: A semiconductor chip has one or more peripheral bond pads. The semiconductor chip comprises a semiconductor substrate having a cell region and a peripheral circuit region adjacent to each other. A bond pad-wiring pattern is formed on at least a part of the peripheral region of the semiconductor substrate. A passivation layer is formed on the bond pad-wiring pattern and exposed portions of the semiconductor substrate; a pad-rearrangement pattern disposed over the passivation layer and electrically connected to the bond pad-wiring pattern; and an insulating layer formed over the pad-rearrangement pattern. The insulating layer has an opening therein that exposes a portion of the pad-rearrangement pattern to define a bond pad. The bond pad is disposed over at least a part of the cell region.
    Type: Grant
    Filed: November 2, 2006
    Date of Patent: June 2, 2009
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Young-Hee Song, Il-Heung Choi, Jeong-Jin Kim, Hae-Jeong Sohn, Chung-Woo Lee
  • Patent number: 7531890
    Abstract: A multi-chip package (MCP) is provided. The MCP comprises a plurality of stacked semiconductor chips, each including a chip pad and a first insulating layer overlying the chip pad with an opening to expose a portion of the chip pad. Each chip additionally includes a pad redistribution line formed on the first insulating layer and a second insulating layer covering the pad redistribution line. A via hole is formed through the chip, the first insulating layer, a pad redistribution line and the second insulating layer. The MCP further includes a protective layer formed on the bottom of the lowest semiconductor chip. The protective layer includes a conductive pad formed opposite the bottom of the lowest semiconductor chip. A conductive bar extends through the via holes of the stacked semiconductor chips, from the conductive pad, and is electrically connected to the pad redistribution line of the stacked semiconductor chips.
    Type: Grant
    Filed: May 16, 2005
    Date of Patent: May 12, 2009
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Gu-Sung Kim
  • Patent number: 7524703
    Abstract: The present invention stacks integrated circuits (ICs) into modules that conserve PWB or other board surface area. In another aspect, the invention provides a lower capacitance memory expansion addressing system and method and preferably with the CSP stacked modules provided herein. In a preferred embodiment in accordance with the invention, a form standard provides a physical form that allows many of the varying package sizes found in the broad family of CSP packages to be used to advantage while employing a standard connective flex circuitry design. In a preferred embodiment, the form standard will be devised of heat transference material such as copper to improve thermal performance. In an alternative embodiment, the form standard may include a heat spreader portion with mounting feet. In a preferred embodiment of the memory addressing system, a high speed switching system selects a data line associated with each level of a stacked module to reduce the loading effect upon data signals in memory access.
    Type: Grant
    Filed: September 7, 2005
    Date of Patent: April 28, 2009
    Assignee: Entorian Technologies, LP
    Inventors: James W. Cady, James Wilder, David L. Roper, James Douglas Wehrly, Jr.
  • Patent number: 7521763
    Abstract: The embodiments of the invention provide a device, method, etc. for a dual stress STI. A semiconductor device is provided having a substrate with a first transistor region and a second transistor region different than the first transistor region. The first transistor region includes a PFET; and, the second transistor region includes an NFET. Further, STI regions are provided in the substrate adjacent sides of and positioned between the first transistor region and the second transistor region, wherein the STI regions each include a compressive region, a compressive liner, a tensile region, and a tensile liner.
    Type: Grant
    Filed: January 3, 2007
    Date of Patent: April 21, 2009
    Assignee: International Business Machines Corporation
    Inventors: Deok-kee Kim, Seong-Dong Kim, Oh-Jung Kwon
  • Patent number: 7514774
    Abstract: A stacked multi-chip package with an EMI shielded component has first and second substrates mounted together by a grid array of metallic connecting nodes, such as a solder Ball Grid Array. Each substrate has a conductive plane associated with it. An electronic component is mounted between the first and second substrates and is surrounded by a group of the metallic connecting nodes that are also electrically connected to the conductive planes of both substrates to form a conductive Faraday cage about the component.
    Type: Grant
    Filed: September 15, 2006
    Date of Patent: April 7, 2009
    Assignee: Hong Kong Applied Science Technology Research Institute Company Limited
    Inventors: Lap Wai Leung, Yu-Chih Chen, Man-Lung Sham, Chang-Hwa Chung
  • Patent number: 7511374
    Abstract: Microelectronic imaging units having covered image sensors are disclosed herein. In one embodiment, the microelectronic imaging units have an image sensor, an integrated circuit, a cover located over the image sensor, at least one dam, and a fill material between adjacent imaging units. The covers may be located on discrete adhesive portions inboard of external contacts that are operably coupled to the integrated circuits.
    Type: Grant
    Filed: June 7, 2006
    Date of Patent: March 31, 2009
    Assignee: Aptina Imaging Corporation
    Inventors: James M. Derderian, Bret K. Street, Eric T. Mueller
  • Publication number: 20090072389
    Abstract: A system and method for providing capacitively-coupled signaling in a system-in-package (SiP) device is disclosed. In one embodiment, the system includes a first semiconductor device and an opposing second semiconductor device spaced apart from the first device, a dielectric layer interposed between the first device and the second device, a first conductive pad positioned in the first device, and a second conductive pad positioned in the second device that capacitively communicate signals from the second device to the first device. In another embodiment, a method of forming a SiP device includes forming a first pad on a surface of a first semiconductor device, forming a second pad on a surface of a second semiconductor device, and interposing a dielectric layer between the first semiconductor device and the second semiconductor device that separates the first conductive signal pad and the second conductive signal pad.
    Type: Application
    Filed: November 25, 2008
    Publication date: March 19, 2009
    Applicant: Micron Technology, Inc.
    Inventor: Philip Neaves
  • Patent number: 7504670
    Abstract: A semiconductor device includes: a substrate; a semiconductor element mounted on the substrate; a sealing structure for sealing the semiconductor element, the sealing structure being mounted on the substrate; and an adhesive for bonding the sealing structure and the substrate, wherein the sealing structure has a groove for storing the adhesive.
    Type: Grant
    Filed: June 7, 2006
    Date of Patent: March 17, 2009
    Assignee: Shinko Electric Industries Co., Ltd.
    Inventors: Satoshi Shiraishi, Yoichi Kazama
  • Patent number: 7495336
    Abstract: An integrated broadband array capacitor includes at least two regions with varying capacitance and response times. The broadband array capacitor is disposable on a socket or is integral with a socket. A method of operating the broadband array capacitor includes responding to load transients from each of the at least two regions. A computing system is also disclosed that includes the broadband array capacitor.
    Type: Grant
    Filed: December 30, 2005
    Date of Patent: February 24, 2009
    Assignee: Intel Corporation
    Inventors: Joel A. Auernheimer, Nicholas Holmberg, Kaladhar Radhakrishnan, Dustin P. Wood
  • Patent number: 7468547
    Abstract: An RF-coupled digital isolator includes a first leadframe portion and a second leadframe portion, electrically isolated from one another. The first leadframe portion includes a first main body and a first finger. The second leadframe portion includes a second main body and a second finger. The first main body is connected to a first ground, and the second main body is connected to a second ground that is electrically isolated from the first ground. The first finger and the second finger are electrically isolated from one another, e.g., by a plastic molding compound that forms a package for the digital isolator. The first finger acts as a primary of a transformer, and the second finger acts as a secondary of a transformer, when an RF signal drives to the first finger. The first finger and the second finger can be substantially parallel or anti-parallel to one another.
    Type: Grant
    Filed: October 23, 2007
    Date of Patent: December 23, 2008
    Assignee: Intersil Americas Inc.
    Inventor: Barry Harvey
  • Patent number: 7466021
    Abstract: Disclosed are IC package structures having stair stepped layers and which have no plated vias. Such structures can be fabricated either as discrete packages or as strips such as might be beneficial in for use with memory devices wherein critical or high speed signals can be routed along the length of the multi-chip strip package without having to have the signals ascend and descend from the interconnection substrate on which the assembly is mounted to the IC package termination and back as the signal transmits between devices.
    Type: Grant
    Filed: May 2, 2006
    Date of Patent: December 16, 2008
    Assignee: Interconnect Portfolio, LLP
    Inventor: Joseph Charles Fjelstad
  • Patent number: 7462935
    Abstract: A system and method for providing capacitively-coupled signaling in a system-in-package (SiP) device is disclosed. In one embodiment, the system includes a first semiconductor device and an opposing second semiconductor device spaced apart from the first device, a dielectric layer interposed between the first device and the second device, a first conductive pad positioned in the first device, and a second conductive pad positioned in the second device that capacitively communicate signals from the second device to the first device. In another embodiment, a method of forming a SiP device includes forming a first pad on a surface of a first semiconductor device, forming a second pad on a surface of a second semiconductor device, and interposing a dielectric layer between the first semiconductor device and the second semiconductor device that separates the first conductive signal pad and the second conductive signal pad.
    Type: Grant
    Filed: February 13, 2004
    Date of Patent: December 9, 2008
    Assignee: Micron Technology, Inc.
    Inventor: Philip Neaves
  • Publication number: 20080296697
    Abstract: Various structures of a programmable semiconductor interposer for electronic packaging are described. An array of semiconductor devices having various values is formed in said interposer. A user can program said interposer and form a “virtual” device having a desired value by selectively connecting various one of the array of devices to contact pads formed on the surface of said interposer. An inventive electronic package structure includes a standard interposer having an array of unconnected devices of various values and a device selection unit, which selectively connects various one of the array of devices in said standard interposer to an integrated circuit die encapsulated in said electronic package. Methods of forming said programmable semiconductor interposer and said electronic package are also illustrated.
    Type: Application
    Filed: May 29, 2007
    Publication date: December 4, 2008
    Inventors: Chao-Shun Hsu, Clinton Chao, Mark Shane Peng
  • Patent number: 7459776
    Abstract: A stack of semiconductor dies is disclosed. A first stack level includes a first semiconductor die and at least one first support that are attached to a substrate surface. A second level includes a second semiconductor die and at least one second support that are attached to the active surface of the first semiconductor die and to a coplanar surface of the first support(s). A third level includes a third semiconductor die attached to the active surface of the second semiconductor die and to a coplanar surface of the second support(s). The second and third semiconductor dies do not overlap bond pads of the first and second semiconductor dies, respectively. An adhesive film overlies the entire inactive surface of the second and third semiconductor dies, and attaches the second and third semiconductor dies to the immediately underlying active surface and support(s).
    Type: Grant
    Filed: September 27, 2006
    Date of Patent: December 2, 2008
    Assignee: Amkor Technology, Inc.
    Inventors: Roger D. St. Amand, Vladimir Perelman
  • Publication number: 20080290508
    Abstract: A semiconductor device includes a first substrate having a first surface for mounting an electronic component and a second surface substantially parallel to the first surface. The first substrate includes a first region for mounting the electronic component, a second region including a plurality of first communication units for transmitting and receiving signals to and from a second substrate, input-output circuits disposed on the first region or the second region, the input-out circuits corresponding to the first communication units, and a control circuit for controlling input to and output from the input-output circuits disposed on the first region or the second region of the first substrate. Each of the input-output circuits includes an output circuit for outputting a signal to a second communication unit of the second substrate corresponding to the first communication unit and an input unit for receiving a signal sent from the corresponding second communication unit.
    Type: Application
    Filed: February 6, 2008
    Publication date: November 27, 2008
    Applicant: Sony Corporation
    Inventors: Shunichi SUKEGAWA, Takeo Sekino, Kenichi Shigenami, Shinichi Toi, Tatsuo Shimizu
  • Patent number: 7456500
    Abstract: A light source module having a plurality of LEDs connected to a metal carrier (4) by means of an insulating layer (3). In order to afford protection against mechanical effects and in order to form a reflector, the LEDs are surrounded by a frame (10), which is segmented into a plurality of parts by expansion joints (13), in order that stresses occurring as a result of temperature fluctuations are absorbed.
    Type: Grant
    Filed: September 24, 2003
    Date of Patent: November 25, 2008
    Assignee: Osram Opto Semiconductors GmbH
    Inventors: Patrick Kromotis, Günter Waitl
  • Patent number: 7446411
    Abstract: A semiconductor structure (100, 900) includes a substrate (110) having a surface (111) and also includes one or more semiconductor chips (120) located over the substrate surface. The semiconductor structure further includes an electrical isolator structure (340) located over the substrate surface, where the electrical isolator structure includes one or more electrical leads (341, 342) and an organic-based element (343) molded to the electrical leads. The semiconductor structure also includes a solder element (350) coupling together the electrical isolator structure and the substrate surface.
    Type: Grant
    Filed: October 24, 2005
    Date of Patent: November 4, 2008
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Brian W. Condie, Lakshminarayan Viswanathan, Richard W. Wetz
  • Patent number: 7432593
    Abstract: A semiconductor package assembly and method for electrically isolating modules, having a capacitor within the semiconductor package assembly. The package assembly and method are suitable for electrically isolating modules according to IEEE 1394.
    Type: Grant
    Filed: January 20, 2005
    Date of Patent: October 7, 2008
    Assignee: Micron Technology, Inc.
    Inventors: Sion C. Quinlan, Tim J. Bales
  • Publication number: 20080224306
    Abstract: The present invention provides a structure of multi-chips package comprising: a substrate with a die receiving cavity formed within an upper surface of the substrate and a first through holes structure, wherein terminal pads are formed under the first through holes structure. A first die is disposed within the die receiving cavity and a first dielectric layer is formed on the first die and the substrate. A first re-distribution conductive layer (RDL) is formed on the first dielectric layer. A second dielectric layer is formed over the first RDL. A third dielectric layer is formed under a second die. A second re-distribution conductive layer (RDL) is formed under the third dielectric layer. A fourth dielectric layer is formed under the second RDL. Conductive bumps are coupled to the first RDL and the second RDL. A surrounding material surrounds the second die. The second die is coupled to the first die through the first RDL, second RDL and the conductive bumps.
    Type: Application
    Filed: May 30, 2008
    Publication date: September 18, 2008
    Inventor: Wen-Kun YANG