Contact For Iii-v Material Patents (Class 257/745)
  • Patent number: 7476970
    Abstract: A method for fabricating a semiconductor device utilizing the step of forming a first insulating film of a porous material over a substrate; the step of forming on the first insulating film a second insulating film containing a silicon compound containing Si—CH3 bonds by 30-90%, and the step of irradiating UV radiation with the second insulating film formed on the first insulating film to cure the first insulating film. Thus, UV radiation having the wavelength which eliminates CH3 groups is sufficiently absorbed by the second insulating film, whereby the first insulating film is highly strengthened with priority by the UV cure, and the first insulating film can have the film density increased without having the dielectric constant increased.
    Type: Grant
    Filed: June 27, 2006
    Date of Patent: January 13, 2009
    Assignee: Fujitsu Limited
    Inventors: Shirou Ozaki, Yoshihiro Nakata, Ei Yano
  • Patent number: 7466012
    Abstract: A power semiconductor package that includes a semiconductor die having at least two power electrodes and a conductive clip electrically and mechanically coupled to each power electrode.
    Type: Grant
    Filed: September 13, 2005
    Date of Patent: December 16, 2008
    Assignee: International Rectifier Corporation
    Inventors: Martin Standing, Robert J Clarke
  • Patent number: 7462877
    Abstract: A nitride-based light emitting device having a light emitting layer between an N-type clad layer and a P-type clad layer is provided. The light emitting device including: a reflective layer which reflects light emitting from the light emitting layer; and at least one metal layer which is formed between the reflective layer and the P-type clad layer.
    Type: Grant
    Filed: July 15, 2004
    Date of Patent: December 9, 2008
    Assignees: Samsung Electronics Co., Ltd., Gwangju Institute of Science and Technology
    Inventors: June-o Song, Tae-yeon Seong
  • Patent number: 7462869
    Abstract: A first semiconductor light emitting device includes: a transparent substrate; a light emitting layer; and a roughened region. The transparent substrate has a first major surface and a second major surface, and is translucent to light in a first wavelength band. The light emitting layer is selectively provided in a first portion on the first major surface of the transparent substrate and configured to emit light in the first wavelength band. The roughened region is provided in a second portion different from the first portion on the first major surface. A second semiconductor light emitting device includes: a transparent substrate; a light emitting layer; a first electrode; and at least one groove. The groove is provided on the second major surface of the transparent substrate and extends from a first side face to a second side face opposing the first side face of the transparent substrate.
    Type: Grant
    Filed: March 13, 2007
    Date of Patent: December 9, 2008
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Kenichi Ohashi, Yasuhiko Akaike, Hitoshi Sugiyama, Yasuharu Sugawara
  • Publication number: 20080290371
    Abstract: A semiconductor structure includes a Group III-nitride semiconductor layer, a protective layer on the semiconductor layer, a distribution of implanted dopants within the semiconductor layer, and an ohmic contact extending through the protective layer to the semiconductor layer.
    Type: Application
    Filed: August 5, 2008
    Publication date: November 27, 2008
    Inventors: Scott T. Sheppard, Adam Saxler
  • Patent number: 7456445
    Abstract: A Group III nitride semiconductor light emitting device having a light emitting layer (6) bonded to a crystal layer composed of an n-type or p-type Group III nitride semiconductor, the Group III nitride semiconductor light emitting device being characterized by comprising an n-type Group III nitride semiconductor layer (4) having germanium (Ge) added thereto and having a resistivity of 1×10?1 to 1×10?3 ?cm. The invention provides a Ge-doped n-type Group III nitride semiconductor layer with low resistance and excellent flatness, in order to obtain a Group III nitride semiconductor light emitting device exhibiting low forward voltage and excellent light emitting efficiency.
    Type: Grant
    Filed: May 20, 2005
    Date of Patent: November 25, 2008
    Assignee: Showa Denko K.K.
    Inventors: Hitoshi Takeda, Syunji Horikawa
  • Patent number: 7436045
    Abstract: A gallium nitride-based semiconductor device has a p-type layer that is a gallium nitride (GaN) compound semiconductor layer containing a p-type impurity and exhibiting p-type conduction. The p-type layer includes a top portion and an inner portion located under the top portion. The inner portion contains the p-type impurity and, in combination therewith, hydrogen. The top portion includes a region containing a Group III element and a Group V element at a non-stoichiometric atomic ratio.
    Type: Grant
    Filed: March 3, 2005
    Date of Patent: October 14, 2008
    Assignee: Showa Denko K.K.
    Inventors: Masato Kobayakawa, Hideki Tomozawa, Hisayuki Miki
  • Patent number: 7420227
    Abstract: The present invention is a compound semiconductor device characterized in that it is Cu-metalized to improved the reliability of the device and to greatly reduce the cost of production.
    Type: Grant
    Filed: June 22, 2005
    Date of Patent: September 2, 2008
    Assignee: National Chiao Tung University
    Inventors: Edward Yi Chang, Shang-Wen Chang, Cheng-Shih Lee
  • Patent number: 7417264
    Abstract: Provided are a top-emitting N-based light emitting device and a method of manufacturing the same. The device includes a substrate, an n-type clad layer, an active layer, a p-type clad layer, and a multi ohmic contact layer, which are sequentially stacked. The multi ohmic contact layer includes one or more stacked structures, each including a modified metal layer and a transparent conductive thin film layer, which are repetitively stacked on the p-type clad layer. The modified metal layer is formed of an Ag-based material.
    Type: Grant
    Filed: December 15, 2004
    Date of Patent: August 26, 2008
    Assignees: Samsung Electronics Co., Ltd., Gwangju Institute of Science and Technology
    Inventors: June-o Song, Tae-yeon Seong, Joon-seop Kwak, Woong-ki Hong
  • Publication number: 20080179743
    Abstract: There is provided a technology for obtaining an electrode having a low contact resistance and less surface roughness. There is provided an electrode comprising a semiconductor film 101, and a first metal layer 102 and a second metal layer 103 sequentially stacked in this order on the semiconductor film 101, characterized in that the first metal film 102 is formed of Al, and the second metal film 103 is formed of at least one metal selected from the group consisting of Nb, W, Fe, Hf, Re, Ta and Zr.
    Type: Application
    Filed: January 8, 2008
    Publication date: July 31, 2008
    Inventors: Tatsuo Nakayama, Hironobu Miyamoto, Yuji Ando, Takashi Inoue, Yasuhiro Okamoto, Masaaki Kuzuhara
  • Patent number: 7402841
    Abstract: An object of the present invention is to provide a light-permeable electrode for use in a gallium nitride-based compound semiconductor light-emitting device, the electrode having improved light permeability and contact resistance. The inventive electrode comprises a light-permeable first layer which is in contact with a surface of a p-contact layer in a gallium nitride-based compound semiconductor light-emitting device and which is capable of providing ohmic contact, and a second layer which is in contact with a part of a surface of said p-contact layer, wherein the first layer comprises a metal, or an alloy of two or more metals, selected from a first group consisting of Au, Pt, Pd, Ni, Co, and Rh, and the second layer comprises an oxide of at least one metal selected from a second group consisting of Ni, Ti, Sn, Cr, Co, Zn, Cu, Mg, and In.
    Type: Grant
    Filed: September 21, 2004
    Date of Patent: July 22, 2008
    Assignee: Showa Denko K.K.
    Inventors: Hideki Tomozawa, Mineo Okuyama, Noritaka Muraki, Soichiro Masuyama
  • Patent number: 7335924
    Abstract: An LED structure is disclosed herein, which comprises, sequentially arranged in the following order, a light generating structure, a non-alloy ohmic contact layer, a metallic layer, and a substrate. As a reflecting mirror, the metallic layer is made of a pure metal or a metal nitride for achieving superior reflectivity. The non-alloy ohmic contact layer is interposed between the metallic layer and the light generating structure so as to achieve the required ohmic contact. To prevent the metallic layer from intermixing with the non-alloy ohmic contact layer and to maintain the flatness of the reflective surface of the first metallic layer, an optional dielectric layer is interposed between the metallic layer and the non-alloy ohmic contact layer.
    Type: Grant
    Filed: July 12, 2005
    Date of Patent: February 26, 2008
    Assignee: Visual Photonics Epitaxy Co., Ltd.
    Inventors: Jin-Hsiang Liu, Hui-Heng Wang, Kun-Chuan Lin
  • Patent number: 7329956
    Abstract: A semiconductor structure having a pore sealed portion of a dielectric layer is provided. Exposed pores of the dielectric material are sealed using an anisotropic plasma so that pores along the bottom of the opening are sealed, and pores along sidewalls of the opening remain relatively untreated by the plasma. Thereafter, one or more barrier layers may be formed and the opening may be filled with a conductive material. The barrier layers formed over the sealing layer exhibits a more continuous barrier layer. The pores may be partially or completely sealed by plasma bombardment or ion implantation using a gas selected from one of O2, an O2/N2 mixture, H2O, or combinations thereof.
    Type: Grant
    Filed: September 12, 2006
    Date of Patent: February 12, 2008
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chen-Hua Yu, Ching-Ya Wang
  • Patent number: 7285857
    Abstract: Provided are a p-type electrode and a III-V group GaN-based compound semiconductor device using the same. The electrode includes a first layer disposed on a III-V group nitride compound semiconductor layer and formed of a Zn-based material containing a solute; and a second layer stacked on the first layer and formed of at least one selected from the group consisting of Au, Co, Pd, Pt, Ru, Rh, Ir, Ta, Cr, Mn, Mo, Tc, W, Re, Fe, Sc, Ti, Sn, Ge, Sb, Al, ITO, and ZnO. The Zn-based p-type electrode has excellent electrical, optical, and thermal properties.
    Type: Grant
    Filed: September 30, 2004
    Date of Patent: October 23, 2007
    Assignees: Samsung Electronics Co., Ltd., Gwangju Institute of Science and Technology
    Inventors: Joon-seop Kwak, Tae-yeon Seong, Ok-hyun Nam, June-o Song, Dong-seok Leem
  • Patent number: 7253015
    Abstract: A repeatable and uniform low doped layer is formed using modulation doping by forming alternating sub-layers of doped and undoped nitride semiconductor material atop another layer. A Schottky diode is formed of such a low doped nitride semiconductor layer disposed atop a much more highly doped nitride semiconductor layer. The resulting device has both a low on-resistance when the device is forward biased and a high breakdown voltage when the device is reverse biased.
    Type: Grant
    Filed: February 17, 2004
    Date of Patent: August 7, 2007
    Assignee: Velox Semiconductor Corporation
    Inventors: Milan Pophristic, Michael Murphy, Richard A. Stall, Bryan S. Shelton, Linlin Liu, Alex D. Ceruzzi
  • Patent number: 7247891
    Abstract: A semiconductor device has a first nitride semiconductor layer, a second nitride semiconductor layer formed on the first nitride semiconductor layer and having such a composition as to generate a 2-dimensional electron gas layer in the upper portion of the first nitride semiconductor layer, and an electrode having an ohmic property and formed selectively on the second nitride semiconductor layer. The second nitride semiconductor layer includes a contact area having at least one inclined portion with a bottom or wall surface thereof being inclined toward the upper surface of the first nitride semiconductor layer and defining a depressed cross-sectional configuration. The electrode is formed on the contact area.
    Type: Grant
    Filed: October 22, 2004
    Date of Patent: July 24, 2007
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Atsuhiko Kanda, Tsuyoshi Tanaka, Yasuhiro Uemoto, Yutaka Hirose, Tomohiro Murata
  • Patent number: 7193249
    Abstract: Provided are a nitride-based light emitting device using a p-type conductive transparent thin film electrode layer and a method of manufacturing the same. The nitride-based light emitting device includes a substrate, and an n-cladding layer, an active layer, a p-cladding layer and an ohmic contact layer sequentially formed on the substrate. The ohmic contact layer is made from a p-type conductive transparent oxide thin film. The nitride-based light emitting device and method of manufacturing the same provide excellent I-V characteristics by improving characteristics of an ohmic contact to a p-cladding layer while enhancing light emission efficiency of the device due to high light transmittance exhibited by a transparent electrode.
    Type: Grant
    Filed: October 14, 2004
    Date of Patent: March 20, 2007
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Tae-yeon Seong, June-o Song, Dong-seok Leem
  • Patent number: 7193247
    Abstract: A GaN compound semiconductor device can be capable of free process design and can have optimum device characteristics. The device can include a group III nitride compound semiconductor laminate structure including an n-type GaN compound semiconductor layer and a p-type GaN compound semiconductor layer. An n electrode can be formed on the n-type GaN compound semiconductor layer, and a p electrode can be formed on the p-type GaN compound semiconductor layer. The n electrode preferably includes an Al layer of 1 to 10 nm, in contact with the n-type GaN compound semiconductor layer, and any metal layer of Rh, Ir, Pt, and Pd formed on the Al layer. The p electrode can be made of a 200 nm or less layer of of Pd, Pt, Rh, Pt/Rh, Pt/Ag, Rh/Ag, Pd/Rh, or Pd/Ag, in contact with the p-type GaN compound semiconductor layer. Both electrodes can make ohmic contact with respective n-type/p-type GaN semiconductors without application of active annealing.
    Type: Grant
    Filed: March 9, 2006
    Date of Patent: March 20, 2007
    Assignee: Stanley Electric Co., Ltd.
    Inventors: Masahiko Tsuchiya, Naochika Horio, Kenichi Morikawa
  • Patent number: 7193322
    Abstract: A strained-silicon (Si) channel CMOS device shallow trench isolation (STI) oxide region, and method for forming same have been provided. The method forms a Si substrate with a relaxed-SiGe layer overlying the Si substrate, or a SiGe on insulator (SGOI) substrate with a buried oxide (BOX) layer. The method forms a strained-Si layer overlying the relaxed-SiGe layer; a silicon oxide layer overlying the strained-Si layer, a silicon nitride layer overlying the silicon oxide layer, and etches the silicon nitride layer, the silicon oxide layer, the strained-Si layer, and the relaxed-SiGe layer, forming a STI trench with trench corners and a trench surface. The method forms a sacrificial oxide liner on the STI trench surface. In response to forming the sacrificial oxide liner, the method rounds and reduces stress at the STI trench corners, removes the sacrificial oxide liner, and fills the STI trench with silicon oxide.
    Type: Grant
    Filed: November 9, 2004
    Date of Patent: March 20, 2007
    Assignee: Sharp Laboratories of America, Inc.
    Inventors: Jong-Jan Lee, Sheng Teng Hsu
  • Patent number: 7190076
    Abstract: A GaN layer is formed on a sapphire substrate through an AlN buffer layer and doped with Mg to prepare a laminate (referred to as “GaN substrate”). A metal (Pt and Ni) electrode 50 nm thick is formed on the GaN substrate by (1) vapor deposition after the GaN substrate is heated to a temperature of 300° C. or by (2) vapor deposition while the GaN substrate is left at room temperature. (3) The electrode obtained in (2) is heated to 300° C. in a nitrogen atmosphere. The contact resistance of the electrode obtained in (1) is lower by two or three digits than that of the electrode obtained in (2) or (3). That is, the electric characteristic of the electrode obtained in (1) is improved greatly.
    Type: Grant
    Filed: October 29, 2003
    Date of Patent: March 13, 2007
    Assignee: Toyoda Gosei Co., Ltd.
    Inventors: Ippei Fujimoto, Tsutomu Sekine, Miki Moriyama, Masanori Murakami, Naoki Shibata
  • Patent number: 7154180
    Abstract: In an electronic device comprising a first electrodes consisting of a metal oxide and a second electrode consisting of an aluminum alloy film directly contacted and electrically connected to the first electrode, the contact interface between the aluminum alloy film and the first electrode is constructed so that at least a part of alloy components constituting the aluminum alloy film exist as a precipitate or concentrated layer. This construction enables direct contact between the aluminum alloy film and the electrode consisting of a metallic oxide and allows elimination of a barrier metal in such an electronic device, and manufacturing technology therefor.
    Type: Grant
    Filed: April 15, 2005
    Date of Patent: December 26, 2006
    Assignee: Kobe Steel, Ltd.
    Inventors: Hiroshi Gotoh, Toshihiro Kugimiya, Junichi Nakai, Katsufumi Tomihisa
  • Patent number: 7145237
    Abstract: An electrode employing a nitride-based semiconductor of III–V group compound having a favorable ohmic characteristic and a producing method thereof are provided. The electrode includes a nitride-based semiconductor layer of III–V group compound, an electrode metal, and a metal oxide inserted therebetween. The metal oxide is preferably an oxide of metal element(s) permitting formation of a nitride semiconductor.
    Type: Grant
    Filed: February 3, 2004
    Date of Patent: December 5, 2006
    Assignee: Sharp Kabushiki Kaishi
    Inventor: Nobuaki Teraguchi
  • Patent number: 7135772
    Abstract: The present invention is a nitride compound semiconductor laser, in which a cleaved end face is flat, and a breakdown of a laser end face induced during an operation can be suppressed, which consequently enables a life to be prolonged. In the nitride compound semiconductor laser, a stress concentration suppression layer is formed between an active layer and a cap layer.
    Type: Grant
    Filed: March 25, 2005
    Date of Patent: November 14, 2006
    Assignee: Sony Corporation
    Inventors: Shigetaka Tomiya, Tomonori Hino
  • Patent number: 7109529
    Abstract: A flip chip type of light-emitting semiconductor device using group III nitride compound includes a thick positive electrode. The positive electrode, which is made of at least one of silver (Ag), rhodium (Rh), ruthenium (Ru), platinum (Pt) and palladium (Pd), and an alloy including at least one of these metals, is adjacent to a p-type semiconductor layer, and reflect light toward a sapphire substrate. Accordingly, a positive electrode having a high reflectivity and a low contact resistance can be obtained. A first thin-film metal layer, which is made of cobalt (Co) and nickel (Ni), or any combinations of including at least one of these metals, formed between the p-type semiconductor layer and the thick electrode, can improve an adhesion between an contact layer and the thick positive electrode. A thickness of the first thin-film metal electrode should be preferably in the range of 2 ? to 200 ?, more preferably 5 ? to 50 ?. A second thin-film metal layer made of gold (Au) can further improve the adhesion.
    Type: Grant
    Filed: June 10, 2004
    Date of Patent: September 19, 2006
    Assignee: Toyoda Gosei Co., Ltd.
    Inventors: Toshiya Uemura, Shigemi Horiuchi
  • Patent number: 7061110
    Abstract: An ohmic contact of semiconductor and its manufacturing method are disclosed. The present invention provides a low resistivity ohmic contact so as to improve the performance and reliability of the semiconductor device. This ohmic contact is formed by first coating a transition metal and a noble metal on a semiconductor material; then heat-treating the transition metal and the noble metal in an oxidizing environment to oxidize the transition metal. In other words, this ohmic contact primarily includes a transition metal oxide and a noble metal. The oxide in the film can be a single oxide, or a mixture of various oxides, or a solid solution of various oxides. The metal of the film can be a single metal, or various metals or an alloy thereof. The structure of the film can be a mixture or a laminate or multilayered including oxide and metal. The layer structure includes at least one oxide layer and one metal layer, in which at least one oxide layer is contacting to semiconductor.
    Type: Grant
    Filed: September 1, 1999
    Date of Patent: June 13, 2006
    Assignee: Industrial Technology Research Institute
    Inventors: Jin-Kuo Ho, Charng-Shyang Jong, Chao-Nien Huang, Chin-Yuan Chen, Chienchia Chiu, Chenn-shiung Cheng, Kwang Kuo Shih
  • Patent number: 7057210
    Abstract: An electrode for a light-emitting semiconductor device includes a light-permeable electrode formed to come into contact with the surface of the semiconductor, and a wire-bonding electrode that is in electrical contact with the light-permeable electrode and is formed to come into partial contact with the surface of the semiconductor with at least a region in contact with the semiconductor having a higher contact resistance per unit area with respect to the semiconductor than a region of the light-permeable electrode in contact with the semiconductor.
    Type: Grant
    Filed: March 16, 2004
    Date of Patent: June 6, 2006
    Assignee: Showa Denko K.K.
    Inventors: Hisayuki Miki, Takashi Udagawa, Noritaka Muraki, Mineo Okuyama
  • Patent number: 7042089
    Abstract: An object of the present invention is to provide a large-size light-emitting device from which uniform light emission can be obtained. That is, in the present invention, in a device having an outermost diameter of not smaller than 700 ?m, a distance from an n electrode to a farthest point of a p electrode is selected to be not larger than 500 ?m.
    Type: Grant
    Filed: June 17, 2004
    Date of Patent: May 9, 2006
    Assignee: Toyoda Gosei Co., Ltd.
    Inventors: Toshiya Uemura, Atsuo Hirano, Koichi Ota, Naohisa Nagasaka
  • Patent number: 7019336
    Abstract: In a nitride-system semiconductor, being different from GaAs and Si, Schottky barrier heights ?B change significantly against work functions ?M of metals. Then, for example, on an HEMT in which a buffer layer and a barrier layer constituted by nitride-system semiconductors are sequentially formed on a substrate, and a gate electrode is formed on the barrier layer, when a metal having a relatively large work function ?M is selected as a metal constituting the gate electrode, and the thickness of the barrier layer is adjusted so that the Schottky barrier height ?B becomes larger as compared to a semiconductor surface potential ?S on both sides of the gate electrode, a two-dimensional electron gas cannot exist below the gate electrode even when no recess is formed on a portion immediately beneath the gate electrode on the barrier layer, so that the enhancement operation becomes possible.
    Type: Grant
    Filed: June 21, 2004
    Date of Patent: March 28, 2006
    Assignee: Fujitsu Limited
    Inventors: Yoshimi Yamashita, Akira Endoh, Keiji Ikeda
  • Patent number: 7018915
    Abstract: An AlN buffer layer 2; a silicon (Si)-doped GaN high-carrier-concentration n+ layer 3; an Si-doped n-type Al0.07Ga0.93N n-cladding layer 4; an Si-doped n-type GaN n-guide layer 5; an active layer 6 having a multiple quantum well (MQW) structure, and including a Ga0.9In0.1N well layer 61 (thickness: about 2 nm) and a Ga0.97In0.03N barrier layer 62 (thickness: about 4 nm), the layers 61 and 62 being laminated alternately; an Mg-doped GaN p-guide layer 7; an Mg-doped Al0.07Ga0.93N p-cladding layer 8; and an Mg-doped GaN p-contact layer 9 are successively formed on a sapphire substrate. A p-electrode 10 is formed of a film of titanium nitride (TiN) or tantalum nitride (TaN) (thickness: 50 nm). The contact resistance of this electrode is reduced through heat treatment.
    Type: Grant
    Filed: June 4, 2004
    Date of Patent: March 28, 2006
    Assignee: Toyoda Gosei Co., Ltd.
    Inventors: Naoki Shibata, Toshiya Uemura, Makoto Asai, Yasuo Koide, Masanori Murakami
  • Patent number: 7005680
    Abstract: The semiconductor light-emitting device of the present invention includes a first semiconductor layer of a first conductivity type formed substantially in a uniform thickness on a substrate and a second semiconductor layer of a second conductivity type formed substantially in a uniform thickness on the first semiconductor layer. The device further includes an active layer, formed substantially in a uniform thickness between the first semiconductor layer and the second semiconductor layer, for generating emission light. The device also comprises a first electrode for supplying a drive current to the first semiconductor layer and a second electrode for supplying a drive current to the second semiconductor layer. The device is adapted that the first or second electrode is a divided electrode comprising a plurality of conductive members spaced apart from each other.
    Type: Grant
    Filed: October 7, 2003
    Date of Patent: February 28, 2006
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Nobuyuki Otsuka, Yoshiaki Hasegawa, Gaku Sugahara, Yasutoshi Kawaguchi
  • Patent number: 7005684
    Abstract: In a flip chip type Group III nitride compound semiconductor light-emitting element, an Au layer is provided on each of a surface of a p-side electrode and a surface of an n-side electrode with interposition of a Ti layer.
    Type: Grant
    Filed: June 3, 2002
    Date of Patent: February 28, 2006
    Assignee: Toyoda Gosei Co., Ltd.
    Inventors: Toshiya Uemura, Shigemi Horiuchi
  • Patent number: 6998649
    Abstract: A semiconductor light-emitting device capable of attaining a surface plasmon effect while attaining excellent ohmic contact is provided. This semiconductor light-emitting device comprises a semiconductor layer formed on an emission layer, a first electrode layer formed on the semiconductor layer and a second electrode layer, formed on the first electrode layer, having a periodic structure. The first electrode layer is superior to the second electrode layer in ohmic contact with respect to the semiconductor layer, and the second electrode layer contains a metal exhibiting a higher plasma frequency than the first electrode layer.
    Type: Grant
    Filed: September 29, 2004
    Date of Patent: February 14, 2006
    Assignee: Sanyo Electric Co., Ltd.
    Inventor: Masayuki Hata
  • Patent number: 6998690
    Abstract: A gallium nitride-based III-V Group compound semiconductor device has a gallium nitride-based III-V Group compound semiconductor layer provided over a substrate, and an ohmic electrode provided in contact with the semiconductor layer. The ohmic electrode is formed of a metallic material, and has been annealed.
    Type: Grant
    Filed: July 1, 2003
    Date of Patent: February 14, 2006
    Assignee: Nichia Corporation
    Inventors: Shuji Nakamura, Takao Yamada, Masayuki Senoh, Motokazu Yamada, Kanji Bando
  • Patent number: 6992334
    Abstract: A high performance, highly reflective ohmic contact, in the visible spectrum (400 nm–750 nm), has the following multi-layer metal profile. A uniform and thin ohmic contact material is deposited and optionally alloyed to the semiconductor surface. A thick reflector layer selected from a group that includes Al, Cu, Au, Rh, Pd, Ag and any multi-layer combinations is deposited over the ohmic contact material.
    Type: Grant
    Filed: December 22, 1999
    Date of Patent: January 31, 2006
    Assignee: Lumileds Lighting U.S., LLC
    Inventors: Jonathan J. Wierer, Jr., Michael R Krames, Serge L Rudaz
  • Patent number: 6946685
    Abstract: Silver electrode metallization in light emitting devices is subject to electrochemical migration in the presence of moisture and an electric field. Electrochemical migration of the silver metallization to the pn junction of the device results in an alternate shunt path across the junction, which degrades efficiency of the device. In accordance with a form of this invention, a migration barrier is provided for preventing migration of metal from at least one of the electrodes onto the surface of the semiconductor layer with which the electrode is in contact.
    Type: Grant
    Filed: August 31, 2000
    Date of Patent: September 20, 2005
    Assignee: Lumileds Lighting U.S., LLC
    Inventors: Daniel A. Steigerwald, Michael J. Ludowise, Steven A. Maranowski, Serge L. Rudaz, Jerome C. Bhat
  • Patent number: 6933545
    Abstract: The present invention provides a hetero-bipolar transistor having a new configuration of the interconnection. The bipolar transistor of the present invention includes the collector mesa, having the base and collector layers therein, includes a first side having a normal mesa surface and extending along the [01-1] orientation, and a second side having a reverse mesa surface and extending along the [011] orientation. The present HBT has a base interconnection, a portion of which diagonally intersects the first side of the collector mesa, accordingly, the breaking of the interconnection may not occur and the high frequency performance of the HBT may be enhanced because the width of the collector mesa is not necessary to widen to disposed the base interconnection on the first side.
    Type: Grant
    Filed: June 3, 2004
    Date of Patent: August 23, 2005
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Takeshi Kawasaki, Hiroshi Yano
  • Patent number: 6921927
    Abstract: A light emitting device assembly comprises a light emitting diode (LED) chip, a substrate with two terminals, at least one encapsulation layer, and a thermally conductive adhesive to connect the LED chip and the substrate. The first terminal of the substrate is comprised of a portion with a width at least as wide as the LED chip and a vertical cross-sectional area of at least 30% of the total vertical cross-sectional area of the encapsulated assembly, and a straight element. The enlarged first terminal portion provides more area for heat dissipation and conduction, and along with the thermally conductive adhesive and the encapsulation package, provide enhanced thermal conductivity.
    Type: Grant
    Filed: August 28, 2003
    Date of Patent: July 26, 2005
    Assignee: Agilent Technologies, Inc.
    Inventors: Kee Yean Ng, Sundar A. L. N. Yoganandan
  • Patent number: 6919583
    Abstract: An edge-emitting thyristor having an improved external luminous efficiency and a self-scanning light-emitting device array comprising the edge-emitting thyristor are disclosed. To improve the external luminous efficiency of an edge-emitting light-emitting thyristor, a structure where the current injected from an electrode concentrates on and near the edge of the light-emitting thyristor is adopted.
    Type: Grant
    Filed: February 11, 2004
    Date of Patent: July 19, 2005
    Assignee: Nippon Sheet Glass Company, Limited
    Inventors: Takashi Tagami, Yukihisa Kusuda, Seiji Ohno, Nobuyuki Komaba
  • Patent number: 6903392
    Abstract: A semiconductor device having a single-crystal substrate made of a material different from nitride III-V compound semiconductors, and a device made on one major surface of said single-crystal substrate by using III-V compound semiconductors, including electrical connection to said device being made through a via hole formed in said single-crystal substrate and method of making the same.
    Type: Grant
    Filed: January 24, 2001
    Date of Patent: June 7, 2005
    Assignee: Sony Corporation
    Inventor: Hiroji Kawai
  • Patent number: 6894391
    Abstract: An electrode structure on a p-type III group nitride semiconductor layer includes first, second and third electrode layers successively stacked on the semiconductor layer. The first electrode layer includes at least one selected from a first metal group of Ti, Hf, Zr, V, Nb, Ta, Cr, W and Sc. The second electrode layer includes at least one selected from a second metal group of Ni, Pd and Co. The third electrode layer includes Au.
    Type: Grant
    Filed: April 25, 2000
    Date of Patent: May 17, 2005
    Assignee: Sharp Kabushiki Kaisha
    Inventor: Kunihiro Takatani
  • Patent number: 6891268
    Abstract: The present invention is a nitride compound semiconductor laser, in which a cleaved end face is flat, and a breakdown of a laser end face induced during an operation can be suppressed, which consequently enables a life to be prolonged. In the nitride compound semiconductor laser, a stress concentration suppression layer is formed between an active layer and a cap layer.
    Type: Grant
    Filed: June 4, 2002
    Date of Patent: May 10, 2005
    Assignee: Sony Corporation
    Inventors: Shigetaka Tomiya, Tomonori Hino
  • Patent number: 6888245
    Abstract: A semiconductor device includes a conductive layer formed on a silicon semiconductor substrate, cobalt silicide films formed in a surface layer of the conductive layer, an interlayer insulating film which covers the silicon semiconductor substrate thereabove, and a barrier metal film and a tungsten film which fill in a contact hole formed in the interlayer insulating film and is electrically connected to the cobalt silicide film. The positions of lower surfaces of the cobalt silicide films at the bottom of the contact hole are set lower than the position of a lower surface of the cobalt silicide film provided outside the contact hole. A cobalt silicide film having a necessary thickness can be ensured at the bottom of the contact hole. Further, a contact resistance can be reduced and a junction leak can be suppressed.
    Type: Grant
    Filed: August 19, 2002
    Date of Patent: May 3, 2005
    Assignee: Renesas Technology Corp.
    Inventor: Kazuhiro Tsukamoto
  • Patent number: 6872986
    Abstract: A nitride semiconductor element exhibiting low leakage current and high ESD tolerance includes an active layer of nitride semiconductor that is interposed between a p-sided layer and an n-sided layer, which respectively consist of a plurality of nitride semiconductor layers, the p-side layer including a p-type contact layer as a layer for forming p-ohmic electrodes, the p-type contact layer being formed by laminating p-type nitride semiconductor layers and n-type nitride semiconductor layers in an alternate manner.
    Type: Grant
    Filed: July 3, 2002
    Date of Patent: March 29, 2005
    Assignee: Nichia Corporation
    Inventors: Yoshikatsu Fukuda, Akira Fujioka
  • Patent number: 6858878
    Abstract: A light shield film is provided adjacent to an anode of an EL element that consists of the anode, an EL layer, and a cathode. The anode and the cathode are transparent or semitransparent to visible light and hence transmit EL light. With this structure, ambient light is absorbed by the light shield film and does not reach an observer. This prevents an external view from appearing on the observation surface.
    Type: Grant
    Filed: January 7, 2003
    Date of Patent: February 22, 2005
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Jun Koyama
  • Publication number: 20040238837
    Abstract: A radiation-emitting semiconductor component, having a layer structure (30) which includes an active layer (32) which, in operation, emits radiation with a spectral distribution (60), and electrical contacts (36, 38, 40) for applying a current to the layer structure (30), includes a coating layer (44) which at least partially surrounds the active layer (32) and holds back a short-wave component of the emitted radiation (60).
    Type: Application
    Filed: July 6, 2004
    Publication date: December 2, 2004
    Applicant: OSRAM OPTO SEMICONDUCTORS GMBH
    Inventors: Ulrich Jacob, Gertrud Krauter, Andreas Plossl
  • Patent number: 6822307
    Abstract: A semiconductor triode comprises a gate electrode provided on a channel layer, wherein there is interposed an insulating metal oxide layer between a top surface of the channel layer and the gate electrode.
    Type: Grant
    Filed: December 26, 2000
    Date of Patent: November 23, 2004
    Assignee: Fujitsu Limited
    Inventors: Mizuhisa Nihei, Yuu Watanabe
  • Publication number: 20040222524
    Abstract: Disclosed herein is a technique for forming a high quality ohmic contact utilizable in the fabrication of short-wavelength light emitting diodes (LEDs) emitting blue and green visible light and ultraviolet light, and laser diodes (LDs) using a gallium nitride (GaN) semiconductor.
    Type: Application
    Filed: March 17, 2004
    Publication date: November 11, 2004
    Applicants: Samsung Electronics Co., Ltd., Kwangju Institute of Science and Technology
    Inventors: June-o Song, Dong-suk Leem, Tae-yeon Seong
  • Patent number: 6812570
    Abstract: An organic carrier member for mounting a semiconductor device is provided that has a plurality of solder pads containing low amounts of tin and bismuth. Embodiments include a bismaleimide-triazine epoxy laminate having a plurality of solder pads on the surface thereof where the solder pads contain no more than about 20 weight percent tin and has a reflow temperature of no greater than about 270° C.
    Type: Grant
    Filed: June 28, 2002
    Date of Patent: November 2, 2004
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Raj N. Master, Mohammad Zubair Khan, Maria Guardado, Charles Anderson
  • Patent number: 6809352
    Abstract: The semiconductor device of the present invention includes: a gallium nitride (GaN) compound semiconductor layer; and a Schottky electrode formed on the GaN compound semiconductor layer, wherein the Schottky electrode contains silicon.
    Type: Grant
    Filed: December 27, 2002
    Date of Patent: October 26, 2004
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Katsunori Nishii, Yoshito Ikeda, Hiroyuki Masato, Kaoru Inoue
  • Patent number: 6806571
    Abstract: An AlN buffer layer 2; a silicon (Si)-doped GaN high-carrier-concentration n+ layer 3; an Si-doped n-type Al0.07Ga0.93N n-cladding layer 4; an Si-doped n-type GaN n-guide layer 5; an active layer 6 having a multiple quantum well (MQW) structure, and including a Ga0.9In0.1N well layer 61 (thickness: about 2 nm) and a Ga0.97In0.03N barrier layer 62 (thickness: about 4 nm), the layers 61 and 62 being laminated alternately; an Mg-doped GaN p-guide layer 7; an Mg-doped Al0.07Ga0.93N p-cladding layer 8; and an Mg-doped GaN p-contact layer 9 are successively formed on a sapphire substrate. A p-electrode 10 is formed of a film of titanium nitride (TiN) or tantalum nitride (TaN) (thickness: 50 nm). The contact resistance of this electrode is reduced through heat treatment.
    Type: Grant
    Filed: February 19, 2003
    Date of Patent: October 19, 2004
    Assignee: Toyoda Gosei Co., Ltd.
    Inventors: Naoki Shibata, Toshiya Uemura, Makoto Asai, Yasuo Koide, Masanori Murakami