Abstract: An electrode employing a nitride-based semiconductor of III-V group compound having a favorable ohmic characteristic and a producing method thereof are provided. The electrode includes a nitride-based semiconductor layer of III-V group compound, an electrode metal, and a metal oxide inserted therebetween. The metal oxide is preferably an oxide of metal element(s) permitting formation of a nitride semiconductor.

Abstract: A GaAsP-base light emitting element capable of sustaining an excellent light emission property for a long period, and a method for manufacturing thereof are provided. The light emitting element 1 has a p-n junction interface responsible for light emission formed between a p-type GaAs1-aPa layer 9 and an n-type GaAs1-aPa layer 8, and has a nitrogen-doped zone 8c formed in a portion including the p-n junction interface between such p-type GaAs1-aPa layer 9 and n-type GaAs1-aPa layer 8. Such element can be manufactured by fabricating a plurality of light emitting elements by varying nitrogen concentration Y of the nitrogen-doped zone 8c while keeping a mixed crystal ratio a of the p-type GaAs1- aPa layer 9 and n-type GaAs1-aPa layer 8 constant; finding an emission luminance/nitrogen concentration relationship by measuring emission luminance of the individual light emitting elements; and adjusting the nitrogen concentration of the nitrogen-doped zone 8c so as to fall within a range from 1.05Yp to 1.

Abstract: A superlattice contact structure for light emitting devices includes a plurality of contiguous p-type Group III nitride layers. The contact structure may be formed of p-type indium nitride, aluminum indium nitride, or indium gallium nitride. Also disclosed is a light emitting device that incorporates the disclosed contact structures.

Abstract: An object of the present invention is to provide a large-size light-emitting device from which uniform light emission can be obtained. That is, in the present invention, in a device having an outermost diameter of not smaller than 700 &mgr;m, a distance from an n electrode to a farthest point of a p electrode is selected to be not larger than 500 &mgr;m.

Abstract: A GaN layer is formed on a sapphire substrate through an AlN buffer layer and doped with Mg to prepare a laminate (referred to as “GaN substrate”). A metal (Pt and Ni) electrode 50 nm thick is formed on the GaN substrate by (1) vapor deposition after the GaN substrate is heated to a temperature of 300° C. or by (2) vapor deposition while the GaN substrate is left at room temperature. (3) The electrode obtained in (2) is heated to 300° C. in a nitrogen atmosphere. The contact resistance of the electrode obtained in (1) is lower by two or three digits than that of the electrode obtained in (2) or (3). That is, the electric characteristic of the electrode obtained in (1) is improved greatly.

Abstract: An undoped In0.52Al0.48As buffer layer (thickness: 500 nm), an undoped In0.53Ga0.47As channel layer (thickness: 30 nm), an n-type delta doped layer for shortening the distance between the channel layer and a gate electrode and attaining a desired carrier density, an undoped In0.52Al0.48As Schottky layer, and an n-type In0.53Ga0.47As cap layer doped with Si (thickness: 50 nm) are formed in this order on the principal surface of an Fe-doped InP semi-insulating substrate. An n-type GaAs protective layer doped with Si (thickness: 7.5 nm) is formed between the cap layer and source/drain electrodes for protecting the cap layer.

Abstract: A field effect transistor (FET) is disclosed that includes a heat spreader adapted to reduce the thermal resistance and channel operating temperature of a field effect transistor used in a circuit block susceptible to self-heating effects. In one embodiment, regulatory circuit blocks of an integrated circuit, such as phase locked loops, utilize the FET to improve the characteristics of a regulatory output required by other circuit blocks, such as digital logic circuits. In one embodiment the FET is a silicon-on-insulator structure.

Abstract: A semiconductor light receiving element having a light receiving layer (1) formed from a GaN group semiconductor, and an electrode (2) formed on one surface of the light receiving layer as a light receiving surface (1a) in such a way that the light (L) can enter the light receiving layer is provided. When the light receiving element is of a Schottky barrier type, the aforementioned electrode (2) contains at least a Schottky electrode, which is formed in such a way that, on the light receiving surface (1a), the total length of the boundary lines between areas covered with the Schottky electrode and exposed areas is longer than the length of the outer periphery of the light receiving surface (1a).

Abstract: A gallium nitride-based HEMT device, comprising a channel layer formed of an InGaN alloy. Such device may comprise an AlGaN/InGaN heterostructure, e.g., in a structure including a GaN layer, an InGaN layer over the GaN layer, and a (doped or undoped) AlGaN layer over the InGaN layer. Alternatively, the HEMT device of the invention may be fabricated as a device which does not comprise any aluminum-containing layer, e.g., a GaN/InGaN HEMT device or an InGaN/InGaN HEMT device.

Abstract: A LED of flip-chip design comprises a light emitting region and one or more transparent substrates overlying the light emitting region. The light emitting region includes a negatively doped layer, a positively doped layer, and an active p-n junction layer between the negatively doped layer and the positively doped layer. At least one of the substrates has a pyramidal shape determined by (1) the composition of electrically conductive or electrically non-conductive material, (2) the number of side surfaces, (3) the degree of offset of an apex or top surface, and (4) the slope angle of each side surface relative to a bottom surface.

Abstract: A self-scanning light-emitting element array using an end face light-emitting thyristor having improved external emission efficiency is provided. To improve the external emission efficiency of the end face light-emitting thyristor, the present invention adopts such structure that the current injected from an anode is concentrated to near the end face of the light-emitting thyristor. A self-scanning light-emitting element array is implemented by using such end face light-emitting thyristor.

Abstract: A Pt alloyed reaction layer is formed under a base ohmic electrode. This alloyed reaction layer extends through a base protective layer so as to reach a base layer. Besides, a Pt alloyed reaction layer is formed under an emitter ohmic electrode. This alloyed reaction layer is formed only within a second emitter contact layer. With this constitution, the manufacturing cost for the HBT can be reduced and successful contact characteristics for the HBT can be obtained.

Abstract: P-type layers of a GaN based light-emitting device are optimized for formation of Ohmic contact with metal. In a first embodiment, a p-type GaN transition layer with a resistivity greater than or equal to about 7 &OHgr;cm is formed between a p-type conductivity layer and a metal contact. In a second embodiment, the p-type transition layer is any III-V semiconductor. In a third embodiment, the p-type transition layer is a superlattice. In a fourth embodiment, a single p-type layer of varying composition and varying concentration of dopant is formed.

Abstract: For improving the light output, a light-emitting diode has at least one section of a light exit-side surface covered with a plurality of truncated pyramids. Light radiations, which are emitted by a light-generating layer, enter into the truncated pyramids through a base area and are efficiently coupled out of the sidewalls of the pyramids.

Abstract: An FET (Field Effect Transistor) has an epitaxial wafer including an Al0.2Ga0.8As gate contact layer. A GaAs gate buried layer doped with Si, Al0.2Ga0.8As wide-recess stopper layer doped with Si, an undoped GaAs layer and a GaAs cap layer doped with Si are sequentially formed on the gate contact layer by epitaxial growth. An electron accumulation layer is formed on the undoped GaAs layer and reduces a potential barrier. This allows electrons to pass through the potential barrier of the AlGaAs layer with higher probability. Because the GaAs layer is not doped with an impurity, electrons are scattered little and achieve higher mobility. It is therefore possible to reduce contact resistance from the cap layer to a channel layer. In addition, sheet resistance sparingly increases because the gate contact layer is not exposed to the outside. An ON resistance as low as 1.4 &OHgr;·mm is achievable which is lower than the conventional ON resistance by 0.2 &OHgr;·mm.

Abstract: A method for cooling an MOVPE deposited, As-containing, P-type contact layer includes cooling the contact layer in an arsine environment to preserve the contact layer during the initial stages of the cooling process until a threshold temperature in the range of 560 to 580° C. is attained. During the cooling process, the arsine flow is reduced with respect to the arsine flow used during the MOVPE deposition. After the threshold temperature is attained, the arsine gas is withdrawn and the contact layer is cooled further. Because of the removal of the arsine gas at the threshold temperature, free carrier concentration within the contact layer is enhanced above the atomic concentration of the P-type dopant, and contact resistance is improved to a suitably low level. A semiconductor optoelectronic device is formed to include such a contact layer, the P-type dopant impurity present in an atomic concentration and the contact layer having a free carrier concentration being greater than the atomic concentration.

Abstract: This invention has an objective to provide a field effect transistor semiconductor which has great adhesiveness between a gate metal and an insulating film defining a gate electrode end and to improve production yield thereof.

Abstract: An undoped GaN buffer layer, an n-type GaN layer and a p-type GaN layer are successively formed on a sapphire substrate, and a partial region from the p-type GaN layer to the n-type GaN layer is removed, to expose the n-type GaN layer. Ti films having a thickness of 3 to 100 Å and Pt films are successively formed on the p-type GaN layer and on the exposed upper surfaces of the n-type GaN layer. Consequently, a p electrode in ohmic contact with the p-type GaN layer and an n electrode in ohmic contact with the n-type GaN layer are formed without being alloyed by heat treatment.

Abstract: A method of manufacturing a semiconductor device having an improved ohmic contact system. The improved ohmic contact system comprises a thin reactive layer of platinum deposited on a portion of the base layer. The improved ohmic contact system further comprises a thick refractory layer of titanium or other suitable material deposited on the thin reactive layer. Both the reactive layer and the refractory layer are substantially free of gold. The improved ohmic contact system and method for forming the same eliminate base contact punchthrough on high performance semiconductor devices, such as heterojunction bipolar transistors, minimize raw material costs, and decrease manufacturing costs.

Abstract: A Group III nitride compound semiconductor light-emitting element (flip chip type light-emitting element) provided with a p-side electrode and an n-side electrode formed on one surface side, wherein the p-side electrode includes: a first metal layer containing Ag and formed on a p-type semiconductor layer; a protective film with which the first metal layer except a part region is covered; and a second metal layer not containing Ag and formed on the protective film.

Abstract: A nitride semiconductor laser device of high reliability such that the width of contact between a p-side ohmic electrode and a p-type contact layer is precisely controlled. The device comprises a substrate, an n-type nitride semiconductor layer, an active layer, and a p-type nitride semiconductor layer. All the layers are formed in order on the substrate. A ridge part including the uppermost layer of the p-type nitride semiconductor layer of the p-type nitride semiconductor layer i.e., a p-type contact layer is formed in the p-type nitride semiconductor layer. A p-side ohmic electrode is formed on the p-type contact layer of the top of the ridge part. A first insulating film having an opening over the top of the ridge part covers the side of the ridge part and the portion near the side of the ridge part. The p-side ohmic electrode is in contact with the p-type contact layer through the opening. A second insulating film is formed on the first insulating film.

Abstract: In an electrode structure for a nitride III-V compound semiconductor device, a metallic nitride is used as an electrode material. A metallic material of the metallic nitride has a negative nitride formation free energy, and comprises at least one metal selected from a group consisting of IVa-group metals such as titanium and zirconium, Va-group metals such as vanadium, niobium, and tantalum, and VIa-group metals such as chromium, molybdenum, and tungsten.

Abstract: A transparent electrode film containing gold for covering the uppermost layer of a group III nitride semiconductor device has a first layer formed on the uppermost layer and not thicker than 15 Å, and a second layer formed on the first layer and containing gold. The first layer contains a first metal having an ionization potential lower than that of gold, and the second layer further contains a second metal having an ionization potential lower than that of gold.

Abstract: A light shield film is provided adjacent to an anode of an EL element that consists of the anode, an EL layer, and a cathode. The anode and the cathode are transparent or semitransparent to visible light and hence transmit EL light. With this structure, ambient light is absorbed by the light shield film and does not reach an observer. This prevents an external view from appearing on the observation surface.

Abstract: An undoped In0.52Al0.48As buffer layer (thickness: 500 nm), an undoped In0.53Ga0.47As channel layer (thickness: 30 nm), an n-type delta doped layer for shortening the distance between the channel layer and a gate electrode and attaining a desired carrier density, an undoped In0.52Al0.48As Schottky layer, and an n-type In0.53Ga0.47As cap layer doped with Si (thickness: 50 nm) are formed in this order on the principal surface of an Fe-doped InP semi-insulating substrate. An n-type GaAs protective layer doped with Si (thickness: 7.5 nm) is formed between the cap layer and source/drain electrodes for protecting the cap layer.

Abstract: A cross under metal wiring structure which may prevent “latch-up” from causing at a pnpn-structure is provided. The cross under metal wiring structure comprises a lower wiring provided on a topmost layer of the pnpn-structure isolated in an island by a groove, and an upper wiring connected to the lower wiring through a first contact hole opened in an insulating film covered the isolated pnpn-structure and to a layer just below the topmost layer through a second contact hole opened in the insulating film.

Abstract: The present invention discloses a substrate within a Ni/Au structure electroplated on electrical contact pads and a method for fabricating the same. The method comprises: providing a substrate with a circuit layout pattern and forming a conducting film on the surface of the substrate; depositing a first photoresist layer within an opening on said electrical conducting film surface to expose a portion of said circuit layout pattern to be electrical contact pads; removing the exposed conducting film uncovered by the first photoresist layer; depositing a second photoresist layer, covering the conducting film exposed in the openings of the first photoresist layer; electroplating Ni/Au covering the surface of the electrical contact pads; removing the first and second photoresists, and the conducting film covered by the photoresists; depositing solder mask on the substrate within an opening to expose said electrical contact pads.

Abstract: The invention relates to a method of manufacturing a double heterojunction bipolar transistor (1) comprising successively at least one sub-collector layer, a collector layer, a base layer and a metallic layer (10) deposited on the said base layer; the said metallic layer (10) being extended towards a contact pad (110) of the base by an underetched metallic “air bridge” (100), characterized in that producing the said “air bridge” (100) includes the following steps: effecting a first localized etching under the said bridge, this first etching being selective so as to etch the sub-collector layer laterally; and effecting a second localized etching under the said bridge, this second etching being selective so as to vertically etch at least the collector layer.

Abstract: According to the invention, there is provided a semiconductor light emitting device comprising: a contact layer formed of a nitride semiconductor; and a p-side electrode provided in contact with a surface of the contact layer, the contact layer having a superlattice including an alternative stacked structure of first nitride semiconductor layers having a wider bandgap and second nitride semiconductor layers having a narrower bandgap, the first semiconductor layers being selectively doped with a p-type dopant.

Abstract: An undoped In0.52Al0.48As buffer layer (thickness: 500 nm), an undoped In0.53Ga0.47As channel layer (thickness: 30 nm), an n-type delta doped layer for shortening the distance between the channel layer and a gate electrode and attaining a desired carrier density, an undoped In0.52Al0.48As Schottky layer, and an n-type In0.53Ga0.47As cap layer doped with Si (thickness: 50 nm) are formed in this order on the principal surface of an Fe-doped InP semi-insulating substrate. An n-type GaAs protective layer doped with Si (thickness: 7.5 nm) is formed between the cap layer and source/drain electrodes for protecting the cap layer.

Abstract: A GaAs substrate is reduced to a thickness of no more than 30 &mgr;m, preferably no more than 10 &mgr;m, by grinding. The substrate thus has the characteristics of a film, which prevents breakage of the substrate. A metallization can be provided on the rear of the substrate. The thermal characteristics are improved, because the heat can be transferred to the rear side of the substrate more effectively. Because of the smaller dimensions and good heat dissipation, smaller housings can be utilized. Extremely small holes (micro via holes) are etched into the substrate and provided with via hole fillers.

Abstract: A semiconductor triode comprises a gate electrode provided on a channel layer, wherein there is interposed an insulating metal oxide layer between a top surface of the channel layer and the gate electrode.

Abstract: A nitride semiconductor device having high electrode contact properties is disclosed. The nitride semiconductor device includes a semiconductor layer made of a group III nitride semiconductor, and a metal electrode for supplying the semiconductor layer with a carrier. The device has a first contact layer made of a group III nitride semiconductor (AlxGa1−x)1−yInyN (0≦x≦1, 0<y≦1), laminated between the semiconductor layer and the metal electrode, and a group II element added thereto, and a second contact layer made of a group III nitride semiconductor Alx′Ga1−x′N (0≦x′≦1) and laminated between the first contact and the metal electrode.

Abstract: An electronic semiconductor device comprising a semiconductor base deposited on a semiconductor substrate by means of molecular beam epitaxy and source, drain and gate disposed on the base in a spaced relationghip to each other, the source and the drain comprising Pd/barrier/Au layers with the palladium layer being in contact with the device. The device is fabricated conventionally except the heat treating is at above about 170° C. for ¼-10 hours sufficient for the palladium layer to react with the base yielding reduced contact and access resistances and a narrower spacing between source and drain.

Abstract: For forming a contact electrode to an n-type contact layer of a gallium nitride-based compound semiconductor, the n-type contact layer of the gallium nitride-based compound semiconductor is exposed to an oxygen plasma to form an oxygen-doped surface layer in a surface of the n-type contact layer, and then, an electrode metal is formed on the oxygen-doped surface layer. With this arrangement, an n-type contact electrode having a low specific contact resistance is obtained with good reproducibility, with performing no annealing after formation of the electrode metal.

Abstract: Disclosed are an epitaxial structure for low ohmic contact resistance in p-type GaN-based semiconductors and a method for growing such a structure. A very high density of p-type doped GaAs or p-type graded AlxGa1−xAs (0<x≦1) is formed between an ohmic metal and a p-type GaN and subjected to crystal growth. The doped p-type GaAs or graded p-type AlxGa1−xAs reduces the potential barrier formed in the p-type GaN, thus significantly reducing the ohmic resistance. This structure can be applied for the improvement in the power efficiency and function of GaN-based optical devices and ultra-speed electronic devices.

Abstract: An electrode for a light-emitting semiconductor device includes a light-permeable electrode formed to come into contact with the surface of the semiconductor, and a wire-bonding electrode that is in electrical contact with the light-permeable electrode and is formed to come into partial contact with the surface of the semiconductor with at least a region in contact with the semiconductor having a higher contact resistance per unit area with respect to the semiconductor than a region of the light-permeable electrode in contact with the semiconductor.

Abstract: The invention provides an electrode material having the low contact resistance against a III-V group compound semiconductor, thereby realizing a light emitting device having a high luminance and driven at low voltages. The electrode material of the invention is applied to a III-V group compound semiconductor, which is expressed as a general formula of InxGayAlzN, where x+y+z=1, 0≦x≦1, 0≦y≦1, and 0≦z≦1, and doped with p-type impurities. The electrode material comprises an alloy of Au and at least one metal selected from the group consisting of Mg and Zn.

Abstract: An ohmic electrode consists of a plurality of metal layers stacked on a p-type group III-V semiconductor crystal base material, in which a layer consisting of a group VB metal is stacked as a first layer as viewed from the side of the base material and a second layer containing Zn, for example, a third layer consisting of a refractory metal and a fourth layer consisting of Au are successively stacked on the first layer. Thus, a thin reaction layer can be formed by performing heating at a low temperature of not more than 400° C. simultaneously with formation of a p-type semiconductor electrode, for obtaining a metal electrode structure of a p-type group III-V semiconductor having an excellent ohmic characteristic.

Abstract: A GaN-based LED element 1 having a double heterostructure, which includes a GaN layer and the like and is formed on a sapphire substrate, is mounted face-down on a Si diode element 2 formed in a silicon substrate. Electrical connections are provided via Au microbumps 11 and 12 between a p-side electrode 5 of the GaN-based LED element 1 and an n-side electrode 8 of the Si diode element 2 and between an n-side electrode 6 of the GaN-based LED element 1 and a p-side electrode 7 of the Si diode element 2. The Si diode element 2 functions to protect the LED element 1 from an electrostatic destruction. The Si diode element 2 has a backside electrode 9 connected to a leadframe 13a. The p-side electrode 7 of the Si diode element 2 has a bonding pad portion 10 connected to a leadframe 13b via an Au wire 17.

Abstract: An electrode structure of compound semiconductor device. The compound semiconductor device has a substrate, an n-type layer over entire substrate, a mesa-like p-type layer on partial surface of the n-type layer, a transparent conductive layer on the mesa-like p-type layer; a p-contact formed on the transparent conductive layer and an n-contact formed on the exposed n-type layer. The n-contact comprises an enclosure portion compassing the p-contact, whereby the current flowed from the p-contact to the n-contact is uniform.

Abstract: For forming a contact electrode to an n-type layer of a gallium nitride-based compound semiconductor, the n-type contact layer of the gallium nitride-based compound semiconductor is exposed to an oxygen plasma to form an oxygen-doped surface layer in a surface of the n-type contact layer, and then, an electrode metal is formed on the oxygen-doped surface layer. With this arrangement, an n-type contact electrode having a low specific contact resistance is obtained with good reproducibility, with performing no annealing after formation of the electrode metal.

Abstract: For forming a contact electrode to an n-type contact layer of a gallium nitride-based compound semiconductor, the n-type contact layer of the gallium nitride-based compound semiconductor is exposed to an oxygen plasma to form an oxygen-doped surface layer in a surface of the n-type contact layer, and then, an electrode metal is formed on the oxygen-doped surface layer. With this arrangement, an n-type contact electrode having a low specific contact resistance is obtained with good reproducibility, with performing no annealing after formation of the electrode metal.

Abstract: An electrode for a light-emitting semiconductor device includes a light-permeable electrode formed to come into contact with the surface of the semiconductor, and a wire-bonding electrode that is in electrical contact with the light-permeable electrode and is formed to come into partial contact with the surface of the semiconductor with at least a region in contact with the semiconductor having a higher contact resistance per unit area with respect to the semiconductor than a region of the light-permeable electrode in contact with the semiconductor.

Abstract: To realize an ohmic electrode having practically satisfactory characteristics relative to GaAs semiconductors, first formed on an n+-type GaAs substrate are a Ni thin film with a thickness between 8 nm and 30 nm, an In thin film with a thickness between 2 nm and 6 nm and a Ge thin film with a thickness between 10 nm and 50 nm, sequentially. After that, the n+-type GaAs substrate having formed the Ni thin film, In thin film and Ge thin film is annealed at a temperature between 300 to 600° C. for a few seconds to minutes. As a result, the ohmic electrode has a multi-layered structure including an n++-type re-grown GaAs layer re-grown from the n+-type GaAs substrate, InGaAs layer and NiGe thin film. Alternatively, before the annealing, a thin film of a refractory metal or its compound, such as Nb thin film, with or without another thin film of a wiring metal, such as Au thin film, may be further formed on the Ge thin film.

Abstract: When a device using GaN semiconductors is made on a hard and chemically stable single-crystal substrate such as sapphire substrate or SiC substrate, a semiconductor device and its manufacturing method ensure high-power output or high-frequency operation of the device by thinning the substrate or making a via hole in the substrate. When a light emitting device using GaN semiconductors is made on a non-conductive single-crystal substrate such as sapphire substrate, the semiconductor device and its manufacturing method reduce the operation voltage of the light emitting device by making a via hole to the substrate. More specifically, after making a GaN FET by growing GaN semiconductor layers on the surface of a sapphire substrate, the bottom surface of the sapphire substrate is processed by lapping, using an abrasive liquid containing a diamond granular abrasive material and reducing the grain size of the abrasive material in some steps, to reduce the thickness of the sapphire substrate to 100 &mgr;m or less.

Abstract: An electrode of a metal, which is one of Group IV and VI elements, is deposited on an n-type InxAlyGa1−x−yN layer. Alternatively, after an electrode material of carbon, germanium), selenium, rhodium, tellurium, iridium, zirconium, hafnium, copper, titanium nitride, tungsten nitride, molybdenum or titanium silicide, is deposited on an n-type InxAlyGa1−x−yN layer or a p-type InxAlyGa1−x−yN layer, an impurity for increasing the carrier concentration of the semiconductor layer is ion-implanted, and the annealing is carried out. Thus, it is possible to provide a light emitting semiconductor device, which has a low contact resistance and a sufficient bond strength to the InxAlyGa1−x−yN layer while maintaining the crystallinity of the InxAlyGa1−x−yN layer.

Abstract: An electrode for a light-emitting semiconductor device includes a light-permeable electrode formed to come into contact with the surface of the semiconductor, and a wire-bonding electrode that is in electrical contact with the light-permeable electrode and is formed to come into partial contact with the surface of the semiconductor with at least a region in contact with the semiconductor having a higher contact resistance per unit area with respect to the semiconductor than a region of the light-permeable electrode in contact with the semiconductor.

Abstract: A light-emitting semiconductor device such as a laser or LED includes a light-emitting region interposed between two GaN contact layers of different conductivity types. A metal electrical contact is provided directly on one of the contact layers and is formed of an annealed, at least partly alloyed metal layer including hafnium and gold. The metal layer may also include platinum, or platinum and titanium. Light-emitting semiconductor devices such as light-emitting diodes and lasers having such annealed, at least partly alloyed metal layer are particularly suitable for high current-density applications which result in higher operating temperatures, such they are capable of operating at higher temperatures without shorting.

Abstract: A p-contact that comprises a contact layer of a p-type Group III-nitride semiconductor having an exposed surface and an electrode layer of palladium (Pd) located on the exposed surface of the contact layer. The p-contact is made by providing a p-type Group III-nitride semiconductor contact layer having an exposed surface, and depositing an electrode layer of palladium on the exposed surface of the contact layer. Preferably, the p-contact is annealed for a prolonged annealing time after the electrode layer is deposited, and the exposed surface of the contact layer is etched using hydrofluoric acid (HF) before depositing the electrode layer.