Abstract: An integrated circuit chip (10) includes a substrate (12), a plurality of transistors (16) provided in the substrate (12), a circuit pattern (14) provided on a top surface of the substrate (12) and a metal layer (42) comprising at least two metals in substantially eutectic proportions provided on a bottom surface of the substrate, the bottom surface of the metal layer (42) being exposed. The integrated circuit chip (10) can be attached to a farther substrate, e.g., a housing, using automated attachment techniques. The chip (10) can be attached to the housing by picking up the integrated circuit chip (10) with the metal layer (42) provided on the bottom surface thereof and placing the integrated circuit chip (10) onto a housing so the bottom surface of the integrated circuit chip (10) faces the housing with the metal layer (42) there between; and then heating the metal layer (42) to a temperature above its eutectic temperature to melt the metal layer and attach the integrated circuit chip (10) to the housing.

Abstract: The electrode structure of the invention includes a p-type AlxGayIn1−x−yN (0≦x≦1, 0≦y≦1, x+y≦1) semiconductor layer and an electrode layer formed on the semiconductor layer. In the electrode structure, the electrode layer contains a mixture of a metal nitride and a metal hydride.

Abstract: A stable, reliable ohmic contact, and improved semiconductor articles and opto-electronic circuits incorporating same, are disclosed. According to an illustrative embodiment of the invention, an ohmic contact having a plurality of thermodynamically-stable layers and layer interfaces is formed by providing a structure comprising multiple, appropriately-thick and specifically-organized layers of suitably-selected material, and exposing the structure to heat to cause reaction to take place between the various layers. Due to the thermodynamic stability of the resulting reacted layers and the interfaces between such layers, there is substantially no tendency for further reaction to occur within the ohmic contact.

Abstract: As will be described in more detail hereinafter, there is disclosed herein a titanium nitride diffusion barrier layer and associated method for use in non-silicon semiconductor technologies. In one aspect of the invention, a semiconductor device includes a non-silicon active surface. The improvement comprises an ohmic contact serving to form an external electrical connection to the non-silicon active surface in which the ohmic contact includes at least one layer consisting essentially of titanium nitride. In another aspect of the invention, a semiconductor ridge waveguide laser is disclosed which includes a semiconductor substrate and an active layer disposed on the substrate. A cladding layer is supported partially on the substrate and partially on the active layer. The cladding layer includes a ridge portion disposed in a confronting relationship with the active region.

Abstract: A light emitting device constructed on a substrate. The device includes an n-type semiconductor layer in contact with the substrate, an active layer for generating light, the active layer being in electrical contact with the n-type semiconductor layer. A p-type semiconductor layer is in electrical contact with the active layer, and a p-electrode is in electrical contact with the p-type semiconductor layer. The p-electrode includes a layer of silver in contact with the p-type semiconductor layer. In the preferred embodiment of the present invention, the n-type semiconductor layer and the p-type semiconductor layer are constructed from group III nitride semiconductor materials. In one embodiment of the invention, the silver layer is sufficiently thin to be transparent. In other embodiments, the silver layer is thick enough to reflect most of the light incident thereon. A fixation layer is preferably provided over the silver layer.

Abstract: A surface light-emitting element having improved external light emission efficiency and a self-scanning light-emitting device using this surface light-emitting element are provided. To improve external light-emission efficiency, the light-emitting center is shifted to an area where there is no light shielding layer thereon. To achieve this, an insulating layer is provided on the electrode portion above which there is a light-shielding layer at a portion making contact with the semiconductor layer thereunder so as to prevent the injected current from flowing from that electrode portion. To increase the amount of light emission, the peripheral length of the electrode is increased. With an electrode of the same area, the larger the peripheral length, the larger becomes the amount of light emission because the current injected from the electrode is distributed evenly over the entire surface, causing light to emit evenly.

Abstract: An ohmic contact including a gallium arsenide substrate having an epitaxially grown crystalline layer of indium arsenide on the substrate. The crystalline material and the substrate define an interface, layers are n-doped with silicon close to the interface.

Abstract: A metal thin film with an ohmic contact for light emit diodes and a method of producing such a film are disclosed. The metal thin film has a p-type gallium nitride (GaN) semiconductor layer. Nickel (Ni), platinum (Pt) and gold (Au) layers are deposited on the GaN semiconductor layer in a way such that the gold layer forms a top layer, with either one of the platinum and nickel layers being selectively used as an inter-diffusion barrier between metal layers. The inter-diffusion barrier may be formed by depositing platinum between the nickel and gold layers, thus forming an Ni/Pt/Au metal thin film, or formed by depositing nickel between the platinum and gold layers, thus forming an Pt/Ni/Au metal thin film. In the method, a GaN semiconductor is washed so as to be free from carbide and oxide layers. The Ni, Pt and Au layers are formed on the GaN semiconductor layer through a vacuum deposition process at 5×10−5-2×10−1 torr.

Abstract: An electrode for a Group III nitride compound semiconductor having p-type conduction that has a double layer structure. The first metal electrode layer comprising, for example, nickel (Ni) and the second metal electrode layer comprising, for example, gold (Au). The Ni layer is formed on the Group III nitride compound semiconductor having p-type conduction, and the Au layer is formed on the Ni layer. Heat treatment changes or reverses the distribution of the elements Ni and Au. Namely, Au is distributed deeper into the Group III nitride compound semiconductor than is Ni. As a result, the resistivity of the electrode is lowered and its ohmic characteristics are improved as well as its adhesive strength.

Abstract: Disclosed is an electrode material for Group III-V compound semiconductor represented by the general formula In.sub.x Ga.sub.y Al.sub.z N (provided that x+y+z=1, 0.ltoreq.x.ltoreq.1, 0.ltoreq.y.ltoreq.1, and 0.ltoreq.z.ltoreq.1) doped with a p-type impurity which is capable of obtaining good ohmic contact, and an electrode using the same, thereby making it possible to reduce a driving voltage of a device using the compound semiconductor. The electrode material is a metal comprising at least Ca and a noble metal, wherein the total amount of the weight of Ca and the noble metal is not less than 50% by weight and not more than 100% by weight based on the weight of the whole electrode material.

Abstract: An electrical contact that comprises a layer of a p-type gallium nitride material, a metal layer, and an intermediate layer of a material different from the gallium nitride material and the metal layer. The intermediate layer is sandwiched between the layer of p-type gallium nitride material and the metal layer. The material of the intermediate layer may be a Group III-V semiconductor that has high band-gap energy, lower than that of the p-type gallium nitride material. The intermediate layer may alternatively include layers of different Group III-V semiconductors. The layers of the different Group III-V semiconductors are arranged in order of their band-gap energies, with the Group III-V semiconductor having the highest band-gap energy next to the layer of the p-type gallium nitride material, and the Group III-V semiconductor having the lowest band-gap energy next to the metal layer. As a further alternative, the material of the intermediate layer may be a metal nitride.

Abstract: A GaN group compound semiconductor device includes an electrode structure provided on a p-GaN group compound semiconductor layer, the electrode structure including: a first layer formed on the p-GaN group compound semiconductor layer, the first layer including a compound including a first metal element and Ga; and a second layer formed on the first layer, the second layer including the first metal element. The first layer contains substantially no nitrogen.

Abstract: A semiconductor light emission device includes at least an n-type semiconductor clad layer, a semiconductor active layer and a p-type semiconductor clad layer formed on a substrate in this order. A stripe portion which determines a light emission region is formed on a part of the p-type clad layer and a p-type capping layer is formed on the stripe portion. A p-side electrode is formed on the p-type capping layer. The p-type capping layer includes a lower capping layer in the form of a stripe overlaid on the stripe portion and an upper capping layer which is formed on the lower capping layer and has an area larger than that of the lower capping layer. The contact area between the p-side electrode and the upper capping layer of the p-type capping layer is larger than that between the upper capping layer and the lower capping layer of the p-type capping layer.

Abstract: A thin oxide region is introduced to a surface of a GaN layer prior to contact meal evaporation by carefully controlling the oxidation of the surface. This results in the normally present surface states to be smothered and thus a low band offset is observed in an ohmic contact comprising the contact metal and the GaN layer. The thickness of the oxide region preferably is about 8 .ANG. to 25 .ANG.. Other elements such as S, Se, Te, As, P and Hf can be used as an alternative to O. Devices using the thin region in the ohmic contact may include semiconductor laser devices, light emitting diodes, and III-V based transistors.

Abstract: By using fusion of a heat spreader layer, a large bandwidth, high power semiconductor laser can be fabricated. The use of multiple metals with low thermal resistance allows for higher power because heat flow is conducted away from the active region easily. The extraction of heat from the active region makes the resultant laser more stable with the capability for higher power outputs.

Abstract: An electrode for a Group III nitride compound semiconductor having p-type conduction that has a double layer structure. The first metal electrode layer comprising, for example, nickel (Ni) and the second metal electrode layer comprising, for example, gold (Au). The Ni layer is formed on the Group III nitride compound semiconductor having p-type conduction, and the Au layer is formed on the Ni layer. Heat treatment changes or reverses the distribution of the elements Ni and Au. Namely, Au is distributed deeper into the Group III nitride compound semiconductor than is Ni. As a result, the resistivity of the electrode is lowered and its ohmic characteristics are improved as well as its adhesive strength.

Abstract: An electronic part comprising an amorphous thin film formed on a substrate; and a metal wiring formed on the surface of the amorphous thin film; wherein an interatomic distance corresponding to a peak of halo pattern appearing in diffraction measurement of the amorphous thin film approximately matches with a spacing of a particular crystal plane defined with the first nearest interatomic distance of the metal wiring. An electronic part provided with a metal wiring formed of highly orientated crystal wherein half or more of all grain boundaries are small angle grain boundaries defined by one of grain boundaries with a relative misorientation of 10.degree. or less in tilt, rotation and combination thereof around orientation axes of neighboring crystal grains; coincidence boundaries where a .SIGMA. value is 10 or less; and grain boundaries with a relative misorientation of 3.degree. or less from the coincidence boundary.

Abstract: The present invention relates to a novel planar technology approach utilizing ion implantation to improve the fabrication procedure for manufacturing nitride light-emitting and laser diodes. The simplified processing significantly reduces the costs of manufacturing these devices and allows flip-chip bonding to be used for efficient heat removal, yielding much brighter LEDs and more powerful lasers.

Abstract: A nitride compound semiconductor light emitting element is made by stacking a metal layer made of one of elements: palladium (Pd), scandium (Sc), vanadium (V), zirconium (Zr), hafnium (Hf), tantalum (Ta), rhodium (Rh), iridium (Ir), cobalt (Co) and copper (Cu), and another metal layer made of one of elements: titanium (Ti), nickel (Ni), molybdenum (Mo), tungsten (W) and magnesium (Mg), to increase the adhesive strength of its electrodes with a semiconductor layer, reduce the contact resistance of the electrodes to improve the ohmic characteristics, and improve the external quantum efficiency by combination of thin-film metals with a transparent electrode.

Abstract: A light emitting diode (LED) and a method for fabricating the same are disclosed, the LED including the steps of successively forming a first epitaxial layer, an active layer, and a second epitaxial layer on a substrate; patterning the active layer and the second epitaxial layer to expose a predetermined area of the first epitaxial layer; increasing an amount of N on a predetermined area of the exposed first epitaxial layer to form a TiN layer and either an Au or Al layer on the TiN layer, so as to form a first electrtode of a bilayer structure; and forming a second electrode on a predetermined area of the second epitaxial layer.

Abstract: A semiconductor device having an ohmic electrode having a satisfactory ohmic contact to an n-type GaAs can be obtained by heat treatment at low temperature. A method of manufacturing the semiconductor device having the ohmic electrode includes two processes. In the first process, a metal layer containing Ni, Sn and AuGe is formed on one main surface of the n-type GaAs. In the second process, the n-type GaAs is subjected to a heat treatment at a temperature which is equal to or higher than 190.degree. C. and equal to or lower than 300.degree. C. Thus, the ohmic electrode is formed on the one main surface of the n-type GaAs.

Abstract: The bipolar transistor includes an emitter layer at least a part of which is composed of AlGaAs, a collector layer at least a part of which is composed of GaAs, a base contact layer disposed in at least a part of an area between a base electrode and a base layer, and a base layer at least a part of which is composed of an InGaAs graded layer in which the concentration of In gradually increases from an emitter-base junction towards a base-collector junction.

Abstract: A p-type electrode structure having low resistance and a high yield light emitting element operable at low operating voltage is disclosed. On a substrate is formed an n-type clad layer, an active layer, a p-type semiconductor layer, a current structure layer, an n-type semiconductor layer and a metal layer. The energy level of a conduction band edge of the n-type semiconductor layer is deeper than that of a valence band edge of the p-type semiconductor layer, and the Fermi level of the metal layer is shallower than the energy level of a conduction band edge of the n-type semiconductor layer.

Abstract: Generally, and in one form of the invention, a method is disclosed for forming an ohmic contact on a GaAs surface 20 comprising the steps of depositing a layer of InGaAs 22 over the GaAs surface 20, and depositing a layer of TiW 24 on the layer of InGaAs 22, whereby a reliable and stable electrical contact is established to the GaAs surface 20 and whereby Ti does not generally react with the In.

Abstract: A low temperature annealed Cu silicide or germanide layer on the surface of a single crystalline semiconductor substrate of Si or Ge is used in interconnection metallization for integrated circuits. The Cu silicide or germanide layer is preferably formed by heating Cu deposited on a Si or Ge substrate up to about 200.degree. C. for about 30 minutes. The layer demonstrates superior (near ideal) current/voltage characteristics and can be used as a high temperature (600-800.degree. C.) stable Ohmic/Schottky contact to Si or as a Cu diffusion barrier. Additional embodiments involve a Cu layer on a Ge layer on Si substrate, a Cu layer on a Si.sub.x Ge.sub.1-x layer on a substrate, and the use of an intermediate layer of a refractory metal such as W.

Abstract: An ohmic contact electrode for a semiconductor device which has a low contact resistance and high stability. The ohmic contact electrode includes: a semiconductor substrate; an atomic doping layer developed on the semiconductor substrate wherein the atomic doping layer is formed by doping impurities such that an energy level of the layer is higher than a Fermi level; a semiconductor layer developed on the atomic doping layer wherein the semiconductor layer is formed of the same material as in the semiconductor substrate; a metal electrode formed on the semiconductor layer for establishing an electric connection with the semiconductor substrate; wherein the semiconductor layer has a thickness sufficient for carriers to transfer between the metal electrode and the atomic doping layer by tunneling through the semiconductor layer.

Abstract: A semiconductor device having a spiral electrode pattern and fabrication method thereof. The device includes an undoped semiconductor substrate, a first and a second probing pads formed on the substrate, and a pair of electrode fingers extending spirally toward a concentric center from the respective first and second probing pads and interdigitated with each other. The method includes the steps of, patterning an insulation layer on a semiconductor substrate in a spiral structure, depositing a metal layer on the substrate including the insulation layer but excluding the sides of the insulation layer, and etching the insulation layer using a wet etching technique.

Abstract: A method for fabricating a semiconductor device includes: successively laminating a pair or more pairs of Ti and Al thin films on an n type GaAs substrate thereby to form Ti/Al laminated films; and performing thermal processing to the n type GaAs substrate and the Ti/Al laminated films at a temperature lower than the temperature at which Al of the Ti/Al laminated films and GaAs of the n type GaAs layer react with each other, to make the Ti/Al laminated films have ohmic junction with the n type GaAs layer thereby to form an ohmic electrode. Therefore, the Ti/Al laminated layer film comprising materials which are not likely to intrude into the n type GaAs layer is alloyed to Al.sub.3 Ti alloy by the annealing, and during the annealing, Ga atoms are out-migrated from the n type GaAs layer, and the Si atoms as dopants in the n type GaAs layer are present in the junction interface of the n type GaAs layer with the Ti/Al laminated layer film, thereby to form an ohmic contact.

Abstract: An ohmic electrode for III-V compound semiconductors such as GaAs semiconductors is provided to have satisfactory practical characteristics. Provided on an n.sup.+ -type GaAs substrate is an ohmic electrode in which an n.sup.++ -type regrown GaAs layer regrown from the n.sup.+ -type GaAs substrate and a NiGe film containing particles of a precipitate composed of .alpha.'-AuGa are sequentially stacked. The ohmic electrode may be fabricated by sequentially stacking a Ni film, Au film and Ge film on the n.sup.+ -type GaAs substrate, then patterning these films by, for example, lift-off, and thereafter annealing the structure at a temperature of 400.about.750.degree. C. for several seconds to several minutes.

Abstract: Structure and fabrication details are disclosed for AlGaAs/GaAs microwave HBTs having improved thermal stability during high power operation. The use of a thermal shunt joining emitter contacts of a multi-emitter HBT is shown to improve this thermal stability and eliminate "current-crush" effects. A significant reduction in thermal resistance of the disclosed devices is also achieved by spreading the generated heat over a large substrate area using thermal lens techniques in the thermal shunt. These improvements achieve thermally stable operation of AlGaAs/GaAs HBTs up to their electronic limitations. A power density of 10 mW/.mu.m2 of emitter area is achieved with 0.6 W CW output power and 60% power-added efficiency at 10 GHz. The thermal stabilization technique is applicable to other bipolar transistors including silicon, germanium, and indium phosphide devices.

Abstract: The invention provides an electrode material having the low contact resistance against a III-V group compound semiconductor, thereby realizing a light emitting device having a high luminance and driven at low voltages. The electrode material of the invention is applied to a III-V group compound semiconductor, which is expressed as a general formula of In.sub.x Ga.sub.y Al.sub.z N, where x+y+z=1, 0.ltoreq.x.ltoreq.1, 0.ltoreq.y.ltoreq.1, and 0.ltoreq.z.ltoreq.1, and doped with p-type impurities. The electrode material comprises an alloy of Au and at least one metal selected from the group consisting of Mg and Zn.

Abstract: A semiconductor photodetection device includes a semiconductor layer of a first conductivity type in which a pair of conductive regions of a second conductivity type are formed, the first conductive region acting as a photodiode and having an area substantially smaller than the area of the second conductive region, wherein the second conductive region carries a second metal bump of which area is at least ten times as large as a first metal bump that is provided on the first conductive region.

Abstract: A gallium nitride-based III-V Group compound semiconductor device has a gallium nitride-based III-V Group compound semiconductor layer provided over a substrate, and an ohmic electrode provided in contact with the semiconductor layer. The ohmic electrode is formed of a metallic material, and has been annealed.

Abstract: A semiconductor device includes a semiconductor substrate having a surface; an active layer of a compound semiconductor disposed at the surface of the semiconductor substrate; and a Schottky barrier gate electrode including a multi-layer film alternately laminating a conductive refractory metal compound layer including a first refractory metal (M.sub.1) and a second refractory metal (M.sub.2) layer to three or more layers respectively, disposed on the active layer, thereby forming a Schottky junction with the active layer. The gate resistance of the Schottky barrier gate electrode can be held low and the internal stress can be reduced, whereby peeling off of the can be suppressed.

Abstract: A light emitting diode includes a doped semiconductor substrate wafer with a layer sequence suitable for light emission in the green spectral range epitaxially applied thereon. A zinc-doped contact is applied to the p-conductive side of the wafer for efficient generation of pure green light emissions. An electrically conductive layer is provided between the zinc-doped contact and the p-conductive wafer side to suppress diffusion of oxygen into the p-conductive wafer side during diode manufacture.

Abstract: A gallium nitride-based III-V Group compound semiconductor device has a gallium nitride-based III-V Group compound semiconductor layer provided over a substrate, and an ohmic electrode provided in contact with the semiconductor layer. The ohmic electrode is formed of a metallic material, and has been annealed.

Abstract: An ohmic electrode for a p-type III-V compound semiconductor is disclosed. The ohmic electrode formed on a p-type III-V compound semiconductor layer includes nickel (Ni), titanium (Ti), and platinum (Pt) as main components in an interface between the ohmic electrode and the p-type III-V compound semiconductor layer.

Abstract: A ceramic element is formed by a rare earth and transition element oxide such as LaCoO.sub.3. The ceramic element is substantially isolated from the atmosphere by a case base, a case, etc.

Abstract: A buffer layer 2 composed of undoped GaAs or undoped AlGaAs, an n-type AlGaAs electron supply layer 3, an undoped InGaAs channel layer 4, an AlGaAs electron supply layer 5 composed of n-type AlGaAs or undoped AlGaAs, an n-type InGaP contact lower layer 16, and an n-type GaAs contact upper layer 7 are formed on a semiinsulating GaAs substrate 1. A gate electrode is formed on the AlGaAs electron supply layer 5. A drain electrode and a source electrode are formed on the GaAs contact upper layer 7. Thus, in the FET with double-recess structure, the drain current can be increased and the gate breakdown voltage can be improved.

Abstract: An electrically isolated MESFET includes a compound semiconductor substrate; a plurality of compound semiconductor layers disposed on the compound semiconductor substrate; a MESFET structure in a prescribed region of the compound semiconductor layers; an electrically isolating region in the compound semiconductor layers surrounding and electrically isolating the MESFET structure from the compound semiconductor layers outside the electrically isolating region, wherein the compound semiconductor layer most remote from the compound semiconductor substrate has the highest conductivity of the compound semiconductor layers; a recess penetrating the compound semiconductor layer most remote from the compound semiconductor substrate and at least the compound semiconductor layer adjacent the compound semiconductor layer most remote from the compound semiconductor substrate, the recess dividing the compound semiconductor layer most remote from the compound semiconductor substrate into mutually separated first and second

Abstract: A lower electrode, a first inorganic insulating film of SiN, and an organic insulating film of polyimide are formed on a GaAs substrate serving as an underlie, in this order. The organic insulating film is selectively etched to form a capacitor opening. A second norganic insulating film covering the surface of the organic insulating film and the bottom and side wall of the capacitor opening, and an upper electrode are formed. As the selective etching of the organic insulating film, wet etching may be used for simplifying manufacturing processes. Alternatively, dry etching may be used for improving etching accuracy. The organic insulating film 4 may be formed by a multi-layer film so that a circuit can be formed across multi-layers, improving the degree of integration.

Abstract: A method of fabricating heterojunction bipolar transistors (HBTs) including epitaxial growth of collector, base and emitter layers, allowing for self-aligned emitter-base contacts to minimize series base resistance and to reduce total base-collector capacitance.

Abstract: A field effect transistor (20) comprises a first semiconductor layer (24) and a second semiconductor layer (25) formed on the first semiconductor layer. The first semiconductor layer is an undoped layer and is composed of InGaAs. The second semiconductor layer is composed of InAlGaP and is a doped layer in which an n-type impurity is doped. A heterojunction structure is formed between the first semiconductor layer and the second semiconductor layer.

Abstract: An ohmic contact to a III-V semiconductor material is fabricated. First, a III-V semiconductor material is provided. Source/drain regions are then formed in the III-V semiconductor material. On the III-V semiconductor material, a contact system is formed which is dry etchable using reactive ions such as chlorine or fluorine and substantially free of arsenic. Subsequently, a portion of the contact system is dry etched using reactive ions such as chlorine or fluorine to leave a portion of the contact system remaining on the source/drain regions. Then, the III-V semiconductor material and the contact system are annealed in an atmosphere substantially free of arsenic at a temperature at which at least a part of the contact system is alloyed with the source/drain regions to form an ohmic contact with the source/drain regions of the III-V semiconductor material.

Abstract: An ohmic electrode is formed on a cBN crystal to form a cBN semiconductor device which is used as a solid electronic element. The cBN semiconductor device may be of an n-type, a p-type or a pn junction type wherein molybdenum is deposited onto an n-type doped region of the cBN crystal or platinum is deposited onto a p-type doped region to thereby form an electrode with ohmic characteristic. The deposition of the molybdenum or the platinum is conducted by using a vapor deposition method followed by heating the attached substance at a temperature of 300.degree. C.-1100.degree. C. in an inactive gas atmosphere. The cBN semiconductor device can be used as a solid electronic element or an optoelectronic element for rectifiers, transistors, light emitting diodes and so on and integrated elements thereof.

Abstract: An n.sup.- -type InP buffer layer is formed on an n-type InP substrate. An n.sup.- -type InGaAs light absorbing layer is formed on the n.sup.- -type InP buffer layer. An n.sup.- -type InP cap layer is formed on the n.sup.- -type InGaAs light absorbing layer. A p-type InP region is formed in the InP cap layer. A layered electrode having a contact with the p-type InP region comprises a first layer made of an Au layer, a second layer made of a Ti layer or the like, a third layer made of a Pt layer or the like, and a fourth layer made of an Au layer. The first layer made of Au has a thickness of 1 to 500 nm. This structure improves an ohmic ability and a peel strength at a contact portion where an electrode is connected, and simplifies manufacturing steps.

Abstract: A light-emitting diode of GaN compound semiconductor emits a blue light from a plane rather than dots for improved luminous intensity. This diode includes a first electrode associated with a high-carrier density n.sup.+ layer and a second electrode associated with a high-impurity density i.sub.H -layer. These electrodes are made up of a first Ni layer (110 .ANG. thick), a second Ni layer (1000 .ANG. thick), an Al layer (1500 .ANG. thick), a Ti layer (1000 .ANG. thick), and a third Ni layer (2500 .ANG. thick). The Ni layers of dual structure permit a buffer layer to be formed between them. This buffer layer prevents the Ni layer from peeling. The direct contact of the Ni layer with GaN lowers a drive voltage for light emission and increases luminous intensity.

Abstract: A gallium arsenide monolithic microwave integrated circuit (MMIC) chip (12) has microelectronic devices (16, 18) formed on a frontside surface (12a), and via holes (12c, 12d) formed through the chip (12) from the frontside surface (12a) to a backside surface (12b). The backside surface (12b) of the chip (12) is bonded to a molybdenum carrier (14) by an eutectic gold/tin alloy (20). A barrier layer (22) including a refractory metal nitride material (22a) is sputtered onto the backside surface (12b) and into the via holes (12c, 12d) of the chip (12) prior to bonding. The barrier layer (22) blocks migration of tin from the eutectic gold-tin alloy (20) through the via holes (12c,-12d) to the frontside surface (12a) of the chip (12) during the bonding operation, thereby preventing migrated tin from adversely affecting the microelectronic devices (16, 18).

Abstract: An ohmic contact to a p-type zinc selenide (ZnSe) layer in a Group II-VI semiconductor device, includes a zinc telluride selenide (ZnTe.sub.x Se.sub.1-x) layer on the zinc selenide layer, a mercury selenide (HgSe) layer on the zinc telluride selenide layer and a conductor (such as metal) layer on the mercury selenide layer. The zinc telluride selenide and mercury selenide layers between the p-type zinc selenide and the conductor layer provide an ohmic contact by eliminating the band offset between the wide bandgap zinc selenide and the conductor. Step graded, linear graded, and parabolic graded layers of zinc telluride selenide may be provided. An integrated heterostructure is formed by epitaxially depositing the ohmic contact on the Group II-VI device. A removable overcoat layer may be formed on the Group II-VI device to allow room temperature atmospheric pressure transfer of the device from a zinc based deposition chamber to a mercury based deposition chamber, for deposition of the ohmic contact.

Abstract: A light-emitting diode of GaN compound semiconductor emits a blue light from a plane rather than dots for improved luminous intensity. This diode includes a first electrode associated with a high-carrier density n.sup.+ layer and a second electrode associated with a high-impurity density .[.i.sub.H -layer.]. .Iadd.H-layer.Iaddend.. These electrodes are made up of a first Ni layer (110 .ANG. thick), a second Ni layer (1000 .ANG. thick), an Al layer (1500 .ANG. thick), a Ti layer (1000 .ANG. thick), and a third Ni layer (2500 .ANG. thick). The Ni layers of dual structure permit a buffer layer to be formed between them. This buffer layer prevents the Ni layer from peeling. The direct contact of the Ni layer with GaN lowers a drive voltage for light emission and increases luminous intensity.