Contact For Iii-v Material Patents (Class 257/745)
  • Patent number: 5365533
    Abstract: The disclosure relates to integrated circuits of lasers, wherein the linear arrays are supplied in series, with a return of current through the substrate. When the substrate is semi-insulating, only the first epitaxially grown layer is conductive. To reduce its electrical resistance, a surface film of the substrate is made conductive by diffusion of a dopant. Application to power semiconductor lasers.
    Type: Grant
    Filed: November 9, 1992
    Date of Patent: November 15, 1994
    Assignee: Thomson Hybrides
    Inventor: Bernard Groussin
  • Patent number: 5355021
    Abstract: A low resistance contact for p-type GaAs is provided by Pd/Zn/Pd/Au structure 1. The contact is suitable for device substrates having carrier concentrations in the range of about 10.sup.18 to about 10.sup.20 cm.sup.-3. The ohmic contact has a Pd layer of depth 3 nm to 15 nm, a Zn layer with a depth of between 5 nm and 40 nm, a second Pd layer with a depth greater than about 50 nm and an Au layer with a depth greater than about 300 nm. A preferred construction (1) is 5 nm/10 nm/100 nm/400 nm of Pd/Zn/Pd/Au. The ohmic contact deposition must be followed by annealing, with preferred annealing carried out at a temperature of about 200.degree. C. Annealing times are dependent upon annealing temperature, with a typical minimum annealing times of greater than 5 minutes at annealing temperatures of about 200.degree. C.
    Type: Grant
    Filed: June 11, 1993
    Date of Patent: October 11, 1994
    Assignee: The Secretary of State for Defence in Her Britannic Majesty's Government of the United Kingdom of Great Britain and Northern Ireland
    Inventors: Mark A. Crouch, Suhkdev S. Gill, William H. Gilbey, Graham J. Pryce
  • Patent number: 5317190
    Abstract: This invention describes a low resistance contact structure to n-type GaAs and a method for making such a contact structure. The contact structure is formed by depositing successive layers of Ni, Au, Ge, and Ni. A fifth layer is then deposited on the first four layers. The fifth layer is a metallic tungsten oxide. The metallic tungsten oxide is formed by sputtering tungsten onto the 4 layer stack in a low pressure argon plus oxygen atmosphere. The resulting 5 layer stack is then annealed in a rapid thermal anneal (RTA) process. The RTA process heats the stack for 5 seconds at 600 degrees. The resulting structure consists of an intermetallic NiGe compound having a small amount of a AuGa compound dispersed within it and being covered by a metallic tungsten oxide film. The oxygen from the metallic tungsten oxide film acts as a gettering mechanism to create gallium vacancies in the GaAs lattice structure during the RTA process.
    Type: Grant
    Filed: October 25, 1991
    Date of Patent: May 31, 1994
    Assignee: International Business Machines Corporation
    Inventors: Aaron J. Fleischman, Naftali E. Lustig, Robert G. Schad
  • Patent number: 5309022
    Abstract: A low resistance ohmic contact for n-type GaAs and GaAlAs is provided by Ni-Ge-Au structure (1). The contact is suitable for device substrates (2) which have carrier concentrations of between about 10.sup.17 cm.sup.-3 and about 10.sup.19 cm.sup.-3. The ohmic contact has a nickel layer of between 40 .ANG. and 200 .ANG. deposited on the substrate, followed by a Ge deposition (4) of between 150 .ANG. and 400 .ANG. and finally an Au deposition (5, 6) of greater than 4000 .ANG.. The Au layer is preferably deposited in two separate layers of between 500 .ANG. and 1000 .ANG., (5), and greater than 4000 .ANG., (6). A preferred construction (1) is 50 .ANG./200 .ANG./800 .ANG.+5000 .ANG. (Ni/Ge/Au+Au). The ohmic contact deposition must be followed by annealing, typically at temperatures between 300.degree. C. and 500.degree. C. for times of between 1 second and 200 seconds. The preferred annealing conditions are a temperature of 400.degree. C. maintained for 15 seconds.
    Type: Grant
    Filed: February 14, 1992
    Date of Patent: May 3, 1994
    Assignee: The Secretary of State for Defence in Her Britannic Majesty's Government of the United Kingdom of Great Britain and Northern Ireland
    Inventors: Sukhdev S. Gill, Mark A. Crouch, John R. Dawsey
  • Patent number: 5294834
    Abstract: A method of enhancing the specific contact resistivity in InP semiconductor devices and improved devices produced thereby are disclosed. Low resistivity values are obtained by using gold ohmic contacts that contain small amounts of gallium or indium and by depositing a thin gold phosphide interlayer between the surface of the InP device and the ohmic contact. When both the thin interlayer and the gold-gallium or gold-indium contact metallizations are used, ultra low specific contact resistivities are achieved. Thermal stability with good contact resistivity is achieved by depositing a layer of refractory metal over the gold phosphide interlayer.
    Type: Grant
    Filed: June 1, 1992
    Date of Patent: March 15, 1994
    Assignee: Sverdrup Technology, Inc.
    Inventors: Navid S. Fatemi, Victor G. Weizer
  • Patent number: 5274268
    Abstract: An electric circuit is provided on a semiconductor substrate with a supercoducting film. The surfaces being in contact with the superconducting film are made of heat-resistant non-oxide insulating materials so that the performance of the superconducting film is not degraded.
    Type: Grant
    Filed: November 25, 1991
    Date of Patent: December 28, 1993
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Shumpei Yamazaki
  • Patent number: 5266818
    Abstract: A compound semiconductor device wherein a contact to an n type Al.sub.x Ga.sub.1-x As layer comprises an In.sub.x Ga.sub.1-x As graded-composition layer, an In.sub.x Ga.sub.1-x As contact layer having a constant composition and a metal electrode layer, the In.sub.x Ga.sub.1-x As graded-composition layer is doped with an n type impurity which concentration is higher than a concentration of an impurity activated as n type, whereby, even when a thickness of the In.sub.x Ga.sub.1-x As graded-composition layer is made sufficiently small, a reduction in the carrier concentration of the thin graded-composition layer causes no increase of its resistance and a low-resistance contact is realized.
    Type: Grant
    Filed: March 17, 1992
    Date of Patent: November 30, 1993
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Kunio Tsuda, Kouhei Morizuka
  • Patent number: 5260603
    Abstract: A semiconductor device having a GaAs substrate and an ohmic electrode. An electrode pad is on part of the ohmic electrode and on part of the GaAs substrate outside the ohmic electrode. The electrode pad includes a first platinum film, a titanium film, a second platinum film, and a gold film which are sequentially deposited on one another. The first platinum film is thinner than each of the titanium film, second platinum film and gold film.
    Type: Grant
    Filed: September 8, 1992
    Date of Patent: November 9, 1993
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Mayumi Kamura, Souichi Imamura, Tatsuo Akiyama
  • Patent number: 5231302
    Abstract: A semiconductor device is made by etching a III-V compound semiconductor layer having a (100) surface using a mask having an opening defined by edges including at least one edge along an [011] direction of the layer so that the surface revealed by etching has a (111) orientation. An electrode is formed on the (111) surface by vacuum vapor deposition.
    Type: Grant
    Filed: November 15, 1991
    Date of Patent: July 27, 1993
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventor: Misao Hironaka