Abstract: A method for forming, on a surface of a thinned-down semiconductor substrate, a contact connected to a metal track of an interconnect stack formed on the opposite surface of the thinned-down substrate, including the steps of: forming, on the side of a first surface of a substrate, an insulating region penetrating into the substrate and coated with a conductive region and with an insulating layer crossed by conductive vias, the vias connecting a metal track of the interconnect stack to the conductive region; gluing the external surface of the interconnect stack on a support and thinning down the substrate; etching the external surface of the thinned-down substrate and stopping on the insulating region; etching the insulating region and stopping on the conductive region; and filling the etched opening with a metal.

Abstract: A silicide element separates a single crystal silicon node from an underlying silicon substrate, and is capable of acting as a conductive element for interconnecting devices on the device. The single crystal silicon node can act as one terminal of a diode, and a second semiconductor node on top of it can act as the other terminal of the diode. The single crystal silicon node can act as one of the terminals of the transistor, and second and third semiconductor nodes are formed in series on top of it, providing a vertical transistor structure, which can be configured as a field effect transistor or bipolar junction transistor. The silicide element can be formed by a process that consumes a base of a protruding single crystal element by silicide formation processes, while shielding upper portions of the protruding element from the silicide formation process.

Abstract: A memory device includes a diode driver and a data storage element, such as an element comprising phase change memory material, and in which the diode driver comprises a silicide element on a silicon substrate with a single crystal silicon node on the silicide element. The silicide element separates the single crystal silicon node from the underlying silicon substrate, preventing the flow of carriers from the single crystal silicon node into the substrate, and is capable of acting as a conductive element for interconnecting devices on the device. The single crystal silicon node acts as one terminal of a diode, and a second semiconductor node is formed on top of it, acting as the other terminal of the diode.

Abstract: In one embodiment, a lower interlayer dielectric layer, and first and second landing pads penetrating the lower interlayer dielectric layer are formed on a substrate. Interconnection patterns covering the second landing pads are formed on the lower interlayer dielectric layer. An etch stop layer is formed over the interconnection patterns. An upper interlayer dielectric layer filling a gap region between the interconnection patterns is formed on the etch stop layer. The upper interlayer dielectric layer is patterned to form a preliminary contact hole between the interconnection patterns, where the etch stop layer is exposed at the bottom of the preliminary contact hole. The preliminary contact hole is extended and the etch stop layer exposed by the extended preliminary contact hole is removed to form a first contact hole exposing the first landing pad. A buried contact plug is then formed within the first contact hole.

Abstract: An interconnect structure is provided. The interconnect structure includes an interconnect opening formed within a dielectric material, a diffusion barrier on the dielectric material, where the diffusion barrier contains a compound from a thermal reaction between cobalt (Co) metal from at least a portion of a cobalt metal layer formed on the dielectric material and a dielectric reactant element from the dielectric material. The interconnect structure further includes a cobalt nitride adhesion layer in the interconnect opening, and a Cu metal fill in the interconnect opening, wherein the diffusion barrier and the cobalt nitride adhesion layer surround the Cu metal fill within the interconnect opening.

Abstract: A cap layer for a copper interconnect structure formed in a first dielectric layer is provided. In an embodiment, the cap layer may be formed by an in-situ deposition process in which a process gas comprising germanium, arsenic, tungsten, or gallium is introduced, thereby forming a copper-metal cap layer. In another embodiment, a copper-metal silicide cap is provided. In this embodiment, silane is introduced before, during, or after a process gas is introduced, the process gas comprising germanium, arsenic, tungsten, or gallium. Thereafter, an optional etch stop layer may be formed, and a second dielectric layer may be formed over the etch stop layer or the first dielectric layer.

Abstract: An epitaxial Ni silicide film that is substantially non-agglomerated at high temperatures, and a method for forming the epitaxial Ni silicide film, is provided. The Ni silicide film of the present disclosure is especially useful in the formation of ETSOI (extremely thin silicon-on-insulator) Schottky junction source/drain FETs. The resulting epitaxial Ni silicide film exhibits improved thermal stability and does not agglomerate at high temperatures.

Abstract: Provided is a method for manufacturing a semiconductor device comprising: a process of forming a first trench 101 in insulating material layer 100 formed on a semiconductor substrate, wherein the first trench has an upper width W2 larger than an lower width W1, and is extended in a first direction; a process of forming embedded layer 102 within the first trench 101, wherein the embedded layer has a height lower than the top of the trench; a process of forming side-walls 103 to cover wall surfaces of the first trench 101 exposed on embedded layer 102; and a process of etching embedded layer 102 using side-wall 103 as a mask to separate the embedded layer in the first direction.

Abstract: A semiconductor structure and method of fabricating the structure. The method includes removing the backside silicon from two silicon-on-insulator wafers having devices fabricated therein and bonding them back to back utilizing the buried oxide layers. Contacts are then formed in the upper wafer to devices in the lower wafer and wiring levels are formed on the upper wafer. The lower wafer may include wiring levels. The lower wafer may include landing pads for the contacts. Contacts to the silicon layer of the lower wafer may be silicided.

Abstract: A layer-stacked wiring made up of a microcrystalline silicon thin film and a metal thin film is provided which is capable of suppressing an excessive silicide formation reaction between the microcrystalline silicon thin film and metal thin film, thereby preventing peeling of the thin film. In a polycrystalline silicon TFT (Thin Film Transistor) using the layer-stacked wiring, the microcrystalline silicon thin film is so configured that its crystal grains each having a length of the microcrystalline silicon thin film in a direction of a film thickness being 60% or more of a film thickness of the microcrystalline silicon thin film amount to 15% or less of total number of crystal grains or that its crystal grains each having a length of the microcrystalline silicon thin film in a direction of a film thickness being 50% or less of a film thickness of the microcrystalline silicon thin film amount to 85% or more of the total number of crystal grains making up the microcrystalline silicon thin film.

Abstract: A trenched semiconductor power device includes a trenched gate insulated by a gate insulation layer and surrounded by a source region encompassed in a body region above a drain region disposed on a bottom surface of a semiconductor substrate. The source region surrounding the trenched gate includes a metal of low barrier height to function as a Schottky source. The metal of low barrier height further may include a PtSi or ErSi layer. In a preferred embodiment, the metal of low barrier height further includes an ErSi layer. The metal of low barrier height further may be a metal silicide layer having the low barrier height. A top oxide layer is disposed under a silicon nitride spacer on top of the trenched gate for insulating the trenched gate from the source region. A source contact disposed in a trench opened into the body region for contacting a body-contact dopant region and covering with a conductive metal layer such as a Ti/TiN layer.

Abstract: An integrated circuit includes a plurality of signal lines. A first signal line layer includes a plurality of first signal lines. A second signal line layer includes a plurality of second signal lines arranged on top of and insulated from the first signal line layer. A third signal line layer includes a plurality of third signal lines arranged on top of and insulated from the second signal line layer. A contact extends through the second signal line layer and connects at least one of the plurality of third signal lines to at least one of the first signal lines. At least one of the second signal lines further extends in a second direction to bend around the contact such that a predetermined distance separates the plurality of second signal lines from the contact.

Abstract: Methods of forming buried bit lines in a non-volatile memory device can include forming impurity regions in a substrate of a non-volatile memory device to provide immediately neighboring buried bit lines for the device and then forming a shallow trench isolation region in the substrate between the immediately neighboring buried bit lines to substantially equalize lengths of the immediately neighboring buried bit lines.

Abstract: A semiconductor device manufacturing method which achieves a contact of a low resistivity is provided. In a state where a first metal layer in contact with a semiconductor is covered with a second metal layer for preventing oxidation, only the first metal layer is silicided to form a silicide layer with no oxygen mixed therein. As a material of the first metal layer, a metal having a work function difference of a predetermined value from the semiconductor is used. As a material of the second metal layer, a metal which does not react with the first metal layer at an annealing temperature is used.

Abstract: Semiconductor fabricating technology is provided, and particularly, a method of fabricating a semiconductor device improving a contact characteristic between a silicon layer including carbon and a metal layer during a process of fabricating a semiconductor device is provided. A semiconductor device including the silicon layer including carbon and the metal layer formed on the silicon layer is provided. A metal silicide layer is interposed between the silicon layer including carbon and the metal layer.

Abstract: A semiconductor device includes a semiconductor substrate, a p-channel MIS transistor formed on the substrate, the p-channel transistor having a first gate dielectric formed on the substrate and a first gate electrode layer formed on the first dielectric, and an n-channel MIS transistor formed on the substrate, the n-channel transistor having a second gate dielectric formed on the substrate and a second gate electrode layer formed on the second dielectric. A bottom layer of the first gate electrode layer in contact with the first gate dielectric and a bottom layer of the second gate electrode layer in contact with the second gate dielectric have the same orientation and the same composition including Ta and C, and a mole ratio of Ta to a total of C and Ta, (Ta/(Ta+C)), is larger than 0.5.

Abstract: System and method for reducing contact resistance and improving barrier properties is provided. An embodiment comprises a dielectric layer and contacts extending through the dielectric layer to connect to conductive regions. A contact barrier layer is formed between the conductive regions and the contacts by electroless plating the conductive regions after openings have been formed through the dielectric layer for the contact. The contact barrier layer is then treated to fill the grain boundary of the contact barrier layer, thereby improving the contact resistance. In another embodiment, the contact barrier layer is formed on the conductive regions by electroless plating prior to the formation of the dielectric layer.

Abstract: In one embodiment, silicide layers are formed on two oppositely doped adjacent semiconductor regions. A conductor material is formed electrically contacting both of the two silicides.

Abstract: The present invention provides a semiconductor device having dual silicon nitride liners and a reformed silicide layer and related methods for the manufacture of such a device. The reformed silicide layer has a thickness and resistance substantially similar to a silicide layer not exposed to the formation of the dual silicon nitride liners. A first aspect of the invention provides a method for use in the manufacture of a semiconductor device comprising the steps of applying a first silicon nitride liner to a silicide layer, removing a portion of the first silicon nitride liner, reforming a portion of the silicide layer removed during the removal step, and applying a second silicon nitride liner to the silicide layer.

Abstract: The semiconductor device comprises a word line and a bit line. The word line comprises a gate electrode and a first metal interconnect. The first metal interconnect has contact with the gate electrode and extends into a region upper than a first impurity-diffused region in a first direction. The bit line comprises a connecting part and a second metal interconnect. The connecting part is formed so as to have contact with at least part of the side surface of the first impurity-diffused region. The second metal interconnect has contact with the connecting part and extends into a region lower than the semiconductor region in a second direction orthogonal to the first direction.

Abstract: Some embodiments include methods of forming semiconductor constructions. Oxide is formed over a substrate, and first material is formed over the oxide. Second material is formed over the first material. The second material may be one or both of polycrystalline and amorphous silicon. A third material is formed over the second material. A pattern is transferred through the first material, second material, third material, and oxide to form openings. Capacitors may be formed within the openings. Some embodiments include semiconductor constructions in which an oxide is over a substrate, a first material is over the oxide, and a second material containing one or both of polycrystalline and amorphous silicon is over the first material. Third, fourth and fifth materials are over the second material. An opening may extend through the oxide; and through the first, second, third, fourth and fifth materials.

Abstract: A semiconductor device includes at least one phase-change pattern disposed on a semiconductor substrate. A planarized capping layer, a planarized protecting layer, and a planarized insulating layer are sequentially stacked to surround sidewalls of the at least one phase-change pattern. An interconnection layer pattern is disposed on the planarized capping layer, the planarized protecting layer, and the planarized insulating layer. The interconnection layer pattern is in contact with the phase-change pattern.

Abstract: Disclosed are embodiments of a wafer that incorporates fill structures with varying configurations to provide uniform reflectance. Uniform reflectance is achieved by distributing across the wafer fill structures having different semiconductor materials such that approximately the same ratio and density between the different semiconductor materials is achieved within each region and, optimally, each sub-region. Alternatively, it is achieved by distributing across the wafer fill structures, including one or more hybrid fill structure containing varying proportions of different semiconductor materials, such that approximately the same ratio between the different semiconductor materials is achieved within each region and, optimally, each sub-region.

Abstract: A device including a first body (101) with terminals (102) on a surface (101a), each terminal having a metallic connector (110), which is shaped as a column substantially perpendicular to the surface. Preferably, the connectors have an aspect ratio of height to diameter of 2 to 1 or greater, and a fine pitch center-to-center. The connector end (110a) remote from the terminal is covered by a film (130) of a sintered paste including a metallic matrix embedded in a first polymeric compound. Further a second body (103) having metallic pads (140) facing the respective terminals (102). Each connector film (130) is in contact with the respective pad (140), whereby the first body (101) is spaced from the second body (103) with the connector columns (110) as standoff. A second polymeric compound (150) is filling the space of the standoff.

Abstract: A method of producing an ohmic contact and a resulting ohmic contact structure are disclosed. The method includes the steps of forming a deposited film of nickel and silicon on a silicon carbide surface at a temperature below which either element will react with silicon carbide and in respective proportions so that the atomic fraction of silicon in the deposited film is greater than the atomic fraction of nickel, and heating the deposited film of nickel and silicon to a temperature at which nickel-silicon compounds will form with an atomic fraction of silicon greater than the atomic fraction of nickel but below the temperature at which either element will react with silicon carbide. The method can further include the step of annealing the nickel-silicon compound to a temperature higher than the heating temperature for the deposited film, and within a region of the phase diagram at which free carbon does not exist.

Abstract: Semiconductor devices containing nickel-titanium (NiTi or TiNi) compounds (or alloys) and methods for making such devices are described. The devices contain a silicon substrate with an integrated circuit having a drain on the backside of the substrate, a TiNi contact layer contacting the drain on the backside of the substrate, a soldering layer on the contact layer, an oxidation reducing layer on the soldering layer, a solder bump on the soldering layer, and a lead frame attached to the solder bump. The combination of the Ti and Ni materials in the contact layer exhibits many features not found in the Ti and Ni materials alone, such as reduced backside on-resistance, ability to form a silicide with the Si substrate at lower temperatures, reduced wafer warpage, increased ductility for improved elasticity, and good adhesion properties. Other embodiments are described.

Abstract: The present invention relates to a semiconductor device with an epitaxially grown titanium silicide layer having a phase of C49 and a method for fabricating the same. This titanium silicide layer has a predetermined interfacial energy that does not transform the phase of the titanium layer, and thus, occurrences of agglomeration of the titanium layer and a grooving phenomenon can be prevented. The semiconductor device includes: a silicon layer; an insulation layer formed on the silicon layer, wherein a partial portion of the insulation layer is opened to form a contact hole exposing a partial portion of the silicon layer; an epitaxially grown titanium silicide layer having a phase of C49 and formed on the exposed silicon substrate disposed within the contact hole; and a metal layer formed on an upper surface of the titanium silicide layer.

Abstract: The present invention relates to an interconnect capping layer and a method of fabricating a capping layer for an interconnect. In particular, but not exclusively, the invention relates to a capping layer for a copper interconnect used to interconnect elements in an integrated circuit. Embodiments of the invention provide a method of fabricating a capping layer for an interconnect in an integrated circuit, comprising the steps of: forming an interconnect comprising upper and lower lateral surfaces; forming a lateral diffusion stop layer between said lateral surfaces; and forming a capping layer.

Abstract: A semiconductor device is provided wherein a foundation insulating film is formed over a semiconductor substrate, a metal resistance element is formed on the foundation insulating film, and contacts are formed at both ends of the metal resistance element in a longitudinal direction of the metal resistance element and connected to the metal resistance element. The foundation insulating film comprises a single upwardly concave curved surface constituting not less than about 40 percent of an upper surface of the metal resistance element between the contacts in the longitudinal direction thereof. The curved surface of the foundation insulating film causes the metal resistance element to comprise a single upwardly concave curved surface constituting not less than about 40 percent of upper and lower surfaces of the metal resistance element between the contacts in the longitudinal direction thereof.

Abstract: A semiconductor device including a substrate, a metal wiring on the substrate, an insulation film on the substrate covering the metal wiring, a connection hole in the insulation film which extends to a portion of the metal wiring, a via in the connection hole, and an alloy layer. The metal wiring includes a first metallic material, the alloy layer comprises a portion of the metal wiring and a second metallic material which is different than the first metallic material, and the via extends to the alloy layer.

Abstract: A layer-stacked wiring made up of a microcrystalline silicon thin film and a metal thin film is provided which is capable of suppressing an excessive silicide formation reaction between the microcrystalline silicon thin film and metal thin film, thereby preventing peeling of the thin film. In a polycrystalline silicon TFT (Thin Film Transistor) using the layer-stacked wiring, the microcrystalline silicon thin film is so configured that its crystal grains each having a length of the microcrystalline silicon thin film in a direction of a film thickness being 60% or more of a film thickness of the microcrystalline silicon thin film amount to 15% or less of total number of crystal grains or that its crystal grains each having a length of the microcrystalline silicon thin film in a direction of a film thickness being 50% or less of a film thickness of the microcrystalline silicon thin film amount to 85% or more of the total number of crystal grains making up the microcrystalline silicon thin film.

Abstract: In one embodiment of the present invention, a high withstand voltage transistor is disclosed having small sizes including an element isolating region. The semiconductor device is provided with the element isolating region formed on a semiconductor substrate; an active region demarcated by the element isolating region; a gate electrode formed on the semiconductor substrate in the active region by having a gate insulating film in between; a channel region arranged in the semiconductor substrate under the gate electrode; a source region and a drain region positioned on the both sides of the gate electrode; and a drift region positioned between one of or both of the source region and the drain region and the channel region. One of or both of the source region and the drain region are at least partially positioned on the element isolating region, and are connected with the channel region through the drift region.

Abstract: A cap layer for a copper interconnect structure formed in a first dielectric layer is provided. In an embodiment, the cap layer may be formed by an in-situ deposition process in which a process gas comprising germanium, arsenic, tungsten, or gallium is introduced, thereby forming a copper-metal cap layer. In another embodiment, a copper-metal silicide cap is provided. In this embodiment, silane is introduced before, during, or after a process gas is introduced, the process gas comprising germanium, arsenic, tungsten, or gallium. Thereafter, an optional etch stop layer may be formed, and a second dielectric layer may be formed over the etch stop layer or the first dielectric layer.

Abstract: A method and apparatus for partially strapping two polysilicon lines, each having a first end and second end, uses a metal line having a plurality of spaced apart metal segments with each metal segment partially strapping a different portion of a polysilicon line. The metal segments are arranged from the first end to the second end with the signals propagating from the second end to the first end. Where two metal segments are used, the segments have lengths of x = 2 ? ? L 7 and L-X where L is the length between the first end and the second end. Where three segments are used, the segments have lengths of X=0.25 L, Y=0.48 L, and Z=0.27 L.

Abstract: A method for forming a metal silicide region in a silicon region of a semiconductor substrate. The method comprises forming a metal layer over the silicon region, then in succession forming a titanium and a titanium nitride layer thereover. As the substrate is heated to form the silicide, the titanium getters silicon dioxide on the surface of the silicon region and the titanium nitride promotes the formation of a smooth surface at the interface between the silicide layer and the underlying silicon region.

Abstract: In one embodiment, silicide layers are formed on two oppositely doped adjacent semiconductor regions. A conductor material is formed electrically contacting both of the two silicides.

Abstract: A monolithic substrate contains an integrated circuit comprising an amplifier having input and output, a mixer and a hybrid coupler for coupling the amplifier to the mixer. Metallic pads on the substrate are connected to each of two ports of the coupler and separate metallic pads are also connected to each of the input and output of the amplifier. The metallic pads allow the amplifier and mixer to be separately tested by a probe and the input or the output of the amplifier to be selectively connected to the mixer to enable the circuit to operate either as a receiver or transmitter. Alternatively, connections between the mixer and both input and output of the amplifier may be preformed and one of the connections subsequently severed depending on whether the circuit is to operate in receive or transmit mode.

Abstract: In accordance with an embodiment of the present invention, a semiconductor wafer has a plurality of dies each having a circuit and a plurality of contact pads. The plurality of contact pads include a first contact pad to receive a power supply voltage, a second contact pad to receive a ground voltage, and a third contact pad to receive a test control signal. The third contact pad is connected to a programmable self-test engine (PSTE) embedded on the corresponding die so that the test control signal activates the PSTE to initiate a self-test. A probe card has a plurality of sets of probe pins, each set of probe pins having three probe pins for contacting the first, second, and third contact pads of one of a corresponding number of the plurality of dies. During wafer test, the plurality of sets of probe pins come in contact with a corresponding number of dies so that the self-test is carried out simultaneously in the corresponding number of dies.

Abstract: A method for fabricating a semiconductor device, includes forming a dielectric film above a substrate; forming an opening in the dielectric film; forming a first film containing a metal whose energy for forming silicide thereof is lower than that of Cu silicide inside the opening; forming a second film that is conductive and contains copper (Cu) in the opening in which the first film containing the metal is formed; and forming a compound film containing Cu and silicon (Si) selectively on the second film in an atmosphere in which a temperature of the substrate is below 300° C.

Abstract: In a method of fabricating a semiconductor device capable of reducing parasitic capacitance between bit lines and a semiconductor device fabricated by the method, the semiconductor device includes a semiconductor substrate having buried contact landing pads and direct contact landing pads. A lower interlayer insulating layer is disposed on the semiconductor substrate. A plurality of parallel bit line patterns are disposed on the lower interlayer insulating layer to fill the direct contact holes. A passivation layer that conformally covers the lower interlayer insulating layer and the bit line patterns is formed. An upper interlayer insulating layer for covering the semiconductor substrate having the passivation layer is formed. Buried contact plugs are disposed in the upper interlayer insulating layer between the bit line patterns and extended to contact the respective buried contact landing pads through the passivation layer and the lower interlayer insulating layer.

Abstract: An improved semiconductor structure consists of interconnects in an upper interconnect level connected to interconnects in a lower interconnect level through use of a conductive protrusion located at the bottom of a via opening in an upper interconnect level, the conductive protrusion extends upward from bottom of the via opening and into the via opening. The improved interconnect structure with the conductive protrusion between the upper and lower interconnects enhances overall interconnect reliability.

Abstract: A semiconductor device includes a first copper-containing conductive film formed on a substrate, insulating films formed on the first copper-containing conductive film with a concave portion reaching the first copper-containing conductive film, a second barrier insulating film formed to cover the side wall of the concave portion of these insulating films, a second adhesive alloy film made of copper and a dissimilar element other than copper, and coming in contact with the first copper-containing conductive film at the bottom surface of the concave portion and in contact with the second barrier insulating film at the side wall of the concave portion to cover the inside wall of the concave portion, and a second copper-containing conductive film containing copper as a main component, and formed on the second adhesive alloy film in contact with the second adhesive alloy film to fill the concave portion.

Abstract: Methods and apparatus relating to a single silicon wafer having metal and alloy silicides are described. In one embodiment, two different silicides may be provided on the same wafer. Other embodiments are also disclosed.

Abstract: A method of monitoring and testing electro-migration and time dependent dielectric breakdown includes forming an addressable wiring test array, which includes a plurality or horizontally disposed metal wiring and a plurality of segmented, vertically disposed probing wiring, performing a single row continuity/resistance check to determine which row of said metal wiring is open, performing a full serpentine continuity/resistance check, and determining a position of short defects.

Abstract: An integrated circuit structure includes a semiconductor substrate having a front side and a backside. A through-silicon via (TSV) penetrates the semiconductor substrate. The TSV has a back end extending to the backside of the semiconductor substrate. A redistribution line (RDL) is over the backside of the semiconductor substrate and connected to the back end of the TSV. A silicide layer is over and contacting the RDL.

Abstract: Methods and associated structures of forming a microelectronic device are described. Those methods may include forming a contact opening in an inter layer dielectric (ILD) disposed on a substrate, wherein a source/drain contact area is exposed, forming a rare earth metal layer on the source/drain contact area, forming a transition metal layer on the rare earth metal layer; and annealing the rare earth metal layer and the transition metal layer to form a metal silicide stack structure.

Abstract: A bond pad structure for an integrated circuit chip has a stress-buffering layer between a top interconnection level metal layer and a bond pad layer to prevent damages to the bond pad structure from wafer probing and packaging impacts. The stress-buffering layer is a conductive material having a property selected from the group consisting of Young's modulus, hardness, strength and toughness greater than the top interconnection level metal layer or the bond pad layer. For improving adhesion and bonding strength, the lower portion of the stress-buffering layer may be modified as various forms of a ring, a mesh or interlocking-grid structures embedded in a passivation layer, alternatively, the stress-buffering layer may has openings filled with the bond pad layer.

Abstract: In the present invention, a wiring layer comprises wirings respectively having different sheet resistance values, or a contact for connecting opposing wiring layers comprises contacts having different sheet resistance values respectively.

Abstract: The present invention provides a method of fabricating a semiconductor device, which could advance the commercialization of semiconductor devices with a copper interconnect. In a process of metal interconnect line fabrication, a TiN thin film combined with an Al intermediate layer is used as a diffusion barrier on trench or via walls. For the formation, Al is deposited on the TiN thin film followed by copper filling the trench. Al diffuses to TiN layer and reacts with oxygen or nitrogen, which will stuff grain boundaries efficiently, thereby blocking the diffusion of copper successfully.

Abstract: A 4-T SRAM cell in which two layers of permanent SOG (with an intermediate oxide layer) are used to provide planarization between the first and topmost poly layers.