Abstract: A semiconductor device comprises select gates and control gates of a plurality of memory cells therebetween so that gate members on upper portions of stacked gates may cross element regions. A metal interconnection is disposed parallel to an upper layer of the element region. A source line SL is arranged at intervals of plural bit lines BL. The source line is led to a source line contact through a conductive member composed of a low-resistance metal in the same manner as a bit line contact.

Abstract: Disclosed are structures and processes which are related to asymmetric, self-aligned silicidation in the fabrication of integrated circuits. A pre-anneal contact stack includes a silicon substrate, a metal source layer such as titanium-rich titanium nitride (TiN.sub.x), and a silicon layer. The metal nitride layer is deposited on the substrate by sputtering a target metal reactively in nitrogen and argon ambient. A N:Ar ratio is selected to deposit a uniform distribution of the metal nitride in an unsaturated mode (x<1) over the silicon substrate. The intermediate substrate structure is sintered to form a metal silicide. The silicidation of metal asymmetrically consumes less of the underlying silicon than the overlying silicon layer. The resulting structure is a mixed metal silicide/nitride layer which has a sufficient thickness to provide low sheet resistance without excessively consuming the underlying substrate.

Abstract: A semiconductor processing method of making electrical connection between an electrically conductive line and a node location includes, a) forming an electrically conductive line over a substrate, the substrate having an outwardly exposed silicon containing node location to which electrical connection is to be made, the line having an outer portion and an inner portion, the inner portion laterally extending outward from the outer portion and having an outwardly exposed portion, the inner portion having a terminus adjacent the node location, and b) electrically connecting the extending inner portion with the node location. An integrated circuit is also described. The integrated circuit includes a semiconductor substrate, a node location on the substrate, and a conductive line over the substrate which is in electrical communication with the node location. The conductive line includes an outer portion and an inner portion.

Abstract: There is provided a method of fabricating a CMOS semiconductor device including nMOSFET and pMOSFET, including the steps of (a) forming a gate insulating film on a semiconductor substrate, (b) forming a first polysilicon film on the gate insulating film, (c) forming an interlayer insulating film on the first polysilicon film, (d) forming a second polysilicon film on the interlayer insulating film, (e) shaping the first polysilicon film, the interlayer insulating film, and the second polysilicon film into a gate electrode in both a first region where the nMOSFET is to be fabricated and a second region where the pMOSFET is to be fabricated, and (f) doping n-type impurities into the first region and p-type impurities into the second region by ion-implantation. The method makes it possible to prevent reduction in dielectric voltage of a gate insulating film, which would be caused by diffusion of titanium atoms, without causing a gate electrode to be depleted.

Abstract: There is provided a semiconductor memory device including a semiconductor substrate, a pair of transfer transistors formed on the substrate, a pair of driver transistors formed on the substrate, first and second thin film load transistors formed above the transfer transistors and the driver transistors with an interlayer insulative film sandwiched therebetween, a drain region of the first thin film load transistor having at least one portion over which a gate electrode of the second thin film load transistor partially lies. The portion is heavily doped with impurities. The above mentioned semiconductor memory device prevents reduction in ON-state current in thin film transistors, and hence improves stability in operation of SRAM cell having a top gate type thin film transistor.

Abstract: In a non-volatile memory, memory cells have respective floating gates formed of a first polysilicon and respective control gates formed of a second polysilicon. Further, in the non-volatile memory, peripheral circuits include transistors having respective gates formed of the first polysilicon. In addition, a silicide layer is formed directly on the control gates of the memory cells and directly on the gates of the transistors.

Abstract: Multi-level semiconductor devices are formed with reduced parasitic capacitance without sacrificing structural integrity or electromigation performance by removing the inter-layer dielectrics and supporting the interconnection system with a rigid lining. Embodiments include depositing a dielectric sealing layer, e.g., silicon oxide, silicon nitride or composite of silicon oxide/silicon nitride, before forming the first metallization level, removing the inter-layer dielectrics after forming the last metallization level, lining the interconnection system with undoped polycrystalline silicon and forming a dielectric protective layer, e.g. a silane derived oxide, on the uppermost metallization level.

Abstract: A low-concentration impurity region and a high-concentration impurity region are formed respectively near the lower surface and the upper surface of an undoped polysilicon film by a first and second ion-implanations. A refractory metal film of tungsten or the like is formed on the polysilicon film. The impurities are thermally diffused to form shallow-junctions of source/drain having low-concentration impurities. Lead-out electrodes having a high-impurity concentration can be formed without impeding formation of the source and drain. The refractory metal film is converted into a silicide with the resistance at the interface between the polysilicon film and the silicide kept lowered.

Abstract: An interconnecting structure for a semiconductor integrated circuit and a method for manufacturing said interconnecting structure. The interconnecting structure comprises a top layer, a bottom layer, and a dielectric isolation layer. The top layer completely covers and encloses the bottom layer. The dielectric isolation layer is disposed between the top layer and the bottom layer. At least one contact opening is formed through the top layer of the structure, thereby exposing a selected region of said bottom layer. A contact is formed on the selected region of the bottom layer.

Abstract: A technique for fabricating an integrated circuit device 100 using an inverse-T tungsten gate structure 121 overlying a silicided layer 119 is provided. This technique uses steps of forming a high quality gate oxide layer 115 overlying a semiconductor substrate 111. The silicided layer 119 is defined overlying the gate oxide layer 115. The silicided layer 119 does not substantially react to this layer. The technique defines the inverse-T tungsten gate electrode layer 121 overlying the silicided layer 119. A top surface of this gate electrode may also be silicided 127 to further reduce the resistance of this device element.

Abstract: A method and the resulting device to permit the formation of minimal insulating space between polysilicon gates by forming an insulating layer over the polysilicon gates and protecting selected ones of the gates and the insulating layer with an etch barrier so that the opening for local interconnect metallization can be misaligned and the selected gates will be protected by its etch barrier and not be exposed to the opening. Further, local interconnect conductive material can pass over a gate or unrelated resistor without shorting the gate/resistor.

Abstract: A metallic layer (10), a thin-film first polycrystalline silicon layer (14), a first contact hole for connecting the metallic layer and first polycrystalline silicon layer, a second polycrystalline silicon layer (18) which becomes an etching stopper layer for the prevention of penetration in the first contact hole area, and a second contact hole which connects the second polycrystalline silicon layer and the first polycrystalline silicon layer are included. P-type impurities are introduced into the first polycrystalline silicon layer, and the second polycrystalline silicon layer is non-doped in the first contact hole area. By a heating step, the P-type impurities in the first polycrystalline silicon layer are diffused to the second polycrystalline silicon layer. The second polycrystalline silicon layer is N-type in a memory cell area.

Abstract: A multilevel interconnection between a polycide layer and a polysilicon layer and a method of forming thereof are provided. The multilevel interconnection comprises: a first impurity-containing conductive layer formed on a semiconductor substrate; a first silicide layer, having a first region thinner than a second region, formed on the first impurity-containing conductive layer; an interlayer dielectric layer formed in other than the first region; a contact hole for exposing the first silicide layer of the first region; and a second impurity-containing conductive layer connected to the first silicide layer through the contact hole. Therefore, increases in contact resistance between conductive layers can be prevented.

Abstract: The present invention includes forming a conductive layer on a substrate. Portions of the conductive layer are removed using a first photoresist layer as a mask. A first oxide layer is formed over the conductive layer and the substrate, and an amorphous silicon layer is then formed on the first oxide layer. After annealing the amorphous silicon layer, thereby transforming amorphous silicon layer to a polysilicon layer, a second oxide layer is formed on the polysilicon layer. The second oxide layer is removed using a second photoresist layer as a mask. An amorphous silicon carbon layer is formed over the second oxide layer and the polysilicon layer, and a heavily-doped amorphous silicon carbon layer is formed on the amorphous silicon carbon layer.

Abstract: A method of forming buried contacts in MOSFET and CMOS devices which substantially reduces the depth of the buried contact trench. A split polysilicon process is used to form the gate electrode and contact electrode. The first polysilicon layer is very thin layer of undoped polysilicon, having a thickness of less than 100 Angstroms. The second polysilicon layer is a layer of doped polysilicon having a thickness of between about 950 and 1150 Angstroms. The buried contact can be formed either using ion implantation or diffusion of impurities from the layer of doped second polysilicon into the contact region. When the metal layers are etched to form the gate electrode and contact electrode the resulting buried contact trench is less than 500 Angstroms deep.

Abstract: On the back side of a base body, three layers of polysilicon layer are formed. These polysilicon layers contain boron. A boron concentration C.sub.B(1), C.sub.B(2) and C.sub.B(3) of the first, second and third polysilicon layers from the base body side have a relationship of C.sub.B(1) .ltoreq.C.sub.B(2) .ltoreq.C.sub.B(3). On the other hand, between the polysilicon layers, silicon oxide layers are formed respectively. Upon fabrication of a semiconductor device, at first, a gettering heat treatment is effected for the substrate under a given condition. Thus, contaminating impurity is captured at the grain boundary of polysilicon layers formed on the back side of the base body. Next, the polysilicon formed at the most back side is removed by etching. By this, contaminated impurity is removed from the semiconductor substrate.

Abstract: SRAM memory cells is provided with high resistance to soft error and no parasitic capacitance due to PN junction. SRAM memory cells comprises the load resister is a thin film transistor having a same conductive type as that of the driver transistor.

Abstract: The semiconductor device has a substrate 101 having a first portion and a second portion, a field insulating film 102 formed on first portion of the substrate, a gate insulating film 103 formed on second portion of the substrate, a first conductive layer 104 selectively formed on the field insulating film and the gate insulating film, a first insulating 108 layer formed on the field insulating film, the gate insulating film, and first conductive layer, a hole 109 formed in first insulating layer exposing a surface of first conductive layer, a second conductive layer 110 selectively formed on a whole surface of the hole and first insulating film, and a high melting point metal selectively formed on second conductive layer.

Abstract: A multi-layered wiring structure includes a lower wiring having an upper surface, a first inter-level insulating layer having a first flat upper surface substantially coplanar with the upper surface of the lower conductive wiring and a recess contiguous to the first flat upper surface, a spin-on-glass layer filling the recess and having a second flat upper surface substantially coplanar with the first flat upper surface, a second inter-level insulating layer covering the first and second flat surfaces and the upper surface of the lower conductive wiring and an upper conductive wiring extending on the second inter-level insulating layer and passing through a contact hole of the second inter-level insulating layer so as to be held in contact with the lower conductive wiring, and the first and second flat upper surfaces are created through an etch-back using gaseous etchant equally etching the first inter-level insulating layer and the spin-on-glass layer, thereby creating smooth surface under the second inter-l

Abstract: A method is provided for forming an improved landing pad of a semiconductor integrated circuit, and an integrated circuit formed according to the same. A first opening is formed through a first dielectric layer to expose a portion of a diffused region. A dual polysilicon landing pad is formed in the first opening and on a portion of the first dielectric layer adjacent the first opening. The dual landing pad is preferably formed from two polysilicon landing pads with an oxide formed in between a portion of the two polysilicon layers and over the first polysilicon layer. This landing pad will enhance the planarization of the wafer at this stage of the manufacturing and tolerate misalignment of subsequently formed metal contacts without invading design rules.

Abstract: A gate oxide film is formed on an element region at the surface of a silicon substrate. A polycrystalline silicon film doped with a large amount of phosphorus is formed on the gate oxide by the CVD method. A titanium nitride layer with about 10 nm thickness is deposited on the polycrystalline film by the sputtering method. Further, a titanium silicide thin film with a 100 nm thickness is deposited on the titanium nitride layer. Furthermore, a silicon layer with about 50 nm thickness is formed on the titanium silicide thin film. Accordingly, a gate electrode is provided.

Abstract: The present invention provides a method of forming a tapered polysilicon contact plug having reduced dimensions beyond the normal resolution limit of a photolithographic method by utilizing at least one polysilicon sidewall spacer as a mask in an anisotropic etching process of an oxide layer such that a contact window of reduced dimensions can be formed for the subsequent deposition of a heavily-doped polysilicon for forming the contact plug.

Abstract: A semiconductor device comprises a first transistor having a composite gate structure containing a lamination of a first polycrystalline silicon film, an interlayer insulating film, and a second polycrystalline silicon film; and a second transistor having a single gate structure containing a lamination of a third polycrystalline silicon film and a fourth polycrystalline silicon film, wherein the first polycrystalline silicon film and the third polycrystalline silicon film have substantially the same thickness; the first polycrystalline silicon film and the third polycrystalline silicon film have different impurity concentrations controlled independently of each other; the second polycrystalline silicon film and the fourth polycrystalline silicon film have substantially the same thickness, and the second polycrystalline silicon film, the fourth polycrystalline silicon film, and the third polycrystalline silicon film have substantially the same impurity concentration.

Abstract: A silicon layer serving as a contact plug directly connected to a diffusion layer of a MOS transistor is provided. On a surface of an N.sup.- type diffusion layer in self-alignment with a silicon nitride layer spacer and a field oxide layer, an N.sup.+ type monocrystalline silicon layer formed by anisotropic selective epitaxial growth method is directly connected. The surface of the N.sup.+ type monocrystalline silicon layer is directly connected to an N.sup.+ type monocrystalline silicon layer formed by isotropic selective epitaxial growth.

Abstract: A semiconductor device comprising, a semiconductor substrate, a first gate insulator film formed on the semiconductor substrate, a floating gate formed on the first gate insulator film, a second insulator film formed on the floating gate, a control gate formed on the second insulator film, and a silicon film doped with nitrogen and an impurity, and interposed between the floating gate and the second gate insulator film and/or between the second gate insulator film and the control gate.

Abstract: The invention concerns integrated circuits in which a MACRO is embedded in a standard cell array. One level of metal is devoted exclusively to non-local interconnect, and a layer of polysilicon is devoted to local interconnect, thereby saving significant space.

Abstract: A semiconductor device comprises a first conducting layer, a first insulating layer formed on the first conducting layer, a second conducting layer formed on the first insulating layer and facing the first conducting layer, wherein, at least part of a peripheral portion of the region of at least one of the first and second conducting layers, in contact with the first insulating layer, includes an amorphous conducting layer made of a semiconductor, and the amorphous conducting layer contains at least one element selected from the group consisting of oxygen, nitrogen, carbon, argon, chlorine, and fluorine and a total concentration of the at least one element falls within the range from 0.1 atomic % to 20 atomic %.

Abstract: In a micro-patterned semiconductor device that uses thin-film polycrystalline silicon for both interconnection and TFT (Thin Film Transistor) configuration elements, the required current supply capacity is achieved by increasing the leakage current of a reverse-direction diode when the reverse-direction junction diode is present in the current path consisting of polycrystalline silicon. Leakage current is increased by steepening the density slope at the PN junction of the diode which consists of polycrystalline silicon, or by making the region near the junction amorphous. For example, sufficient current can be supplied to a large number of memory cells via reverse-direction diodes even when cells that use TFTs consisting of thin-film polycrystalline silicon as the load for the flip-flop are used as large-scale SRAM memory cells. In this way, ultra high-integration memory ICs can be realized.

Abstract: A semiconductor processing method includes: a) providing a substrate having a base region to which electrical connection is to be made; b) providing a first layer of a conductive first material; c) providing an etch stop layer over the first layer; d) etching a contact opening through the etch stop and first layers to the base region; e) providing a second layer of first material outwardly of the etch stop layer and within the contact opening to a thickness greater than the first layer thickness and extending outwardly beyond the contact opening upper edge; f) removing first material of the second layer and defining a second layer plug within the contact, the second layer plug having an outermost surface extending outwardly beyond the contact opening upper edge and thereby providing the second layer plug to be of greater thickness than the first layer; g) masking outwardly of the first layer and the second layer plug to define a mask pattern for definition of a circuit component from the first layer which con

Abstract: Capacitor arrays may be incorporated within silicon integrated circuits as part of analog-to-digital or digital-to-analog converters. Capacitance ratios between individual capacitors need to be controlled to better than 1%. Because of microloading effects during etching, the areas of the electrodes of the capacitors located along the edges of the array have tended to be slightly less than the areas of electrodes located completely inside the array. The present invention solves this problem by providing additional electrodes located along the periphery of the array, spaced the same distance away from the array edge as the spacing between electrodes inside the array.

Abstract: A field effect transistor comprises a semiconductor substrate having a main surface and a predetermined impurity concentration of a first conductivity type, impurity layers of a second conductivity type formed spaced apart at the main surface of the semiconductor substrate, and a shaped conductive layer serving as a gate electrode. The impurity layers constitute source.multidot.drain regions, and a region between the impurity layers defines a channel region in the main surface. The shaped conductive layer is formed on the channel region with an insulating film therebetween. The shaped conductive layer has an upper portion and a lower portion wherein the upper portion is longer than the lower portion and the length of the lower portion adjacent the insulating film is substantially equal to or shorter than the length of the channel region at the main surface. Additionally, the upper and lower portions of the shaped conductive layer are formed of the same base composition.

Abstract: A semiconductor memory device including memory cells with the stacked-capacitor structure that makes it possible to prevent a contact pad from being damaged. This device includes a memory cell area and a peripheral circuit area formed on a semiconductor substrate. An interlayer insulating layer having first and second penetrating holes is formed to cover the entire substrate. A capacitor has lower and upper electrode and a dielectric located between these electrodes. The lower electrode is electrically connected to the first element through the first penetrating hole. Each of the peripheral circuits has a second element, a contact pad electrically connected to the second element, a pad insulating layer formed to cover the contact pad, a pad protection layer formed on the pad insulating layer, and an interconnection conductor electrically connected to the contact pad through a contact hole penetrating the pad protection and pad insulating layers.

Abstract: The present invention provides a polycrystalline silicon conducting structure (e.g., a resistor) whose resistance value is controlled, and can be less variable and less dependent on temperature with respect to any resistant value, and a process of producing the same. Use is made of at least a two-layer structure including a first polycrystalline silicon layer of large crystal grain size and a second polycrystalline silicon layer of small crystal grain size, and the first polycrystalline silicon layer has a positive temperature dependence of resistance while the second polycrystalline layer has a negative temperature dependence of resistance, or vice versa. Moreover, the polycrystalline silicon layer of large grain size can be formed by high dose ion implantation and annealing, or by depositing the layers by chemical vapor deposition at different temperatures so as to form large-grain and small-grain layers.

Abstract: The dynamic range is increased and the noise level is reduced in a bipolar-based active pixel sensor cell with a capacitively coupled base region by forming the capacitor over a portion of the base region and the field oxide region of the cell. In addition, the noise levels are also reduced by heavily-doping the material which forms a portion of the bottom plate of the capacitor with the same conductivity type as the base region of the cell, and by placing the material which forms the portion of the bottom plate in direct contact with the base region.

Abstract: A three-dimensional polysilicon capacitor for use within integrated circuits and a method by which the three-dimensional polysilicon capacitor is formed. Formed upon a semiconductor substrate is a first polysilicon layer which has a series of apertures formed at least partially through the first polysilicon layer. A conformal insulator layer is then formed upon the first polysilicon layer and into the apertures within the first polysilicon layer. The conformal insulator layer has a series of apertures corresponding to the series of apertures within the first polysilicon layer. A second polysilicon layer is then formed upon the surface of the conformal insulator layer and filling the apertures within the conformal insulator layer. Optionally, the first polysilicon layer may be formed from a multi-coating stack comprising two polysilicon coatings separated by an metal silicide etch stop layer.

Abstract: On a p.sup.+ diffused region which is to be a lower electrode of a capacitor, a silicon nitride film which is a capacitor insulating layer is formed. An upper electrode is formed on this silicon nitride film. The upper electrode has a non-doped polycrystalline silicon film and a silicide layer. Non-doped polycrystalline silicon film is formed in contact with silicon nitride film. Silicide layer is formed on a surface of non-doped polycrystalline silicon film. Thus, a capacitor structure is obtained in which a larger capacitance and a higher breakdown voltage can be assured, so that it would not operate inaccurately even when it is integrated to a higher degree.

Abstract: A bonding pad adapted for use with an Aluminum wire that resists stresses that would otherwise peel the pad from the substrate. The pad has a polysilicon layer adhered to an insulating layer on a semiconductor substrate, a overlying refractory metal polycide layer, a second polysilicon layer, a refractory metal layer, and a thick Aluminum alloy bonding pad.

Abstract: A triple-poly process forms a static random access memory (SRAM) which has a compact four-transistor SRAM cell layout. The cell layout divides structures among the three layers of polysilicon to reduce the area required for each cell. Additionally, a contact between a pull-up resistor formed in an upper polysilicon layer forms a "strapping" via which cross-couples a gate region and a drain region underlying the strapping via. Pull-up resistors extend across boundaries of cell areas to increase the length and resistance of the pull-up resistors.

Abstract: In a semiconductor device including a semiconductor substrate, an impurity doped region formed in the semiconductor substrate, an insulating layer formed on the semiconductor substrate and having an opening leading to the impurity doped region, a polycrystalline silicon layer formed on the insulating layer and the impurity doped region, and a metal silicide layer formed on the polycrystalline silicon layer, a transverse thickness of the polycrystalline silicon layer at a sidewall of the insulating layer is larger than a longitudinal thickness of the polycrystalline silicon layer at a bottom of the opening and at a surface of the insulating layer.

Abstract: A semiconductor processing method includes: a) providing a substrate having a base region to which electrical connection is to be made; b) providing a first layer of a conductive first material; c) providing an etch stop layer over the first layer; d) etching a contact opening through the etch stop and first layers to the base region; e) providing a second layer of first material outwardly of the etch stop layer and within the contact opening to a thickness greater than the first layer thickness and extending outwardly beyond the contact opening upper edge; f) removing first material of the second layer and defining a second layer plug within the contact, the second layer plug having an outermost surface extending outwardly beyond the contact opening upper edge and thereby providing the second layer plug to be of greater thickness than the first layer; g) masking outwardly of the first layer and the second layer plug to define a mask pattern for definition of a circuit component from the first layer which con

Abstract: V-shaped contact buffer layers of polycrystalline silicon are disposed between ring-shaped gate electrodes of thin-film polycrystalline silicon of amplifying pixel transistors and vertical scanning lines. The contact buffer layers and the ring-shaped gate electrodes are connected to each other by contacts, and the contact buffer layers and the vertical scanning lines are connected to each other by contacts which are positionally displaced from the above contacts. The channel length of the ring-shaped gates is rendered constant in all areas, and a potential shift is prevented from occurring in gate contacts for thereby avoiding operation characteristic degradations of the pixel transistors.

Abstract: A method for fabricating buried metal plug structures for multi-polysilicon layer interconnects and for concurrently making metal plugs on semiconductor integrated circuits, such as DRAM and SRAM, was achieved. The method involved forming contact opening in an insulating layer over opening in a patterned polysilicon layer. The opening in the polysilicon layer aligned over source/drain contact areas on the substrate and providing a means for forming self-aligned contact openings. Buried metal plugs in the contact openings form interconnects between the polysilicon layer and the source/drains. And, by merging the process steps, concurrently forming metal plug interconnects for contacts to semiconductor devices and first level metal. The process is applicable to the formation of bit line contacts on DRAM and SRAM circuits and simultaneously form the peripheral contact on the chip.

Abstract: Reduced area metal contacts to a thin polysilicon layer contact structure having low ohmic resistance was achieved. The structure involves forming contact openings in an insulating layer over a buffer layer composed of a thick polysilicon layer. A portion of the sidewall in the opening includes a patterned thin polysilicon layer that forms part of a semiconductor device and also forms the electrical connection to the metal contact. The structure provides metal contacts having very low resistance and reduced area for increased device packing densities. The metal contact structure also eliminates the problem of forming P.sup.+ /N.sup.+ non-ohmic junctions usually associated with making P.sup.+ /N.sup.+ stacked contact. The structure further allows process steps to be used that provide larger latitude in etching the contact opening and thereby provides a structure that is very manufacturable.

Abstract: A lower-level conductor layer is formed in a surface of, on or over a semiconductor substrate. An interlayer insulator film is formed on the lower-level conductor layer. An upper-level conductor layer such as an interconnection layer of the semiconductor device is formed on the interlayer insulator film. A conductor plug is formed in a contact hole of the interlayer insulator film. The lower-level conductor layer and the upper-level conductor layer are electrically connected with each other through the conductor plug. A top part of the conductor plug protrudes from the interlayer insulator film. The upper-level conductor layer is contacted with a top face and a side face of the top part of the conductor plug. Both the contact resistance between the conductor contact and the upper-level conductor layer and the resistance of the upper-level conductor layer itself can be reduced without using a special equipment and a special process.

Abstract: SRAM memory cells is provided with high resistance to soft error and no parasitic capacitance due to PN junction.SRAM memory cells comprises the load resister is a thin film transistor having a same conductive type as that of the driver transistor.

Abstract: A method for forming a semiconductor device includes forming insulated gate regions (122,222) on a substrate (26) using a first photo-masking step, forming a base region (47) through an opening (143) between the insulated gate regions (122,222), and forming a source region (152) within the base region (47). Next, a protective layer (61) is formed and selectively patterned using a second photo-masking step to form an opening (62) within the first opening (143) and an opening (63) above one of the insulated gate regions (122). Next, a portion (66) of the substrate (26) and a portion (67) of the insulated gate region (122) are removed. Ohmic contacts (74,76) are then formed and patterned using a third photo-masking step. Additionally, a termination structure (81) is described.

Abstract: For the global planarization of a semiconductor circuit or a micromechanical component with a step between a higher-lying region and a lower-lying region, the regions being large in area, it is envisaged to deposit a first layer (50), remove it again in the higher-lying region apart from a rib (50), deposit a second layer (51) and then, in a CMP step, planarize the entire arrangement.

Abstract: In an insulated gate field effect semiconductor device, the gate electrode formed on the gate insulating film includes the first and second semiconductor layers as a double layer. An impurity for providing one conductivity type is not contained in first semiconductor layer which is in contact with a gate insulating film and is contained at a high concentration in the second semiconductor layer which is not in contact with the gate insulating film. Accordingly, By existence of the first semiconductor layer is which the impurity is not doped, the impurity is prevented from penetrating through the gate insulating film from the gate electrode and diffusing into the channel forming region. Also, by existence of the second semiconductor layer in which high concentration impurity is doped, the gate electrode has low resistance.

Abstract: Stringers and depth of focus problems in substrates having above-surface isolation schemes are avoided by applying a first portion of a gate conductor over the entire surface having above-surface isolation, selectively removing the gate conductor from above the isolation features of the above-surface isolation, and overcoating the entire surface with a second portion of gate conductor. The process has particular application to substrates that employ regions having field-shield isolation. An important feature of the invention is drawn to creating structures wherein gate conductor is applied to a substrate including both above-surface and below-surface isolation regions in a manner which leaves the gate conductor planarized over both the above-surface and below-surface regions.

Abstract: A saddled and wrapped stack capacitor DRAM and a method thereof are provided. The DRAM of the invention includes three factors in increasing the effective area for a capacitor. One is a storage poly layer comprising a first poly layer and a second poly layer, which is formed thick in a region over a field oxide layer through two steps; another is a spacer which is formed through an etchback technique for an oxide layer coated on another oxide layer being patterened to selectively remove the storage poly layer, and the spacer maximizes the size of the storage poly; another is an undercut which is formed in boundary regions on an upper oxide layer, on which a .?.plat.!. .Iadd.plate .Iaddend.poly material is coated and wrapped.