Abstract: A semiconductor device comprises a first conductive layer, an insulating layer formed on the first conductive layer, a plurality of contact holes formed through the insulating layer, a second conductive layer consisting of a plurality of pillar-shaped contacts each respectively formed in a corresponding one of the contact holes, the pillar-shaped contacts each respectively having a projecting portion projecting above the insulating layer, and a third conductive layer consisting of a plurality of conductive portions each respectively formed on the projecting portion of a corresponding one of the pillar-shaped contacts in a selectively growing manner.

Abstract: The present invention is directed to providing an electrostatic discharge ("ESD") protection cell for use in an integrated circuit device including antifuses. The ESD protection cell is formed simultaneously with the antifuses that it protects and provides protection from ESD during the fabrication of the antifuses. The concept is to use thin undoped or doped polysilicon on top of antifuse material as a block etching mask for the formation of the ESD protection cells by using common etching techniques. This polysilicon mask is placed where the antifuses will be and not where the ESD protection cells will be. The polysilicon mask is then merged with a top polysilicon electrode during later processing. During the block etching process, the antifuse material layer is compromised in the region about the ESD protection cells.

Abstract: An SRAM semiconductor device comprises a first layer, a second layer and a third layer of polysilicon are separated by dielectric layers formed on a substrate, and a split gate structure with transistors formed in different polysilicon levels. Preferably, the split gate structure includes pull down transistors and pass gate transistors formed in different polysilicon levels; the second polysilicon layer extends into contact with the substrate; the second polysilicon layer contacts the third polysilicon layer in an interconnection region; and the third polysilicon layer comprises a polysilicon load resistor.

Abstract: A field effect transistor comprises a semiconductor substrate having a main surface and a predetermined impurity concentration of a first conductivity type, impurity layers of a second conductivity type formed spaced apart at the main surface of the semiconductor substrate, and a shaped conductive layer serving as a gate electrode. The impurity layers constitute source.multidot.drain regions, and a region between the impurity layers defines a channel region in the main surface. The shaped conductive layer is formed on the channel region with an insulating film therebetween. The shaped conductive layer has an upper portion and a lower portion wherein the upper portion is longer than the lower portion and the length of the lower portion adjacent the insulating film is substantially equal to or shorter than the length of the channel region at the main surface. Additionally, the upper and lower portions of the shaped conductive layer are formed of the same base composition.

Abstract: A semiconductor integrated circuit device has upper wirings extending on an inter-level insulating layer covering a lower wiring at spacing with zig-zag side surfaces between the upper wirings, and the zig-zag lines are transferred to the inter-level insulating layer so as to prevent the upper wirings from short circuit due to a residue of conductive material for the upper wirings.

Abstract: V-shaped contact buffer layers of polycrystalline silicon are disposed between ring-shaped gate electrodes of thin-film polycrystalline silicon of amplifying pixel transistors and vertical scanning lines. The contact buffer layers and the ring-shaped gate electrodes are connected to each other by contacts, and the contact buffer layers and the vertical scanning lines are connected to each other by contacts which are positionally displaced from the above contacts. The channel length of the ring-shaped gates is rendered constant in all areas, and a potential shift is prevented from occurring in gate contacts for thereby avoiding operation characteristic degradations of the pixel transistors.

Abstract: A bipolar transistor with a structure such that it is possible to reduce the parasitic capacity without sacrificing improvements in cut-off frequency f.sub.T, in which a P.sup.+ -type polycrystalline silicon film 122A is provided on the side wall of an opening 143A which is provided in a silicon nitride film 152A serving as the middle layer of a laminated insulation film 107A, and, a P-type single crystal silicon layer 121A constituting the intrinsic base region is connected to a P.sup.+ -type polycrystalline silicon film 111 which is a base drawing electrode via a thin P.sup.+ -type polycrystalline silicon film 123A.

Abstract: A polycrystalline silicon layer is deposited and patterned to define a level of interconnect. Contact opening to lower conductive layers are then defined and patterned. A refractory metal such as tungsten is selectively deposited over the device, so that it adheres to the polycrystalline silicon in the interconnect leads and silicon of the lower conductive layer which is exposed in the contact openings. This provides a low resistance interconnect, and good, metal, contacts to underlying layers. Shared contacts between two or more polycrystalline silicon interconnect layers and in underlying conductive layers such as a substrate are easily formed using this technique.

Abstract: An interconnect structure, and method for forming same, is suitable for use in integrated circuits such as SRAM devices. The structure uses masking of a polycrystalline silicon interconnect level to move a P-N junction to a region within a polycrystalline silicon interconnect line, rather than at the substrate. This P-N junction can then be shorted out using a refractory metal silicide formed on the polycrystalline silicon interconnect structure.

Abstract: A silicon layer in a lower layer and an interconnection layer arranged in an upper layer are electrically connected through an opening for contact. A silicon plug layer having the same conductivity type as that of the silicon layer is embedded in the opening. The silicon plug layer is embedded in the opening by an etch back method after deposited using a CVD method. The interconnection layer in the upper layer has conductivity type different from that of the silicon plug layer. A refractory metal silicide layer is formed between the upper interconnection layer and the silicon plug layer.The refractory metal silicide layer prevents pn junction from being formed between the upper interconnection layer and the silicon plug layer.

Abstract: A field effect transistor comprises a semiconductor substrate having a main surface and a predetermined impurity concentration of a first conductivity type, impurity layers of a second conductivity type formed spaced apart at the main surface of the semiconductor substrate, and a shaped conductive layer serving as a gate electrode. The impurity layers constitute source.drain regions, and a region between the impurity layers defines a channel region in the main surface. The shaped conductive layer is formed on the channel region with an insulating film therebetween. The shaped conductive layer has an upper portion and a lower portion wherein the upper portion is longer than the lower portion and the length of the lower portion adjacent the insulating film is substantially equal to or shorter than the length of the channel region at the main surface. Additionally, the upper and lower portions of the shaped conductive layer are formed of the same base composition.

Abstract: A self-aligned via between interconnect layers in an integrated circuit allows a less precise masking alignment to be used to fabricate an integrated circuit with increased packing density and improved yield. In one embodiment, self-aligned vias are used to connect first and second interconnect layers in an SRAM memory cell.

Abstract: In forming an electrode 2 on a silicon 6 oxide film 5 on a semiconductor substrate 4 through a silicon oxide film 5, for example, the gate electrode 2 is structured in a laminated structure of a plurality of polycrystalline silicon layers 6. The portion of the gate electrode 2 is formed by a method of manufacturing a thin film having a process of depositing amorphous layers and a process of crystallizing (recrystallizing) this amorphous material.

Abstract: A lower electrode of a capacitor for use in a semiconductor device includes a first semiconductor layer having a predetermined impurity concentration and a second semiconductor layer having an impurity concentration higher than that of the first semiconductor layer. As a result, intensification of an electric field at an end portion of the capacitor can be reduced. In addition, a word line is formed of a buffer layer and a main conductor layer to reduce a parasitic capacitance between the lower electrode of the capacitor and the word line.

Abstract: A method is provided for forming a polysilicon buried contact of an integrated circuit, and an integrated circuit formed according to the same. A field oxide region is formed over a portion of a substrate leaving an exposed active region. An oxide layer is formed over the active region. A first photoresist layer is formed and patterned over the first silicon layer. The first silicon layer is then etched to form an opening therethrough to expose a portion of the oxide layer. The oxide layer is etched through the opening to expose a portion of the substrate. a conductive etch stop layer is formed over the exposed portion of the substrate and the first photoresist layer. The first photoresist layer and the etch stop layer overlying the first photoresist layer are then removed. A second silicon layer is formed over the first silicon layer and the remaining etch stop layer. A second photoresist layer is formed and patterned over the second silicon layer.

Abstract: A semiconductor memory of the invention includes a semiconductor substrate having a plurality of transistors, a plurality of stacked capacitors connected to portions of the plurality of transistors, a plurality of first level interconnection layers connected to other portions of the plurality of transistors, and a plurality of second level interconnection layers disposed above the stacked capacitors and the first level interconnection layers. Each of the plurality of stacked capacitors includes a first electrode layer, a capacitance insulating film formed on top of the first electrode layer, and a second electrode layer formed on top of the capacitance insulating film. The second electrode layer is connected to a portion of one of the plurality of second level interconnection layers. At least portions of the plurality of first level interconnection layers are connected to other portions of the plurality of second level interconnection layers.

Abstract: In a semiconductor device of gate self-alignment structure, at least two lamination layer portions each composed of a gate electrode, an insulating film and a conductive film are formed on a semiconductor substrate with a contact hole sandwiched therebetween. A wire is formed on the respective lamination layer portions. Further, a total thickness of the conductive film and the wire is determined to be large enough to prevent impurities implanted into the wire from being doped into the gate electrode. In formation of the gate self-alignment structure, an insulating side wall is formed on the side wall of the contact hole, to insulate the gate electrode from the wire or vice versa.

Abstract: Provided is a semiconductor memory device wherein nonvolatile memory elements are arranged in a matrix configuration, each of the memory elements having a field effect transistor including a floating gate, an interlayer insulating film and a control gate electrode which are stacked on an insulating film covering a semiconductor substrate, and a source region and a drain region which are respectively formed in the semiconductor substrate on both sides of the gate electrode, the floating gate, interlayer insulating film and control gate electrode being formed in a recess provided in the semiconductor substrate. The semiconductor device of such a structure is reduced in size and highly integrated with its high-performance characteristics maintained.

Abstract: A semiconductor device and a method of manufacturing a semiconductor device includes the steps of forming a first conductivity type layer on one surface of a work piece comprising a semiconductor substrate. A gate oxide is formed on the surface of the substrate. A first conductive structure is formed on the gate oxide consisting essentially of polysilicon. An insulating structure is formed in contact with the first conductive structure. Material is removed from the surface of the first conductive structure to expose at least a portion of the surface of the first layer, and to form on the remaining structure on the workpiece a second conductive structure consisting essentially of polysilicon. The polysilicon is in electrical contact with the first conductive structure. Thus, a compound conductive structure is provided on the work piece.

Abstract: A semiconductor device without erroneous operation and deterioration of characteristics in a transistor even when an impurity region is formed in self-alignment by ion implantation using a gate electrode as a mask, and a method of manufacturing thereof are disclosed. This semiconductor device includes a gate electrode formed of a polycrystal silicon layer 4b having the crystal orientation of the crystal grains arranged in a definite orientation. By implanting ions at a predetermined angle with respect to the crystallographic axis of the crystal grains of the polycrystal silicon layer 4b in forming a p.sup.+ impurity region 5 by ion implantation using the gate electrode as a mask, the channeling phenomenon where ions pass through the gate electrode is prevented. Therefore, generation of erroneous operation and deterioration of characteristics in a transistor are prevented in forming an impurity region in self-alignment by ion implantation using the gate electrode as a mask.

Abstract: A saddled and wrapped stack capacitor DRAM and a method thereof are provided. The DRAM of the invention includes three factors in increasing the effective area for a capacitor. One is a storage poly layer comprising a first poly layer and a second poly layer, which is formed thick in a region over a field oxide layer through two steps; another is a spacer which is formed through an etchback technique for an oxide layer coated on another oxide layer being patterened to selectively remove the storage poly layer, and the spacer maximizes the size of the storage poly; another is an undercut which is formed in boundary regions on an upper oxide layer, on which a plat poly material is coated and wrapped.

Abstract: A grid-like arrangement of membranes of doped polysilicon are mounted on a substrate but are electrically insulated therefrom each membrane extends over a cavity and is joined to the substrate at at least two supporting locations so that they cavity lies between the membrane and the substrate. Changes in an electrical quantity existing between the membranes and the substrate are measured as forces exerted on the grid-like arrangement of sensor elements so that the ridges in the skin on a finger tip may be sensed for detecting a fingerprint.

Abstract: A semiconductor device is provided which includes a conductive layer, an insulating film formed on the surface of the conductive layer, and a conductive metal interconnection layer formed on the insulating film and electrically connected to the conductive layer through a contact hole formed in a predetermined position of the insulating film. The conductive metal interconnection and the surface of the conductive layer are directly joined together and a silicon layer including a single crystal or polycrystalline silicon having a grain size of at least about 10 .mu.m is interposed between the conductive metal interconnection layer and the insulating film. The conductive metal interconnection layer becomes a single crystal or a polycrystal having a grain size of about 10 .mu.m or above under the influence of the crystalline properties of the underlying crystal of the silicon layer.

Abstract: A field effect transistor includes a polycrystalline silicon gate having a semiconductor junction therein. The semiconductor junction is formed of first and second oppositely doped polycrystalline silicon layers, and extends parallel to the substrate face. The polycrystalline silicon gate including the semiconductor junction therein is perfectly formed by implanting ions into the top of the polycrystalline silicon gate simultaneous with implantation of the source and drain regions. The semiconductor junction thus formed does not adversely impact the performance of the field effect transistor, and provides a low resistance ohmic gate contact. The gate need not be masked during source and drain implant, resulting in simplified fabrication.

Abstract: Low resistance contacts for establishing an electrical pathway to an integrated surface substrate are provided. The pathway is formed by the connection of a p+ doped channel stop region with a p+ doped extrinsic layer. P+ doped polysilicon contacts are positioned on the substrate surface. In one embodiment, a metal silicide layer connects the polysilicon contacts and overlies the p+ doped extrinsic layer.

Abstract: A process is used to fabricate diodes having an emitter contacted p-n junction. A stack of n.sup.+ -type polysilicon layers are formed one upon the other upon a p-type silicon substrate. In an accordingly fabricated diode, native oxide layers that forms between the n.sup.+ -type polysilicon layer and the p-type substrate would be liable to be broken up, and thicker epitaxial layer would be formed between the same. The p-n junction is with a thickness of 0.05-0.2 .mu.m. As the diode is reverse-biased, for example at -5V, leakage current could be less than 1 n.ANG./cm.sup.2. The reverse-bias breakdown voltage could be larger than -100 V. When forward-biased, the ideality factor of the diode is close to unity.

Abstract: A thin first insulating oxide film is formed on a semiconductor substrate. A thick second insulating oxide film is formed on a semiconductor substrate. A first polysilicon resistance film is formed on the first insulating oxide film. A second polysilicon resistance film is formed on the second insulating oxide film. An insulating protection film, which contains a large amount of hydrogen ion and covers the first polysilicon resistance film, second polysilicon resistance film, first electrode and second electrode, is formed on the semiconductor substrate. A hydrogen ion intercepting film, which prevents passage of hydrogen ion, is interposed between the first insulating oxide film and the first polysilicon resistance film and between the second insulating oxide film and second polysilicon resistance film.

Abstract: A lateral bipolar transistor and method of making which is compatible with making BICMOS circuits are disclosed. The method includes: Forming on a substrate of one conductivity type at least one layer of a semiconductor material of opposite conductivity type. Forming a first region of opposite conductivity type into one portion of the layer and a highly conductive contact region to the layer in another portion, forming a layer of an insulating material over the layer and providing an aperture therethrough to the first region. Depositing a layer of polycrystalline silicon over the insulating layer and in the aperture so that it is in the aperture and extends a short distance beyond the aperture but not beyond the edge of the first region.

Abstract: A bipolar transistor and a diode are incorporated in a semiconductor integrated circuit device, and an emitter electrode is constituted by lower and upper doped polysilicon films sandwiching an oxygen-leakage film which tunnels minority carriers of the base therethrough at higher probability than the majority carriers so as to enhance the emitter injection efficiency, thereby allowing a designer to increase the base width and the distance from the p-n junction between the anode and the cathode for improving the breakdown voltage of the diode without sacrifice of the current amplification factor.

Abstract: An antifuse memory cell having a P.sup.+ polysilicon doping in a region directly under an intrinsic silicon programming layer. The P.sup.+ polysilicon region is surrounded by an N.sup.- polysilicon doped region, and the two regions are sandwiched between layers of silicon dioxide insulation. The interface between the two regions is a P-N junction, in fact, a diode. The diode does not suffer from a diffusion current that increases with increasing levels of N.sup.- doping, therefore the N.sup.- polysilicon can be heavily doped to yield a very conductive bit line interconnect for a memory matrix. The interconnect line widths can be very narrow, and further microminiaturization is aided thereby. The top metalization is aluminum and serves as a word line interconnect in the memory matrix.

Abstract: A is a heat-resisting ohmic electrode on diamond film, including: a p-type semiconducting diamond film; a boron-doped diamond layer provided on the semiconducting diamond film; and an electrode element made of p-type Si selectively formed on the boron-doped diamond layer; wherein the boron concentration in the boron-doped diamond layer is from 1.0.times.10.sup.19 to 1.8.times.10.sup.23 cm.sup.-3, and at least one impurity selected from the group consisting of B, Al and Ga is doped in the electrode element with a concentration from 1.0.times.10.sup.20 to 5.0.times.10.sup.22 cm.sup.-3. The ohmic electrode on diamond film is applicable for electronic devices operative at high temperature.

Abstract: A submicron channel length is achieved in cells having sharp corners, such as square cells, by blunting the corners of the cells. In this way, the three dimensional diffusion effect is minimized, and punch through is avoided. Techniques are discussed for minimizing defects in the shallow junctions used for forming the short channel, including the use of a thin dry oxide rather than a thicker steam thermal over the body contact area, a field shaping p+ diffusion to enhance breakdown voltage, and TCA gathering. Gate-source leakage is reduced with extrinsic gathering on the poly backside, and intrinsic gathering due to the choice of starting material. Five masking step and six masking step processes are also disclosed for manufacturing a power MOSFET structure. This power MOSFET structure has an active region with a plurality of active cells as well as a termination region with a field ring or a row of inactive cells and a polysilicon field plate.

Abstract: A silicon-on-insulator lateral bipolar transistor having an edge-strapped base contact is disclosed. A thin layer of oxide is deposited on a silicon-on-insulator structure and a layer of polysilicon is deposited on the thin oxide layer that is patterned and etched to form an extrinsic base region of the transistor. The polysilicon extrinsic base is very heavily doped and the thin oxide layer acts as both a diffusion stop and an etch stop during the formation of the extrinsic base. A silicon edge contact region is formed of selective epitaxy or polysilicon to connect the extrinsic base to the intrinsic base formed in the silicon-on-insulator layer.

Abstract: A semiconducting wafer has an active area and first and second field oxide regions adjacent opposite sides of the active area. A first poly layer is deposited to form a first landing pad member electrically contacting the active area and overlapping the first field oxide region. Then an insulating oxide layer is deposited, followed by a second poly layer to form a second landing pad member overlapping the first landing pad member and the second field oxide region. A contact etch is performed with the landing pad members acting as an etch stop. A contact is deposited to electrically contact the landing pad members.

Abstract: A MOS semiconductor device with a double-layer gate electrode structure includes a silicon substrate and a field oxide layer which is selectively formed on one major surface of the substrate in such a manner as to surround an active region. A first silicon oxide layer is deposited in a region of a gate electrode of the semiconductor device. A polycrystalline silicon layer is provided on the first silicon layer and in a portion which extends from the region of the gate electrode to above the field oxide layer. Source and drain diffusion regions are defined in a part of the active region of the major surface of the substrate. An impurity-doped second silicon oxide layer is deposited on the entire surface of a laminate which is constituted by the substrate to the source and drain diffusion regions except for the surface of that portion of the polycrystalline silicon layer which overlies the field oxide layer.

Abstract: An interconnection structure of a semiconductor device for electrically connecting a thin conductive layer and a metallization and the fabrication method thereof are disclosed. The interconnection structure includes a semiconductor substrate, an insulating layer coated on the substrate, a thick conductive layer formed on a certain portion of the insulating layer, a first interlaid insulating layer covering the thick conductive layer, a first contact hole formed within the first interlaid insulating layer on the thick conductive layer, a thin conductive layer consisting of vertical structure formed in the first contact hole and horizontal structure formed on the first interlaid insulating layer, a second interlaid insulating layer covering the thin conductive layer, a second contact hole formed within said first and second interlaid insulating layers and crossing the first contact hole, and a metallization filling the second contact hole and formed on the second interlaid insulating layer.

Abstract: A semiconductor device is disclosed that can form contacts with ease even if the distance between adjacent gate electrodes is reduced in accordance with larger scale integration of semiconductor devices. The semiconductor device includes a polysilicon pad 8c connected to impurity implanted layers 5a and 7a, formed over sidewalls 6a and 6b of gate electrodes 3a and 3b and insulating films 4a and 4b; and a polysilicon pad 11a connected to impurity implanted layers 5b and 7b, formed over polysilicon pad 8c with an insulating film 9 and sidewalls 10b therebetween. Even if elements are miniaturized to have reduced gate electrode length and gate electrode distance in accordance with larger scale integration of a semiconductor device, polysilicon pads 8c and 11a can be formed with ease between impurity implanted layers 5a, 7a and an upper layer wiring 13a, and between impurity implanted layers 5b, 7b and an upper layer wiring 13b, respectively.

Abstract: The present invention relates to a semiconductor device used as a gate electrode or interconnection, in which a polysilicon layer in a laminate comprising a polysilicon layer doped with an impurity and a refractory metal silicide layer has an impurity concentration that is reduced close to a boundary between the polysilicon layer and the refractory metal silicide layer. With this structure, the difference in oxidation speed between the polysilicon layer and the silicide layer is smaller in comparison with a conventional structure, and thus peeling due to bird's beaks can be prevented. The semiconductor device of this structure can be realized by a two-layer polysilicon structure in which the upper layer in contact with the refractory metal silicide layer has a lower impurity concentration, or by a structure in which the peak of the impurity concentration profile is set to be deep within the polysilicon layer during ion implantation.

Abstract: A semiconductor device having multi-layered leads having a first lead portion including a polycrystalline silicon layer and a titanium silicide layer, and a second lead portion formed over the first lead portion and made up of a polycrystalline silicon layer. An intermediate insulating layer is provided between the first and second lead portions. The intermediate insulation layer and the underlying titanium silicide layer are provided with contact holes aligned with each other so as to allow the polycrystalline silicon of the second lead portion to be in direct contact with the polycrystalline silicon layer of the first lead portion without interposing therebetween the titanium silicide layer at the contact hole portion.

Abstract: A semiconductor memory has many memory cells each comprising a transistor and a capacitor. In each memory cell, one of the source and drain regions of the transistor is connected to a bit line. The bit line is formed above the transistor. The capacitor comprises a first capacitor electrode formed on a substrate and a second capacitor electrode formed on an insulation film coated on the surface of the first capacitor electrode. The first capacitor electrode is connected to the other of the source and drain regions of the transistor. The first capacitor electrode is formed above the bit line.To manufacture such a semiconductor memory, each memory cell region is separately formed on the surface of a substrate. A gate insulation film is formed on the memory cell region. A gate electrode is formed on the gate insulation film. The gate electrode is used as a mask to dope the substrate with impurities to form source and drain regions of a transistor.

Abstract: A semiconductor integrated circuit device having a structure in which each of the following regions, that is, a first region for forming the base and emitter regions of each of the bipolar transistors, a second region for forming the collector lead-out region of the bipolar transistor, and a third region for forming each of the MISFETs, is projected from the main surface of a semiconductor substrate, whereby it is possible to effect isolation between the MISFETs and between these MISFETs and the bipolar transistors with the same isolation structure and in the same manufacturing step as those for the isolation between the bipolar transistors. In this device, furthermore, the base region of the bipolar transistor is electrically and self-alignedly connected to a base electrode which is formed over the main surface so as to surround the emitter region.

Abstract: A buried contact between the gate of a transistor device formed at the surface of a semiconductor substrate and a diffusion region formed in the surface of the substrate remote from the transistor device. The buried contact includes a polysilicon interconnect structure formed after shaping of the gate layer and the gate insulator. The polysilicon interconnect structure engages a side edge and an adjoining lower surface of the gate layer at a location where the gate insulator has been removed by isotropic etching from between the gate layer and the surface of the substrate. The polysilicon interconnect layer also contacts the surface of the substrate beneath an overhanging edge of the gate layer so as to form a surface current pathway interface. Below the surface current pathway interface a migration region is formed by heat-induced movement of ions from the gate layer through the polysilicon interconnect structure.

Abstract: A memory cell layout achieves a reduced cell area. In one embodiment, a six transitor (6T) SRAM cell has two vertical thin-film transistors (18 and 20) as load transistors, two transfer transistors (10 and 12), two latch transistors (14 and 16), and two storage nodes. NODE 1 and NODE 2 of the cell each have a minimum feature defined by trenches (60). Four of five interconnects associated with each node are located within the respective trench. For example in NODE 1, a drain of latch transistor (14), a gate of latch transistor (16), a drain of load transistor (18), and a current electrode of transfer transistor (10) are electrically coupled within or beneath one trench (60). A remaining interconnection of NODE 1, a gate of load transistor 20, is located within the trench associated with NODE 2. Thus, ten interconnects of the memory cell are contained within areas defined by two minimum features.

Abstract: A semiconductor device of a MOS structure having a p-type gate electrode has a gate electrode including at least two layers consisting of a boron-doped polysilicon layer and a polysilicon layer doped with boron and an inert material. This inert material is nitrogen or carbon.