Abstract: A bonding pad design, comprising: a substrate; a lower series of metal pads upon the substrate; and an intermediate series of metal pads over the lower series of metal pads. The lower series of metal pads and the intermediate series of metal pads being connected by a respective series of intermediate interconnects and each series of intermediate metal pads being interlocked by a respective series of extensions.

Abstract: An image sensor has a vertically integrated thin-film photodiode.

Abstract: A method for forming contact holes using a multi-layer hard mask. A substrate with a device region and an alignment region having an opening therein to serve as an alignment mark is provided. A dielectric layer is formed overlying the substrate and fills the opening, followed by the multi-layer hard mask. The multi-layer hard mask over the opening is partially removed and that on the device region is patterned to form a plurality of holes therein and expose the underlying dielectric layer. The exposed dielectric layer on the device region is etched to form the plurality of contact holes therein.

Abstract: A fabrication method for an integrated device having a capacitor in an interconnect system is described. At least a first exposed metal line and a second metal line are provided in an insulating layer. A stack layer is deposited and patterned to form a film stack structure over the second metal line. An inter-metal dielectric layer is formed over the film stack structure, the first metal line and the insulating layer. At least a first dual damascene interconnect and a second dual damascene interconnect are formed over and in contact with the first metal line and the film stack structure, respectively.

Abstract: This specification relates to a process for manufacturing a semiconductor device, comprising the steps of: forming a lower gate electrode film on a semiconductor substrate 10 via a gate insulating film 11; forming an upper gate electrode film on the lower gate electrode film, the upper gate electrode film being made of a material having a lower oxidation rate than that of the lower gate electrode film; forming a gate electrode 12 by patterning the upper gate electrode film and the lower gate electrode film, the gate electrode 12 comprising a lower gate electrode element 12a and an upper gate electrode element 12b; forming source/drain regions 15 by introducing an impurity into the semiconductor substrate 10; and forming oxide film sidewalls 13 by oxidizing the side faces of the lower gate electrode element 12a and the upper gate electrode element 12b, the thickness of the oxide film sidewalls 13 in the gate length direction being larger at the sides of the lower gate electrode element 12a than at the sides of

Abstract: An inductance integrated in a monolithic circuit, including a conductive spiral having an internal end connected to a connection track, the spiral and the connection track belonging to a same metallization level, in which the connection between the internal end of the spiral and the connection track is formed by a connecting track belonging to a metallization level higher than the metallization level of the spiral.

Abstract: A PIN active pixel sensor array including self aligned encapsulated electrodes and a method for forming the same the method including forming an electrically conductive layer over a substrate; forming a first doped semiconductor layer over the conductive layer; photolithographically patterning and etching through a thickness portion of the first doped semiconductor layer and conductive layer to expose the substrate to form a plurality of spaced apart electrodes having an upper portion comprising the first doped semiconductor layer; blanket depositing a second doped semiconductor layer to cover the spaced apart electrodes including the exposed substrate; and, etching through at least a thickness portion of the second doped semiconductor layer.

Abstract: The invention provides overlapping row decode in a multiport memory. Overlapping row decode includes predecode wires positioned on a first metallization layer and configured to address wordline drivers of a first port. A second plurality of predecode wires is located on a third metallization layer and configured to address wordline drivers of a second port. The overlapping row decode includes a plurality of wordline connections that are formed on a second metallization layer between the first metallization layer and the third metallization layer. The wordline connections include a first and second portion. The first portion communicates with the first plurality of predecode wires and the wordline drivers of the first port. The second portion communicates with the second plurality of predecode wires and the wordline drivers of the second port.

Abstract: Defect-free dielectric coatings comprised of porous polymeric matrices are prepared using nitrogen-containing polymers as pore-generating agents. The dielectric coatings are useful in a number of contexts, including the manufacture of electronic devices such as integrated circuit devices and integrated circuit packaging devices. The dielectric coatings are prepared by admixing, in a solvent, a polymeric nitrogenous porogen with a high temperature, thermosetting host polymer miscible therewith, coating a substrate surface with the admixture, heating the uncured coating to cure the host polymer and provide a vitrified, two-phase matrix, and then decomposing the porogen. The dielectric coatings so prepared have few if any defects, and depending on the amount and molecular weight of porogen used, can be prepared so as to have an exceptionally low dielectric constant on the order of 2.5 or less, preferably less than about 2.0.

Abstract: A semiconductor device has a semiconductor substrate and a conductive layer formed above the semiconductor substrate. The conductive layer has a silicon film, a silicide film formed on the silicon film, and a high melting-point metal film formed on the silicide film. The silicon film has a non-doped layer, which does not contain impurities, and an impurity layer which is formed on the non-doped layer and contains impurities. The silicide film is formed on the impurity layer of the silicon film.

Abstract: A structure useful for electrical interconnection comprises a substrate; a plurality of porous dielectric layers disposed on the substrate; an etch stop layer disposed between a first of the dielectric layers and a second of the dielectric layers; and at least one thin, tough, non-porous dielectric layer disposed between at least one of the porous dielectric layers and the etch stop layer. A method for forming the structure comprising forming a multilayer stack of porous dielectric layers on the substrate, the stack including the plurality of porous dielectric layers, and forming a plurality of patterned metal conductors within the multilayer stack. Curing of the multilayer dielectric stack may be in a single cure step in a furnace. The application and hot plate baking of the individual layers of the multi layer dielectric stack may be accomplished in a single spin-coat tool, without being removed, to fully cure the stack until all dielectric layers have been deposited.

Abstract: An object of the present invention is to improve the inter-layer adhesiveness of the diffusion barrier film while maintaining the lower dielectric constant of the diffusion barrier film. A diffusion barrier film for a copper interconnect comprises an insulating material containing silicon, carbon, hydrogen and nitrogen as constituent elements, and also containing Si—H bond, Si—C bond and methylene bond (—CH2—). The insulating material involves I2/I1 of not lower than 0.067 and I3/I1 of not higher than 0.0067 appeared in an infrared absorption spectrum; where I1 is defined as an absorption area of the infrared absorption band having a peak near 810 cm−1, I2 is defined as an absorption area of the infrared absorption band having a peak near 2,120 cm−1 and I3 is defined as an absorption area of the infrared absorption band having a peak near 1,250 cm−1.

Abstract: A multi-level shielded multi-conductor interconnect bus for use in interconnecting MEM devices with control signal sources and a method of fabricating a multi-level shielded multi-conductor interconnect bus are disclosed. In one embodiment, a multi-level shielded interconnect bus (410A) formed on a substrate (20) includes first and second level electrically conductive lines (42, 92) arranged in sets of one, two or more conductive lines between first and second level electrically conductive shield walls (46, 66, 96). The first and second level electrically conductive lines (42, 92) are surrounded by various layers of dielectric material (30, 50, 80, 100). A first level electrically conductive shield (78) overlies the first level electrically conductive lines (42) and shield walls (46, 66). A second level electrically conductive shield (112) overlies the second level electrically conductive lines (92) and shield walls (96).

Abstract: A memory device wherein a diode is serially connected to a programmable resistor and is in electrical communication with a buried digit line. An electrically conductive plug is electrically interposed between the digit line and a strapping layer, thereby creating a double metal scheme wherein the strapping layer is a second metal layer overlying metal wordlines. In a method of a first embodiment the strapping material is electrically connected to the digit line through a planar landing pad overlying the conductive plug. An insulative material is sloped to the planar landing pad in order to provide a surface conducive to the formation of the strapping material.

Abstract: A micromechanical component and method for its manufacture, in particular an acceleration sensor or a rotational speed sensor, includes: function components suspended movably above a substrate; a first insulation layer provided above the substrate; a first micromechanical function layer including conductor regions provided above the first insulation layer; a second insulation layer provided above the conductor regions and above the first insulation layer; a third insulation layer provided above the second insulation layer; a second micromechanical function layer including first and second trenches provided above the third insulation layer, the second trenches extending to the third insulation layer above the conductor regions and the first trenches extending to a cavity beneath the movably suspended function components in the second micromechanical function layer.

Abstract: This invention provides practical methods to fabricate sub-micron 3D integrated circuits using multiple layers of diodes manufactured on polycrystalline or amorphous semiconductor thin films. The long existing problems for using poly diodes for high density IC are solved by design and manufacture methods. The circuit design methods of the present invention improve the tolerance in non-ideal properties of diodes. The resulting IC products can function correctly even when many of their diodes are defective. We also developed manufacture procedures fully compatible with current art IC technologies. No additional masking steps or high temperature procedures are used. The 3D IC devices of the present invention are ready to be manufactured by current art IC technologies. Integrated circuits with unprecedented densities are therefore realized by stacking thin film diodes upon common active devices.

Abstract: Integrated circuitry includes a semiconductive substrate, an insulative material over the semiconductive substrate, and a series of alternating first and second conductive lines, the first and second lines being spaced and positioned laterally adjacent one another over the insulating layer. At least some of the laterally adjacent conductive lines may have different cross-sectional shapes in a direction perpendicular to the respective line. Alternatively, or in addition, individual second series conductive lines may be spaced from adjacent first series conductive lines a distance that is less than a minimum width of the first series lines.

Abstract: An integrated circuit test system and method therefor is provided having a semiconductor substrate with an electrical ground and a source of electrical potential. A dielectric layer with first and second openings is formed on the semiconductor substrate. First and second barrier layers are deposited on the dielectric layer to line the openings. A first conductor core is deposited over the first barrier layer to fill the first opening and is connected to a source of electrical potential. A second conductor core is deposited over the second barrier layer to fill the second opening and is connected to the electrical ground. A current measuring device is provided to measure leakage current flow between the first and second conductor cores.

Abstract: To provide excellent reliability and high yield of a semiconductor device that has a multi-wiring structure by using a fluorine-containing silicon oxide film as an interlayer insulating film. A fluorine-containing silicon oxide film is formed so as to cover a lower layer metal wiring. A TEOS film is formed on the fluorine-containing silicon oxide film. After planarizing the TEOS film with the CMP method, an SiH4-based silicon oxide film that is suitable for capturing fluorine is formed on the TEOS film. Metal wirings are formed on the SiH4-based silicon oxide film. A predetermined heat treatment is performed to capture fluorine inside the SiH4-based silicon oxide film. The SiH4-based silicon oxide film is patterned to the same pattern as the metal wirings. After diffusing fluorine into the atmosphere from the exposed area of the TEOS film, a silicon nitride film is formed on the metal wirings.

Abstract: A semiconductor memory device having at least one memory cell row, each memory cell having an information storing element and a related select transistor for selecting the storing element. The select transistor includes a gate oxide region over a silicon substrate, a lower polysilicon layer and an upper polysilicon layer superimposed to the gate oxide region and electrically insulated by an intermediate dielectric layer interposed therebetween. The gate oxide regions of the select transistors of the at least one row are separated by field oxide regions, and the lower and upper polysilicon layers and the intermediate dielectric layer extend along the row over the gate oxide regions of the select transistors and over the field oxide regions. Along the row there is at least one opening in the upper polysilicon layer, intermediate dielectric layer and lower polysilicon layer, inside of which a first contact element suitable to electrically connect the lower and upper polysilicon layers is inserted.

Abstract: A novel dielectric composition is provided that is useful in the manufacture of electronic devices such as integrated circuit devices and integrated circuit packaging devices. The dielectric composition is prepared by crosslinking a thermally decomposable porogen to a host polymer via a coupling agent, followed by heating to a temperature suitable to decompose the porogen. The porous materials that result have dielectric constants less than about 3.0, with some materials having dielectric constants less than about 2.5. Integrated circuit devices, integrated circuit packaging devices, and methods of manufacture are provided as well.

Abstract: The use of chlorine and oxygen chemistry in a polysilicon etch environment provides a process to etch a plurality of silicon-based layers on a semiconductor substrate to an underlying oxide layer in a single step. The process is useful in the formation of gate structures wherein high selectivity to the underlying oxide layer thereby affords higher processing control over the formed gate structure.

Abstract: A low-concentration impurity region and a high-concentration impurity region are formed respectively near the lower surface and the upper surface of an undoped polysilicon film by a first and second ion-implanations. A refractory metal film of tungsten or the like is formed on the polysilicon film. The impurities are thermally diffused to form shallow-junctions of source/drain having low-concentration impurities. Lead-out electrodes having a high-impurity concentration can be formed without impeding formation of the source and drain. The refractory metal film is converted into a silicide with the resistance at the interface between the polysilicon film and the silicide kept lowered.

Abstract: A method of fabricating a semiconductor device includes following four steps. (1) Cu wiring is buried in an insulating interlayer film, an insulating film for preventing diffusion of copper is deposited on a planarized surface including the Cu wiring as the uppermost layer, and another insulating film having high moisture resistance is deposited. (2) On the insulating film, a photosensitive polyimide material is applied, exposed, and developed, thereby forming an etching mask. (3) The etching mask is cured. (4) By using the cured etching mask, the insulating films are etched to expose the Cu wiring as the uppermost layer.

Abstract: A semiconductor integrated circuit device and method of forming same is disclosed and includes a silicon substrate having a field oxide region and spaced active region. First and second self-aligned contact window openings are associated with a respective field oxide region and active region. A dummy polysilicon landing pad is formed over the field oxide region and formed below the first self-aligned contact window opening. An operative polysilicon landing pad is formed above the dummy landing pad. A silicon nitride barrier layer is also formed during the process.

Abstract: A system and related process to enable control of photolithographic pattern features on a structure having one or more severe non-flat topologies. The system includes an analysis of the Depth of Focus associated with photolithographic equipment and a photoresist film applied to the structure. From that determination a range of layout dimension of the topologies is identified accordingly and incorporated into the fabrication of such topologies. A conformal layer of material is then applied to the formed structure including the determined topologies to effectively substantially close up the topologies prior to application of the photoresist film. The system is suitable for use with any structure having severe topologies and photolithographic limitations including, for example, in the fabrication of micro-electro mechanical systems.

Abstract: A semiconductor device adopting an interlayer contact structure between upper and lower conductive layers and a method of manufacturing the semiconductor device adopting the structure are provided. The lower conductive layer includes a first conductive layer and a first silicide layer stacked together. The upper conductive layer includes a second conductive layer doped with impurities and a second silicide layer stacked together. In the interlayer contact structure, the first and second conductive layers are in direct contact with each other. This decreases the contact resistance between the two conductive layers and improves the electrical properties of the device.

Abstract: Disclosed are structures and processes which are related to asymmetric, self-aligned silicidation in the fabrication of integrated circuits. A pre-anneal contact stack includes a silicon substrate, a metal source layer such as titanium-rich titanium nitride (TiNx), and a silicon layer. The metal nitride layer is deposited on the substrate by sputtering a target metal reactively in nitrogen and argon ambient. A N:Ar ratio is selected to deposit a uniform distribution of the metal nitride in an unsaturated mode (x<1) over the silicon substrate. The intermediate substrate structure is sintered to form a metal silicide. The silicidation of metal asymmetrically consumes less of the underlying silicon than the overlying silicon layer. The resulting structure is a mixed metal silicide/nitride layer which has a sufficient thickness to provide low sheet resistance without excessively consuming the underlying substrate.

Abstract: A semiconductor integrated circuit device and method of manufacturing the same is presented. The device comprises a first conductive line formed on a semiconductor substrate. An insulating layer formed on the first conductive line and the semiconductor substrate has a first contact hole exposing the first conductive line. A second conductive line consisting of a polysilicon layer and a silicide layer thereon is formed on the insulating layer including the first contact hole. The polysilicon layer of the second conductive line extends from the sidewall of the first contact hole to the top of the insulating layer so as to expose the first conductive line. The silicide layer of the second conductive line is directly connected to the exposed first conductive line in the first contact hole. Contact resistance between a bit line and a word line on the device can be reduced by directly contacting a silicide layer of the word line and a silicide layer of the bit line.

Abstract: A wire bond pad in an electrical circuit device package and method therefor including forming an opening in a conductor of a first electrically conductive material, forming a conducting member of a second electrically conductive material, transferring the conducting member into the opening of the conductor, electrically contacting the conducting member with the conductor, and embedding conductor with the conducting member in the opening thereof in an insulating electrical circuit device package.

Abstract: A semiconductor memory device having at least one memory cell row, each memory cell having an information storing element and a related select transistor for selecting the storing element. The select transistor includes a gate oxide region over a silicon substrate, a lower polysilicon layer and an upper polysilicon layer superimposed to the gate oxide region and electrically insulated by an intermediate dielectric layer interposed therebetween. The gate oxide regions of the select transistors of the at least one row are separated by field oxide regions, and the lower and upper polysilicon layers and the intermediate dielectric layer extend along the row over the gate oxide regions of the select transistors and over the field oxide regions. Along the row there is at least one opening in the upper polysilicon layer, intermediate dielectric layer and lower polysilicon layer, inside of which a first contact element suitable to electrically connect the lower and upper polysilicon layers is inserted.

Abstract: A method for forming an electrical interconnect overlying a buried contact region of a substrate is characterized by a deposition of a first polycrystalline silicon layer and the patterning and etching of same to form a via. The via is formed in the first polycrystalline silicon layer to expose the substrate and a second polycrystalline silicon layer is formed in the via to contact the substrate. Portions of the second polycrystalline silicon layer overlying the first polycrystalline silicon layer are removed eliminating any horizontal interface between the two polycrystalline silicon layers. The first polycrystalline silicon layer remaining after the etch is then patterned to form an electrical interconnect.

Abstract: A method for making interlevel contacts having low contact resistance (Rc) between patterned polycide layers is described. The method and resulting contact structure consists of depositing and conductively doping a first polysilicon layer having a first tungsten silicide (WSi2) layer. The first polysilicon/silicide (first polycide) layer is patterned to form the first polycide inter connecting conducting layer. An insulating layer is deposited over the patterned first polycide layer and contact openings are anisotropically plasma etched in the insulating layer to the underlying polycide layer. The etching is continued to remove completely the first silicide layer in the contact openings, and to etch into the first polysilicon-layer. After a brief hydrofluoric (HF) etch, a second doped polysilicon layer is deposited and patterned to form a second conducting interconnecting level over the contact openings.

Abstract: In forming an electrode 2 on a silicon oxide film 5 on a semiconductor substrate 4 through a silicon oxide film 5, for example, the gate electrode 2 is structured in a laminated structure of a plurality of polycrystalline silicon layers 6. The portion of the gate electrode 2 is formed by a method of manufacturing a thin film having a process of depositing amorphous layers and a process of crystallizing (recrystallizing) this amorphous material.

Abstract: A semiconductor device includes a T-shaped gate on a gate insulation film, wherein the T-shaped gate includes a lower polycrystal layer containing Si and Ge and an upper polycrystal layer of polysilicon.

Abstract: A semiconductor device capable of operating at a high speed or of having many functions. In this device, delamination of buried electrodes is prevented and thus high reliability is offered. The depth A of contact holes, the minimum linewidth R of a lower metallization layer, and the thickness B of the lower metallization layer satisfy relations given by (0.605/R)0.5<A<2.78−1.02B+0.172B2.

Abstract: Form a butted contact in an SRAM memory device by exposing a contact region on the surface of a doped semiconductor substrate and a conductor stack above a field oxide region on the surface of the substrate. Form an interpolysilicon silicon oxide dielectric layer over the device with an opening framing the contact region and the butt end of the conductor stack near the contact region. Form an undoped upper polysilicon layer on the surface of the SRAM device covering the dielectric layer, the contact region, and the butt end of the conductor stack and then patterned into interconnect and load resistance parts. Form a Vcc mask on the surface of the undoped upper polysilicon layer with a window framing the dielectric layer, the contact region, and the butt end of the conductor stack, leaving an exposed region of the undoped upper polysilicon layer.

Abstract: For an integrated semiconductor chip to operate reliably, it is necessary to homogenize a substrate potential as far as possible in all regions of the chip. In order to improve the substrate contact-connections on the chip, modular dummy structures are configured in such a way that, in addition to homogenizing the areal occupancy of the chip, they form extensive electrically conductive contact between the substrate and metal interconnects of a metallization plane of the chip. This achieves homogenization of the substrate potential and improvement of the wave guiding properties of wiring planes lying above the dummy structures without an additional process step or an additional chip area being required for this purpose.

Abstract: The present invention provides a circuitry comprising: a first circuit for rising a voltage level, the first circuit having an output terminal connected to a high voltage output line for outputting a high voltage output; a comparator having an output terminal connected to an input side of the first circuit, the comparator further having a first input terminal and a second input terminal for receiving a reference voltage; and a voltage dividing circuit connected between the high voltage output line and a low voltage line having a substantially fixed lower potential than the high voltage output line, the voltage dividing circuit having an output node which is connected to the first input terminal of the comparator for outputting a divided voltage output; and the voltage dividing circuit having at least a resistance between the output node and the high voltage output line, wherein a parasitic capacitance of the at least resistance between the output node and the high voltage output line is connected to the high

Abstract: In one embodiment a substrate 14 is patterned to have high and low conductive areas 110, 112, respectively. Metal lines 104, 108 in dielectric layer 16 pass transversely over the areas 110, 112. The areas 112 interrupt parasitic inductive current induced in the substrate 14.

Abstract: A semiconductor device includes a polysilicon film formed directly or indirectly on a semiconductor substrate, and a refractory metal silicide film formed on the polysilicon film. The refractory metal silicide film comprises grains of refractory metal silicide. At least a portion of the grains has a maximum grain diameter equal to or larger than at least one of a film thickness of the refractory metal silicide film and a film width of the refractory metal silicide film.

Abstract: A method of forming a transistor in a peripheral circuit of a random access memory device wherein a transistor gate, capacitor electrode or other component in the memory cell array is formed simultaneously with the formation of a transistor gate in the periphery.

Abstract: A semiconductor memory device including memory cells with the stacked-capacitor structure that makes it possible to prevent a contact pad from being damaged. This device includes a memory cell area and a peripheral circuit area formed on a semiconductor substrate. An interlayer insulating layer having first and second penetrating holes is formed to cover the entire substrate. A capacitor has lower and upper electrode and a dielectric located between these electrodes. The lower electrode is electrically connected to the first element through the first penetrating hole. Each of the peripheral circuits has a second element, a contact pad electrically connected to the second element, a pad insulating layer formed to cover the contact pad, a pad protection layer formed on the pad insulating layer, and an interconnection conductor electrically connected to the contact pad through a contact hole penetrating the pad protection and pad insulating layers.

Abstract: An interlayer insulating film having contact holes is formed on a major surface of a semiconductor substrate. A metal silicide film is formed on the interlayer insulating film. A polycrystal silicon film extending from the inside of contact holes onto the metal silicide film is formed. A local interconnection line is constituted of the polycrystal silicon film and the metal silicide film.

Abstract: A semiconductor device adopting an interlayer contact structure between upper and lower conductive layers and a method of manufacturing the semiconductor device adopting the structure are provided. The lower conductive layer includes a first conductive layer and a first silicide layer stacked together. The upper conductive layer includes a second conductive layer doped with impurities and a second silicide layer stacked together. In the interlayer contact structure, the first and second conductive layers are in direct contact with each other. This decreases the contact resistance between the two conductive layers and improves the electrical properties of the device.

Abstract: The MOS transistor has field plates and a subarea of the gate formed from the same polysilicon layer. A gate oxide lying underneath them is produced at the beginning of the fabrication process and it therefore exhibits particularly high quality. The polysilicon in the active area is raised to the same level as the adjoining field oxide areas, resulting in a planar topology.

Abstract: An electrical interconnection method includes: a) providing two conductive layers separated by an insulating material on a semiconductor wafer; b) etching the conductive layers and insulating material to define and outwardly expose a sidewall of each conductive layer; c) depositing an electrically conductive material over the etched conductive layers and their respective sidewalls; and d) anisotropically etching the conductive material to define an electrically conductive sidewall link electrically interconnecting the two conductive layers. Such is utilizable to make thin film transistors and other circuitry.

Abstract: A capacitor integrated on a silicon substrate includes a first electrode made of highly doped polysilicon, a thin silicon oxide layer, a second electrode made of polysilicon and a silicide layer covering the second electrode. The second electrode has a high dopant concentration at its interface with the silicon oxide layer and a low or medium dopant concentration at its interface with the silicide layer.

Abstract: A vertical or parallel interconnection structure in a semiconductor device wherein a shielding means is provided to prevent signal coupling between signal lines having small swing signals and noise sensitive signals. The shielding means is disposed between the signal lines and parallel with them and driven by power source of stable level, for example a ground voltage, a power supply voltage, or a DC voltage of arbitrary level.

Abstract: A CMOS analog semiconductor apparatus and a fabrication method thereof are provided that are capable of selectively oxidizing a polysilicon to form a single layer having a conductive region and an insulation region of a semiconductor apparatus. The apparatus and method improve at least a step coverage problem of a semiconductor apparatus by using a simpler process. Further, the apparatus and method reduce a defective wiring and cracks to increase yield and reliability of the product. The apparatus can include a capacitor having a lower electrode formed on the field insulation layer of the semiconductor substrate, a first insulation layer formed on the field insulation layer including the lower electrode so as to expose a contact region for connecting with the lower electrode. An upper electrode is formed on an upper surface of the first insulation layer over the lower electrode except for the contact region. A resistance device is formed on the upper electrode.