Abstract: A fabrication method for an integrated device having a capacitor in an interconnect system is described. At least a first exposed metal line and a second metal line are provided in an insulating layer. A stack layer is deposited and patterned to form a film stack structure over the second metal line. An inter-metal dielectric layer is formed over the film stack structure, the first metal line and the insulating layer. At least a first dual damascene interconnect and a second dual damascene interconnect are formed over and in contact with the first metal line and the film stack structure, respectively.

Abstract: An active matrix substrate comprises a matrix array of TFTs. A double-layered film includes an under-layer of aluminum-neodymium (Al—Nd) alloy and an over-layer of high melting point metal. The double-layered film forms first interconnection lines for connection to the TFTs. A triple-layered film includes an under-layer of said high melting point metal, a middle-layer of said Al—Nd alloy and an over-layer of the high melting point metal. The triple-layered film forms second interconnection lines for connection to the TFTs.

Abstract: A method and structure for a single or dual damascene interconnect structure comprises forming wiring lines in a metallization layer over a substrate, shaping a laminated insulator stack above the metallization layer, patterning a hardmask over the laminated insulator stack, forming troughs in the hardmask, patterning the laminated insulator stack, forming vias in the patterned laminated insulator stack, creating sidewall spacers in the bottom portion of the vias, depositing an anti-reflective coating on the sidewall spacers, etching the troughs, removing the anti-reflective coating, depositing a metal layer in the troughs, vias, and sidewall spacers, and applying conductive material in the troughs and the vias. The laminated insulator stack comprises a dielectric layer further comprising oxide and polyarylene.

Abstract: A method for manufacturing a semiconductor device can simply form a silicide film for reducing ohmic contact between a metal line and a substrate and a ternary phase thin film as an amorphous diffusion prevention film between a metal line and the silicide film. The method for manufacturing a semiconductor device includes the steps of sequentially forming a first refractory metal and a second refractory metal on a semiconductor substrate, forming a silicide film on an interface between the semiconductor substrate and the first refractory metal, and reacting the semiconductor substrate with the first and second refractory metals on the silicide film to form a ternary phase thin film.

Abstract: In a semiconductor device, an interlevel insulating film formed between a Cu interconnection, formed by damascene, and an upper metal interconnection layer on it has a multilayered structure made up of a Cu diffusion preventive insulating layer and another insulating film. The Cu diffusion preventive insulating layer has a multilayered structure made up of not less than two layers. A method for manufacturing the semiconductor device is also disclosed.

Abstract: A typical integrated-circuit fabrication requires interconnecting millions of microscopic transistors and resistors with metal wires. Making the metal wires flush, or coplanar, with underlying insulation requires digging trenches in the insulation, and then filling the trenches with metal to form the wires. The invention provides a new “trench-less” or “self-planarizing” method of making coplanar metal wires. Specifically, one embodiment forms a first layer that includes silicon and germanium; oxidizes a region of the first layer to define an oxidized region and a non-oxidized region; and reacts aluminum or an aluminum alloy with the non-oxidized region. The reaction substitutes, or replaces, the non-oxidized region with aluminum to form a metallic wire coplanar with the first layer. Another step removes germanium oxide from the oxidized region to form a porous insulation having a very low dielectric constant, thereby reducing capacitance.

Abstract: A structure includes a diffusion barrier layer pattern, a conductive layer pattern, an adhesion layer pattern, and a tantalum nitride layer pattern that are sequentially stacked over a semiconductor substrate. According to the method of forming the structure, a tantalum nitride layer is formed by using a PVD, CVD, or ALD process and patterned to form a tantalum nitride layer pattern. The structure and the method prevents process failures such as ring defects, simplifies associated processes, and allows relatively easy exposure of only an anti-refractive layer when forming a via hole in the structure.

Abstract: An electrolytic capacitor including one type of electrode selected from a group consisting of an electrode of at least one type of alloy selected from a group consisting of niobium alloy, titanium alloy, and tungsten alloy, an electrode of mixed sinter of niobium and aluminum, or a fluorine-doped electrode of niobium or niobium alloy and on a surface of each electrode a dielectric layer is formed by anodizing the electrode.

Abstract: An organic-inorganic hybrid film is deposited on a substrate by introducing, into a vacuum chamber, a gas mixture of a silicon alkoxide and an organic compound and generating a plasma derived from the gas mixture. Then, a hydrogen plasma process is performed with respect to the organic-inorganic hybrid film by introducing, into the vacuum chamber, a gas containing a reducing gas and generating a plasma derived from the gas. As a result, an organic component in the organic-inorganic hybrid film eliminates therefrom and numerous fine holes are formed in hollow portions from which the organic component has eliminated, whereby a porous film composed of the organic-inorganic hybrid film is obtained.

Abstract: A method for controlling silver doping of a chalcogenide glass in a resistance variable memory element is disclosed herein. The method includes forming a thin metal containing layer having a thickness of less than about 250 Angstroms over a second chalcogenide glass layer, formed over a first metal containing layer, formed over a first chalcogenide glass layer. The thin metal containing layer preferably is a silver layer. An electrode may be formed over the thin silver layer. The electrode preferably does not contain silver.

Abstract: A semiconductor package seal ring including a plurality of insulating layers, a plurality of conductive runners each embedded in one of the insulating layers, and a plurality of conductive posts each contacting one of the conductive runners and extending through at least one of the insulating layers and at least partially through an opening in another one of the conductive runners.

Abstract: A typical integrated circuit interconnects millions of microscopic transistors and resistors with aluminum wires buried in silicon-dioxide insulation. Yet, aluminum wires and silicon-dioxide insulation are a less attractive combination than gold, silver, or copper wires combined with polymer-based insulation, which promise both lower electrical resistance and capacitance and thus faster, more efficient circuits. Unfortunately, conventional etch-based techniques are ineffective with gold, silver, or copper, and conventional polymer formation promote reactions with metals that undermine the insulative properties of polymer-based insulations. Accordingly, the inventor devised methods which use a liftoff procedure to avoid etching problems and a non-acid-polymeric precursor and non-oxidizing cure procedure to preserve the insulative properties of the polymeric insulator. The resulting interconnective structures facilitate integrated circuits with better speed and efficiency.

Abstract: For fabricating an interconnect structure formed within an interconnect opening surrounded by dielectric material, the interconnect opening is filled with a conductive fill material comprised of a bulk conductive fill material doped with a first dopant element and a second dopant element that is different from the first dopant element. The dielectric material is comprised of a first dielectric reactant element and a second dielectric reactant element. A diffusion barrier material is formed from a reaction of the first dielectric reactant element and the first dopant element that diffuses from the conductive fill material to the walls to the interconnect opening. In addition, a boundary material is formed from a reaction of the second dielectric reactant element and the second dopant element that diffused from the conductive fill material to the walls of the interconnect opening.

Abstract: An under-ball-metallurgy layer between a bonding pad on a chip and a solder bump made with tin-based material is provided. The under-ball-metallurgy layer at least includes an adhesion layer over the bonding pad, a nickel-vanadium layer over the adhesion layer, a wettable layer over the nickel-vanadium layer and a barrier layer over the wettable layer. The barrier layer prevents the penetration of nickel atoms from the nickel-vanadium layer and reacts with tin within the solder bump to form inter-metallic compound. This invention also provides an alternative under-ball-metallurgy layer that at least includes an adhesion layer over the bonding pad, a wettable layer over the adhesion layer and a nickel-vanadium layer over the wettable layer. The nickel within the nickel-vanadium layer may react with tin within the solder bump to form an inter-metallic compound.

Abstract: An alloy or composite is deposited in a recess feature of a semiconductor substrate by sputtering an alloy or composite target into a recess, to form a first layer of deposited material. The first layer of deposited material is resputtered at a low angle and low energy, to redeposit the first layer of deposited material onto the bottom of the recess as a second layer of deposited material having a different stoichiometry than that of the first deposited material. In a further embodiment, a sputtering chamber ambient is comprised of argon and nitrogen. In yet a further embodiment, the resputtering step is followed by deposition of at least one layer of material with a different stoichiometry than that of the second deposited layer, to form a “graded” stoichiometry of material deposited in the recess.

Abstract: A method of reducing the contact resistance of metal suicides to the p+ silicon area or the n+ silicon area of the substrate comprising: (a) forming a metal germanium (Ge) layer over a silicon-containing substrate, wherein said metal is selected from the group consisting of Co, Ti, Ni and mixtures thereof; (b) optionally forming an oxygen barrier layer over said metal germanium layer; (c) annealing said metal germanium layer at a temperature which is effective in converting at least a portion thereof into a substantially non-etchable metal silicide layer, while forming a Si—Ge interlayer between said silicon-containing substrate and said substantially non-etchable metal silicide layer; and (d) removing said optional oxygen barrier layer and any remaining alloy layer. When a Co or Ti alloy is employed, e.g.

Abstract: A semiconductor device which includes, between a copper conductive layer and a low-k organic insulator, a barrier layer comprising an amorphous metallic glass, preferably amorphous tantalum-aluminum. A method of making the semiconductor device is also disclosed.

Abstract: Described is a method and apparatus for altering the top surface of a metal interconnect. In one embodiment of the invention, a metal interconnect and a barrier layer are formed into an interlayer dielectric (ILD) and the metal interconnect and the barrier layer are planarized to the top of the ILD. The top surfaces of the metal interconnect, the barrier layer, and the ILD are altered with a second metal to form an electromigration barrier. In one embodiment of the invention, the second metal is prevented from contaminating the electrical resistivity of the metal interconnect.

Abstract: An organic electro-luminescence device that is adapted to improve its characteristic by using materials being different from each other and corresponding to each function for a formation of data lines, gate lines and supply voltage lines. The organic electro-luminescence device includes a plurality of gate lines for receiving scanning signal; a plurality of data lines for receiving data signal; and a plurality of supply voltage lines arranged alternatively with the data lines, wherein at least one of the gate line, the data line and the supply voltage line is a wiring formed from a metal material having a high melting point. The organic electro-luminescence device allows metal materials of high melting points for forming the gate line, the data line and the supply voltage line to be different from each other. Accordingly, the organic electro-luminescence device reduces defects that can be generated at the wiring formation. As a result, the organic electro-luminescence device can be highly productive.

Abstract: One via contact through which upper and lower interconnections of a multilevel interconnection are connected to each other is provided when the width or volume of the lower interconnection is not larger than a given value. A plurality of via contacts are arranged at regular intervals, each of which is not larger than a given value, in an effective diffusion region of voids included in the lower interconnection, when the width or volume of the lower interconnection exceeds a given value.

Abstract: Interconnection structures for integrated circuits have first cells disposed in a first plane, at least second cells disposed in at least a second plane parallel to the first plane, and vertical interconnections disposed for connecting conductors in the first plane with conductors in the second plane, at least some of the vertical interconnections initially incorporating antifuses. The antifuses may be disposed over conductors that are disposed on a base substrate. The antifuses are selectively fused to prepare the integrated circuit for normal operation. Methods for fabricating and using such vertical interconnection structures are disclosed.

Abstract: A solder terminal and a fabrication method thereof are provided. According to one embodiment of the present invention, a solder terminal structure includes an adhesion metal layer formed on an electrode pad of a semiconductor device, a thermal diffusion barrier, a solder bonding layer, and a solder bump formed on upper portion of the solder bonding layer. With the thermal diffusion layer, the characteristic deterioration caused by the probe mark generated on the electrode pad can be prevented during a semiconductor reliability test, and at the same time, material movement between the layers of the electrode pad, the solder bonding layer and the adhesion metal layer can be reduced. Also, by having the thermal diffusion barrier act as a solder dam (a layer to confine the melted solder area to prevent the solder from being wetted), an additional deposition or etching process can be omitted.

Abstract: A barrier layer is formed on an insulating or conducting film provided on a semiconductor substrate, and an electrode or an interconnect made from a conducting film is formed on the barrier layer. The barrier layer includes a tantalum film having the &bgr;-crystal structure.

Abstract: A method for forming within a substrate employed within a microelectronics fabrication an electrical interconnection cross-over bridging between conductive regions separated by non-conductive regions formed within the substrate. There is formed over a substrate provided with conductive and non-conductive regions a blanket dielectric layer and a blanket polysilicon layer. After patterning the polysilicon and dielectric layers. A portion of the dielectric layer at the periphery of the polysilicon layer is etched away, leaving a gap between the polysilicon patterned layer and the underlying substrate contact region. There is formed over the substrate a layer of refractory metal and after rapid thermal annealing, there is formed a surface layer of refractory metal silicide over the surfaces of the polysilicon layer and within the gap between the polysilicon layer and the substrate, completing the electrical connection.

Abstract: This invention relates to a method of forming a bottomless liner structure. The method involves the steps of first obtaining a material having a via. Next, a first layer is deposited on the material, the first layer covering the sidewalls and bottom of the via. Finally, a second layer is sputter deposited on the first material, the material Rf biased during at least a portion of the time that the second layer is sputter deposited, such that the first layer deposited on the bottom of the via is substantially removed and substantially all of the first layer deposited on the sidewalls of the via is unaffected.

Abstract: Disclosed is a semiconductor device including a semiconductor substrate, an interlayer insulating film formed on one main surface of the semiconductor substrate and having a concave portion, a liner film formed on the inner surface of the concave portion, a wiring layer formed inside the concave portion with the liner film interposed therebetween, and an agglomeration suppressing material contained in the wiring layer for suppressing agglomeration of the material constituting the wiring layer. The agglomeration suppressing material is selected from the group consisting of O, N, Nb, Ta, Ti, W and C.

Abstract: A method is proposed for forming circuit probing (CP) contact points on fine pitch peripheral bond pads (PBP) on a flip chip for the purpose of facilitating peripheral circuit probing of the internal circuitry of the flip chip. The proposed method is characterized in the forming of a dual-layer NiV/Cu metallization structure, rather than a triple-layer Al/NiV/Cu metallization structure, over each aluminum-based PBP, which includes a bottom layer of nickel-vanadium (NiV) deposited over the aluminum-based PBP and an upper layer of copper (Cu) deposited over the nickel-vanadium layer. When low-resolution photolithographic and etching equipment is used for photoresist mask definition for selective removal of the NiV/Cu metallization structure, the resulted photoresist masking can be misaligned to the PBP.

Abstract: A conductive composition of tantalum nitride is disclosed for use as a conductive element in integrated circuits. The layer is shown employed in a memory cell, and in particular in a cell incorporating a high dielectric constant material such as Ta2O5. The tantalum nitride can serve as a barrier layer protecting an underlying contact plug, or can serve as the top or bottom electrode of the memory cell capacitor. The tantalum nitride has a nitrogen content of between about 7% and 40%, thereby balancing susceptibility to oxidation with conductivity. In an illustrative embodiment, the tantalum nitride layer is a bilayer formed of a thick portion having a low nitrogen concentration, and thin portion with a higher nitrogen concentration. The thick portion thus carries the bulk of the current with low resistivity, while the thinner portion is highly resistant to oxidation.

Abstract: A semiconductor device having a multi-layered wiring structure containing a copper layer, comprises a first insulating film formed over a semiconductor substrate, a first copper pattern buried in the first insulating film, a cap layer formed on the first copper pattern and the first insulating film and made of a substance a portion of which formed on the first copper pattern has a smaller electrical resistance value than a portion formed on the first insulating film, second insulating films formed on the cap layer, and a second copper pattern buried in a hole or a trench, which is formed in the second insulating films on the first copper pattern, and connected electrically to the first copper pattern via the cap layer.

Abstract: A semiconductor device having a bump electrode comprising a substrate having a dielectric layer formed thereon, an aluminum contact pad on the substrate wherein at least a portion of the aluminum contact pad is exposed through the dielectric layer on the substrate. The aluminum contact pad is provided with an under bump metallurgy including a aluminum layer formed on the exposed portion of the aluminum contact pad, a nickel-vanadium layer formed on the aluminum layer and a titanium layer formed on the nickel-vanadium layer. A gold bump formed on the titanium layer acts as the bump electrode.

Abstract: A Cu interconnect, e.g.; a dual damascene structure, is formed with improved electromigration resistance and increased via chain yield by depositing a barrier layer in an opening by CVD, depositing a flash layer of &agr;-Ta by PVD, at a thickness less than 30 Å, on the bottom of the barrier layer, depositing a seedlayer and then filling the opening with Cu. Embodiments include depositing a thin &agr;-Ta layer, as at a thickness less than 10 Å, and/or as discontinuous regions of clusters of atoms on sides of the opening.

Abstract: A method and structure for protecting a flowable oxide insulator in a semiconductor by oxidizing sidewalls of the FOX insulator, optionally nitridizing the oxidized FOX sidewalls, and then covering all surfaces of a trough or plurality of troughs in the FOX insulator, including the sidewalls, with a conductive secondary protective layer. In a multiple layer damascene structure, the surface of the FOX insulator is also oxidized, an additional oxide layer is deposited thereon, and a nitride layer deposited on the oxide layer. Then steps are repeated to obtain a comparable damascene structure. The materials can vary and each damascene layer may be either a single damascene or a dual damascene layer.

Abstract: A connection device for a circuitry device connects a circuitry unit with a contact device to thermo-mechanically uncouple the circuitry unit and the contact device by forming the connection device as a metallic section and/or an alloy section having a buffer region, an intermediate region, and a connection region. The buffer region is of silver, the intermediate region (14) is of a silver-tin alloy region, and the connection region (16) is of an intermetallic substrate and, in particular, of an intermetallic tin-substrate.

Abstract: A semiconductor device includes a semiconductor substrate having a main circuit part including a predetermined active element and the like on a silicon substrate, an interconnection transmitting to the active element an externally supplied input signal or transmitting an output signal to be supplied to any external unit, an opening for input/output of the externally supplied signal or the signal to be supplied to any external unit to and from the interconnection, an insulating protection film for protecting the interconnection and an underlying portion thereof, a conductive metal film arranged above the main circuit part, and an aluminum oxide film arranged to cover the conductive metal film. This structure can preclude the main circuit part from being discerned by visual observation, a visible light microscope and an IR microscope, and accordingly imitation, copy and altering of the main circuit part by other people can be prevented.

Abstract: The electromigration resistance of planarized metallization patterns, for example copper, inlaid in the surface of a layer of dielectric material, is enhanced by a process comprising blanket-depositing on the planarized, upper surfaces of the metallization features and the dielectric layer at least one alloying layer comprising at least one alloying element for the metal of the features, and diffusing the at least one alloying element within the metallization features to effect alloying therewith. The at least one alloying element diffused within the metallization features, under conditions wherein an oxide layer forms on the surface of the metallization features, forms a stable oxide layer on the surface of the metallization features. The stable oxide layer reduces electromigration from the metallization features along the oxide layer.

Abstract: An integrated circuit and manufacturing method therefor is provided having a semiconductor substrate with a semiconductor device and a device dielectric layer formed on the semiconductor substrate. A channel dielectric layer on the device dielectric layer has a channel opening, a barrier layer lining the channel opening, and a conductor core filling the channel opening. The barrier layer has a more negative heat of formation than the channel dielectric layer whereby the barrier layer is reacts with and forms a barrier to diffusion of the material of the conductor core to the channel dielectric layer. The barrier layer also forms a stable compound with the conductor core to form a coherent barrier layer bonding the channel dielectric to the conductor core.

Abstract: Using plating, metal gates for N channel and P channel transistors are formed of different materials to achieve the appropriate work function for these N and P channel transistors. The plating is achieved with a seed layer consistent with the growth of the desired layer. The preferred materials are selected from the platinum metals, which comprise ruthenium, ruthenium oxide, iridium, palladium, platinum, nickel, osmium, and cobalt. These are attractive metals because they are relatively high conductivity, can be plated, and provide a good choice of work functions for forming P and N channel transistors.

Abstract: A capacitor is disposed on a semiconductor substrate and includes an interlayer dielectric layer pattern with first and second openings, which expose the semiconductor substrate in predetermined regions, respectively. A sidewall and a bottom of the first opening are covered with a first lower electrode, and a sidewall and a bottom of the second opening is covered with a second lower electrode. Inner walls of the first and second lower electrodes are covered with an upper dielectric layer. The upper dielectric layer is covered with first and second upper electrodes at the first and second openings, respectively. A lower dielectric layer pattern intervenes between the second lower electrode and the upper dielectric layer. The method includes forming and patterning an interlayer dielectric layer on a semiconductor substrate, thereby forming an interlayer dielectric layer pattern with first and second openings, which expose the semiconductor substrate, respectively.

Abstract: The invention includes a method of forming a semiconductor construction. A metal-rich metal suicide layer is formed on a silicon-comprising substrate, and a metal nitride layer is formed on the metal-rich metal silicide layer. The metal-rich metal silicide layer and metal nitride layer are thermally processed to convert some of the metal-rich metal silicide into a stoichiometric metal silicide region. The thermal processing also drives nitrogen from the metal nitride layer into the metal-rich metal silicide layer to convert some of the metal-rich metal silicide layer into a region comprising metal, silicon and nitrogen. The invention also includes semiconductor constructions comprising a layer of MSi2 and a layer of MSiqNr, where M is Ta, W or Mo, and both q and r are greater than 0 and less than 2.

Abstract: An impurity region is formed on the surface of a semiconductor substrate. An insulating layer is provided on the semiconductor substrate to cover the impurity region. A trench for defining a wiring layer is provided on the surface of the insulating layer. A connection hole is provided in the insulating layer for connecting the trench and the impurity region with each other. A conductive layer made of a high melting point metal or a compound thereof is embedded in the connection hole. A copper wire is formed in the trench to be connected to the conductive layer. According to the present invention, a semiconductor device improved to be capable of implementing an excellent wiring circuit and providing a highly integrated semiconductor circuit is obtained.

Abstract: One via contact through which upper and lower interconnections of a multilevel interconnection are connected to each other is provided when the width or volume of the lower interconnection is not larger than a given value. A plurality of via contacts are arranged at regular intervals, each of which is not larger than a given value, in an effective diffusion region of voids included in the lower interconnection, when the width or volume of the lower interconnection exceeds a given value.

Abstract: This invention provides a solution to increase the yield strength and fatigue strength of miniaturized springs, which can be fabricated in arrays with ultra-small pitches. It also discloses a solution to minimize adhesion of the contact pad materials to the spring tips upon repeated contacts without affecting the reliability of the miniaturized springs. In addition, the invention also presents a method to fabricate the springs that allow passage of relatively higher current without significantly degrading their lifetime.

Abstract: A Fluorine doped Silicon Oxide (SiO2)/Tantalum interface and method for manufacturing the same are provided that ensure the structural integrity of integrated circuits that include a Fluorine doped Silicon Oxide structure and a corresponding Tantalum barrier layer. The Fluorine doped Silicon Oxide (SiO2)/Tantalum interface comprises an amount of Silicon Nitride (SiN) in a surface region of a Fluorine doped Silicon Oxide structure. The concentration of Fluorine in the surface region is depleted with respect to a concentration of Fluorine in the remaining portion(s) of the Fluorine doped Silicon Oxide structure. The Fluorine doped Silicon Oxide (SiO2)/Tantalum interface also includes an amount of Tantalum Nitride (TaN) in the surface region. Finally, a Tantalum barrier layer is deposited over the surface region.

Abstract: A metal interconnect structure generally includes a lower-layer metal wiring, an upper-layer metal wiring partially overlapping with the lower-layer metal wiring to define a via region thereof, a dielectric layer disposed between the lower-layer metal wiring and the upper-layer metal wiring, a plurality of via plugs arranged in the dielectric layer within a first area of the via region for electrically connecting the lower-layer metal wiring and the upper-layer metal wiring, and a plurality of first dielectric structures embedded in the upper-layer metal wiring within a second area of the via region, in which the first area does not overlap with the second area.

Abstract: According to one embodiment, an NiV adhesion layer is deposited over the backside surface of a semiconductor substrate. The semiconductor substrate might comprise a group III-V compound semiconductor. The NiV adhesion layer can be deposited over the backside surface of the semiconductor substrate in, for example, a magnetron deposition system. In certain embodiments, the backside surface of the semiconductor surface may be cleaned to remove oxides from the surface prior to deposition of the NiV adhesion layer. After the NiV adhesion layer has been deposited, a gold seed layer is deposited over the NiV adhesion layer. Following deposition of the gold seed layer, a second gold layer is electroplated, or otherwise deposited, over the gold seed layer. In one embodiment, the invention is a structure fabricated according to the process steps described above.

Abstract: A semiconductor device having a contact structure that can exhibit superlative step coverage without causing voids or wiring discontinuities, using aluminum or aluminum alloys as a conductive substance for via-holes. A method of fabricating the semiconductor device comprises, for at least one layer of wiring regions above the first wiring region on a semiconductor substrate, the following steps (a) to (f): (a) a step of forming a via-hole in a second interlayer dielectric formed above the first wiring region on a semiconductor substrate; (b) a degassing step for removing gaseous components included within the interlayer dielectric by a heat treatment under reduced pressure and at the substrate temperature of 300° C. to 550° C.; (c) a step of forming a wetting layer on the surface of the interlayer dielectric and the via-hole; (d) a step of cooling the substrate to a temperature of no more than 100° C.

Abstract: The present invention is an input/output for a device and it method of fabrication. The input/output of the present invention comprises a bond pad having a ball limiting metallurgy (BLM) formed thereon and a bump formed on the ball limiting metallurgy (BLM). In an embodiment of the present invention the ball limiting metallurgy comprises a first film comprising nickel, vanadium, and nitrogen. In the second embodiment of the present invention the bump limiting metallurgy includes a first alloy film comprising a nickel-niobium alloy.

Abstract: Ta—Al—N is formed on a semiconductor device structure, such as a wiring line, to prevent interdiffusion between surrounding layers. Ta—Al—N serves as a diffusion between two conductor layers, a semiconductor layer and a conductor layer, an insulator layer and a conductor layer, an insulator layer and a semiconductor layer, or two semiconductor layers. Ta—Al—N also promotes adhesion of adjacent layers, such as two conductor layers, a conductor layer and an insulator layer, a semiconductor layer and a conductor layer, or two semiconductor layers. Ta—Al—N is also useful for forming a contact or electrode. The disclosed Ta—Al—N includes between 0.5% and 99.0% aluminum, between 0.5% and 99.0% tantalum, and between 0.5% and 99.0% nitrogen. A Ta—Al—N layer has a thickness between 50 Å and 6000 Å, and as part of a wiring line, has a thickness between 1% and 25% of the wiring line thickness.

Abstract: A semiconductor memory device includes: a capacitor formed on a substrate and including a lower electrode, a dielectric film and an upper electrode; a selection transistor formed at the substrate; an electrically conductive plug for providing electrical connection between the selection transistor and the capacitor; and a diffusion barrier film provided between the electrically conductive plug and the lower electrode of the capacitor. The diffusion barrier film is a TaxSi1−xNy film or a HfxSi1−xNy film (where 0.2<x<1 and 0<y<1). The lower electrode includes an Ir film and an IrO2 film which are sequentially formed.

Abstract: The present invention relates to a high performance, high reliability antifuse using conductive electrodes. According to first and second embodiments, the problem of switch-off in conductor-to-conductor antifuses is solved by utilizing conductive electrode materials having a relatively lower thermal conductivity than prior art electrode materials and by utilizing relatively thin electrodes, thus increasing their thermal resistance. According to a third embodiment, a relatively thin barrier layer is placed between one or both of the low thermal conductivity electrodes and the antifuse material to prevent reaction between the conductive electrodes and the antifuse material, or the materials used in manufacturing. According to a fourth embodiment, low thermal conductivity conductors are used for both electrodes in the conductor-to-conductor antifuse to achieve enhanced reliability and freedom from switch-off.