Abstract: A low-k dielectric metal conductor interconnect structure having no micro-trenches present therein and a method of forming such a structure are provided. Specifically, the above structure is achieved by providing an interconnect structure which includes at least a multilayer of dielectric materials which are applied sequentially in a single spin apply tool and then cured in a single step and a plurality of patterned metal conductors within the multilayer of spun-on dielectrics. The control over the conductor resistance is obtained using a buried etch stop layer having a second atomic composition located between the line and via dielectric layers of porous low-k dielectrics having a first atomic composition. The inventive interconnect structure also includes a hard mask which assists in forming the interconnect structure of the dual damascene-type.

Abstract: An interconnection wiring structure in an integrated circuit chip designed to eliminate electromigration. The structure includes segments of aluminum interspersed with segments of refractory metal, wherein each aluminum segment is followed by a segment of refractory metal. The aluminum and refractory metal segments are aligned with respect to each other to ensure electrical continuity and to force the electrical current to sequentially cross the aluminum and the refractory metal segments. The above structure can be advantageously enhanced by adding an underlayer, an overlayer or both, all of which are made of refractory metal. The interconnection wire structure described above can be expanded to include vias or studs linking interconnection lines placed at different levels of the IC chip.

Abstract: A method is described for fabricating an encapsulated metal structure in a feature formed in a substrate. The sidewalls and bottom of the feature are covered by a barrier layer and the feature is filled with metal, preferably by electroplating. A recess is formed in the metal, and an additional barrier layer is deposited, covering the top surface of the metal and contacting the first barrier layer. The additional barrier layer is planarized, preferably by chemical-mechanical polishing. The method may be used in fabricating a MIM capacitor, with the encapsulated metal structure serving as the lower plate of the capacitor. A second substrate layer is deposited on the top surface of the substrate, with an opening overlying the encapsulated metal structure. A dielectric layer is deposited in the opening, covering the encapsulated metal structure at the bottom thereof. An additional layer, serving as the upper plate of the capacitor, is deposited to cover the dielectric layer and to fill the opening.

Abstract: A semiconductor device includes an NMOSFET and a PMOSFET. Each MOSFET includes first and second impurity diffusion layers for forming a source region and a drain region which are formed in a silicon layer of an SOI substrate or the like, a channel region formed between the first and second impurity diffusion layers, a gate insulation layer at least formed on the channel region, and a gate electrode formed on the gate insulation layer. The gate electrode includes a tantalum nitride layer in a region in contact with at least the gate insulation layer. The semiconductor device exhibits high current drive capability and can be manufactured at high yield.

Abstract: Semiconductor films include insulating films including contact holes in semiconductor substrates, capacitors comprising lower electrodes formed on conductive material films in the contact holes, high dielectric films formed on the lower electrodes and upper electrodes formed on the high dielectric films, and barrier metal layers positioned between conductive materials in the contact holes and the lower electrodes, the barrier metal layers including metal layers formed in A-B-N structures in which a plurality of atomic layers are stacked by alternatively depositing reactive metal (A), an amorphous combination element (B) for preventing crystallization of the reactive metal (A) and nitrogen (N). The composition ratios of the barrier metal layers are determined by the number of depositions of the atomic layers.

Abstract: A semiconductor device comprises a semiconductor substrate on which an element is formed, a low dielectric constant insulation film formed over the semiconductor substrate and having a relative dielectric constant of 3 or lower, a plug and a wiring layer buried in the low dielectric constant insulation film, and a high Young's modulus insulation film having a Young's modulus of 15 GPa or higher and formed in contact with a side of the plug between the low dielectric constant insulation film and the plug.

Abstract: A conductive composition of tantalum nitride is disclosed for use as a conductive element in integrated circuits. The layer is shown employed in a memory cell, and in particular in a cell incorporating a high dielectric constant material such as Ta2O5. The tantalum nitride can serve as a barrier layer protecting an underlying contact plug, or can serve as the top or bottom electrode of the memory cell capacitor. The titanium nitride has a nitrogen content of between about 7% and 40%, thereby balancing susceptibility to oxidation with conductivity. In an illustrative embodiment, the titanium nitride layer is a bilayer formed of a thick portion having a low nitrogen concentration, and thin portion with a higher nitrogen concentration. The thick portion thus carries the bulk of the current with low resistivity, while the thinner portion is highly resistant to oxidation.

Abstract: A multi-layer film for a thin film structure, a capacitor using the multi-layer film and methods for fabricating the multi-layer film and the capacitor, the multi-layer film including a composition transition layer between a lower material layer and an upper material layer respectively formed of different elements whose interaction parameters are different from each other, the composition transition layer containing both elements of the lower and upper material layers, the concentration of the composition transition layer gradually varying from the portion of the composition transition layer contacting with the lower material layer to the portion of the composition transition layer contacting with the upper material layer such that the concentration of the element of the upper material layer is relatively large in its portion adjacent to the upper material layer, each of the lower and upper material layers being formed of an oxide or nitride material of aluminum, silicon, zirconium, cerium, titanium, yttrium,

Abstract: A structure and method for an insulator layer having carbon-graded layers above a substrate is disclosed, wherein the concentration of carbon increases in each successive carbon-graded layer above the substrate. The insulator comprises a low-k dielectric having a dielectric constant less than 3.3. The carbon-graded layer increases adhesion between the substrate and the insulator and between the insulator and the conductor layer. The structure may also include stabilization interfaces between the carbon-graded layers. More specifically, the carbon-graded layers include a first layer adjacent the substrate having a carbon content between about 5% and 20%, a second layer above the first layer having a carbon content between about 10% and 30%, and a third layer above the second layer having a carbon content between about 20% and 40%.

Abstract: An Ir—M—O composite film has been provided that is useful in forming an electrode of a ferroelectric capacitor, where M includes a variety of refractory metals. The Ir combination film effectively prevents oxygen diffusion, and is resistant to high temperature annealing in oxygen environments. When used with an underlying barrier layer made from oxidizing the same variety of M transition metals, the resulting conductive barrier also suppresses the diffusion of Ir into any underlying Si substrates. As a result, Ir silicide products are not formed, which degrade the electrode interface characteristics. The Ir combination film remains conductive, not peeling or forming hillocks, during high temperature annealing processes, even in oxygen. The Ir—M—O conductive electrode/barrier structures are useful in nonvolatile MFMIS (metal/ferro/metal/insulator/silicon) memory devices, DRAMs, capacitors, pyroelectric infrared sensors, optical displays, and piezoelectric transducers.

Abstract: An integrated circuit and manufacturing method therefor is provided having a semiconductor substrate with a semiconductor device. A device dielectric layer is formed on the semiconductor substrate and a channel dielectric layer on the device dielectric layer has an opening formed therein. A barrier layer lines the channel opening and a conductor core fills the opening over the barrier layer. A seedless barrier layer lines the opening, and a conductor core fills the opening over the seedless barrier layer. The barrier layer is deposited in the opening and contains atomic layers of barrier material which bonds to the dielectric layer, an intermediate material which bonds to the barrier material layer and to the conductor core, and a conductor core material which bonds to the intermediate material. The conductor core bonds to the conductor core material.

Abstract: To provide a technique for manufacturing a wiring line having a low resistance and a high heat resistance so as to make an active matrix type display device larger and finer. The wiring line is constructed of a laminated structure of a refractory metal, a low resistance metal and a refractory metal, and the wiring line is further protected with an anodized film. As a result, it is possible to form the wiring line having the low resistance and the high heat resistance and to form a contact with an upper line easily.

Abstract: A leadframe for use with integrated circuit chips comprising a base metal, usually copper or a copper alloy, having a modified surface adapted to provide bondability and solderability and adhesion to polymeric compounds. The modified surface comprises a layer created by converting a percentage of base metal atoms into substitutional metal complexes, usually hydrated chromates. A thin layer of plated copper may be employed for controlling uniformity and consistency of the replacement reaction.

Abstract: A process is described for forming a common input-output (I/O) site that is suitable for both wire-bond and solder bump flip chip connections, such as controlled-collapse chip connections (C4). The present invention is particularly suited to semiconductor chips that use copper as the interconnection material, in which the soft dielectrics used in manufacturing such chips are susceptible to damage due to bonding forces. The present invention reduces the risk of damage by providing site having a noble metal on the top surface of the pad, while providing a diffusion barrier to maintain the high conductivity of the metal interconnects. Process steps for forming an I/O site within a substrate are reduced by providing a method for selectively depositing metal layers in a feature formed in the substrate. Since the I/O sites of the present invention may be used for either wire-bond or solder bump connections, this provides increased flexibility for chip interconnection options, while also reducing process costs.

Abstract: Semiconductor structures are provided with on-board deuterium reservoirs or with deuterium ingress paths which allow for diffusion of deuterium to semiconductor device regions for passivation purposes. The on-board deuterium reservoirs are in the form of plugs which extend through an insulating layer and a deuterium barrier layer to the semiconductor substrate, and are preferably positioned in contact with a shallow trench oxide which will allow diffusion of deuterium to the semiconductor devices. The deuterium ingress paths extend through thin film layers from the top or through the silicon substrate.

Abstract: A ferroelectric memory cell formed on a monocrystalline silicon underlayer, either an epitaxial silicon contact plug to a transistor source or drain or silicon gate region for which the memory cell forms a non-volatile gate. A conductive barrier layer of vanadium or niobium substituted strontium titanate is epitaxially grown over the silicon, and a lower metal oxide electrode layer, a ferroelectric layer and an upper metal oxide electrode layer are epitaxially grown on the barrier layer. No platinum barrier is needed beneath the ferroelectric stack. The invention can be applied to many other functional oxide devices including micromachined electromechanical (MEM) devices and ferromagnetic tri-layer devices.

Abstract: A structure having pores includes a first layer containing alumina, a second layer that includes at least one of Ti, Zr, Hf, Nb, Ta, Mo, W and Si, and a third layer with electrical conductivity, in this order, wherein the first and second layers have pores.

Abstract: An integrated circuit and manufacturing method therefor is provided having a semiconductor substrate with a semiconductor device. A dielectric layer is on the semiconductor substrate and has an opening provided therein. A barrier layer lines the opening and has a first amorphized atomic layer of a barrier compound and a second atomic layer of a barrier metal. A seed layer is deposited to line the amorphized barrier layer. A conductor core fills the opening over the barrier layer to form a conductor channel. The seed layer is securely bonded to the amorphized barrier layer and prevents electromigration along the surface between the seed and barrier layers.

Abstract: In accordance with the invention, a metal substrate is coated with a multilayer finish comprising a layer of tin or tin alloy and one or more outer metal layers. An optional metal underlayer may be disposed between the substrate and the tin. In an exemplary embodiment the metal substrate comprises copper alloy coated with a nickel underlayer, a layer of tin and an outer metal layer of palladium. The resulting structure is particularly useful as an electrical connector or lead frame.

Abstract: To decrease the area of a chip, improve the manufacturing efficiency and decrease the cost in a semiconductor device such as a driver integrated circuit having a number of output pads, and an electronic circuit device such as electronic clock. There are disposed output pads superposed in two dimensions on driving transistors or logic circuits connected thereto, respectively. Further, not only aluminum interconnection but also bump electrodes or barrier metals are used for the interconnection of the semiconductor device. In a case where a semiconductor integrated circuit is electrically adhered on to a printed circuit board in a face down manner, a solder bump disposed on the semiconductor integrated circuit and the interconnection of the printed circuit board are directly connected to each other, thereby realizing the electrical connection. On this occasion, the bump electrode as the external connecting terminal of the semiconductor integrated circuit is laminated on the transistor.

Abstract: Between a copper film 5a and a tantalum-based barrier metal film 2b, there is set an alloy layer 10 made through the reaction of the material of the barrier metal film and copper.

Abstract: A semiconductor device fabricated by a method of reducing electromigration in Cu interconnect lines by forming an interim layer of Ca-doped copper seed layer lining a via in a chemical solution. The method reduces the drift velocity, thereby decreasing the Cu migration rate in addition to void formation rate.

Abstract: A semiconductor device includes a semiconductor substrate, a first interlayer dielectric film covering the semiconductor substrate, a second interlayer dielectric film covering the first interlayer dielectric, an opening having an upper-layer opening penetrating the second interlayer dielectric film, and a lower-layer opening penetrating the first interlayer dielectric film down to the surface of the semiconductor substrate and being connected to the upper-layer opening. The lower-layer opening being arranged such that diameter of the lower-layer reduces gradually from the upper-layer opening toward the semiconductor substrate. A conductive film covering at least the bottom surface of the lower-layer opening and side walls of the lower-layer and upper-layer openings.

Abstract: A semiconductor device has a dielectric film made of a fluorine-added carbon film formed on a substrate, a metallic layer formed on the fluorine-added carbon film and an adhesive layer formed between the dielectric film and the metallic layer. The adhesive layer is made of a compound layer having carbon and the metal (or metal the same as the metal included in the metallic layer), to protect the metallic layer from being peeled-off from the fluorine-added carbon film.

Abstract: An integrated circuit and manufacturing method therefor is provided having a semiconductor substrate with a semiconductor device. A device dielectric layer is formed on the semiconductor substrate. A channel dielectric layer on the device dielectric layer has an opening formed therein. A barrier layer, which has been implanted with a compounding material, lines the channel opening. A conductor core fills the opening over the barrier layer. The barrier layer having a dielectric layer proximate portion of a barrier compound varying into a conductor core proximate portion of a pure barrier material.

Abstract: An integrated circuit device comprising a semiconductor die having a plurality of conductive pads. Over the conductive pads is formed a passivation layer that has a plurality of passivation layer openings. The passivation layer openings are positioned over an associated one of the conductive pads. Barrier base pads are placed in electrical contact with the conductive pads such that a portion of each of barrier base pads cover at least the perimeter of each passivation layer opening. Each of the barrier base pads prevents cracks from propagating through the integrated circuit device. In another aspect of the invention, the integrated circuit device is attached to an external substrate by connecting the contact bumps to the bond pads on an electronic substrate. In yet another aspect of the invention, a method for manufacturing the integrated circuit device is described.

Abstract: A wiring of a liquid crystal display device is made of a lamination film including a first layer of Nb or alloy containing Nb as its main component and a second layer of nitride of Nb or alloy containing Nb as its main component. A liquid crystal display device having such a wiring provides a wiring structure excellent in resistance to thermal oxidation.

Abstract: A semiconductor device having bump electrodes mainly comprises a specialized under bump metallurgy (UBM) applied to a chip with copper contact pads. Typically, the chip comprises a substrate and at least one copper contact pad on the substrate. A passivation layer is formed over the substrate and has an opening positioned over the al least one copper contact pad. The UBM includes a titanium layer, a first copper layer, a nickel-vanadium layer and a second copper layer. The titanium layer forms a closed-loop surrounding the opening of the dielectric layer. The first copper layer is formed over the titanium layer and the opening of the dielectric layer such that the first copper layer directly contacts the copper contact pad. The nickel-vanadium layer is formed on the first copper layer and the second copper layer is formed on the nickel-vanadium layer. A metal bump is provided on the UBM over the copper contact pad thereby forming a bump electrode.

Abstract: A conductive barrier, useful as a ferroelectric capacitor electrode, having high temperature stability has been provided. This conductive barrier permits the use of iridium (Ir) metal in IC processes involving annealing. Separating silicon substrate from Ir film with an intervening, adjacent, tantalum (Ta) film has been found to very effective in suppressing diffusion between layers. The Ir prevents the interdiffusion of oxygen into the silicon during annealing. A Ta or TaN layer prevents the diffusion of Ir into the silicon. This Ir/TaN structure protects the silicon interface so that adhesion, conductance, hillock, and peeling problems are minimized. The use of Ti overlying the Ir/TaN structure also helps prevent hillock formation during annealing. A method of forming a multilayer Ir conductive structure and Ir ferroelectric electrode are also provided.

Abstract: An interconnect structure and barrier layer for electrical interconnections is described incorporating a layer of TaN in the hexagonal phase between a first material such as Cu and a second material such as Al, W, and PbSn. A multilayer of TaN in the hexagonal phase and Ta in the alpha phase is also described as a barrier layer. The invention overcomes the problem of Cu diffusion into materials desired to be isolated during temperature anneal at 500° C.

Abstract: Ta—Al—N is formed on a semiconductor device structure, such as a wiring line, to prevent interdiffusion between surrounding layers. Ta—Al—N serves as a diffusion between two conductor layers, a semiconductor layer and a conductor layer, an insulator layer and a conductor layer, an insulator layer and a semiconductor layer, or two semiconductor layers. Ta—Al—N also promotes adhesion of adjacent layers, such as two conductor layers, a conductor layer and an insulator layer, a semiconductor layer and a conductor layer, or two semiconductor layers. Ta—Al—N is also useful for forming a contact or electrode. The disclosed Ta—Al—N includes between 0.5% and 99.0% aluminum, between 0.5% and 99.0% tantalum, and between 0.5% and 99.0% nitrogen. A Ta—Al—N layer has a thickness between 50 Å and 6000 Å, and as part of a wiring line, has a thickness between 1% and 25% of the wiring line thickness.

Abstract: A controlled collapse chip connection (C4) structure having stronger resistance to failure is constructed for use with integrated circuit devices having copper wiring. Failure resistance is obtained by replacing the mechanically weak final passivation to copper interface. The weak interface is eliminated by use of a specific peg on peg structure together with a layer of shunt metal having excellent adhesion and barrier characteristics. A shunt metal, e.g., Ta or TaN, is placed between both the copper and final passivation and the copper and C4 metals such that it overlaps the edge of the peg defined wiring mesh to encase the copper. Overlap is obtained by the peg on peg structure where a SiO2 peg defines the copper wire mesh and a smaller Si3N4 peg placed on the SiO2 peg defines the overlap above the mesh wire and provides the ability to pattern the overlayer shunt without exposure of the copper conductor.

Abstract: A semiconductor device having bump electrodes mainly comprises a specialized under bump metallurgy (UBM) applied to a chip with copper contact pads. Typically, the chip comprises a substrate and at least one copper contact pad on the substrate. A passivation layer is formed over the substrate and has an opening positioned over the al least one copper contact pad. The UBM includes a titanium layer, a first copper layer, a nickel-vanadium layer and a second copper layer. The titanium layer forms a closed-loop surrounding the opening of the dielectric layer. The first copper layer is formed over the titanium layer and the opening of the dielectric layer such that the first copper layer directly contacts the copper contact pad. The nickel-vanadium layer is formed on the first copper layer and the second copper layer is formed on the nickel-vanadium layer. A metal bump is provided on the UBM over the copper contact pad thereby forming a bump electrode.

Abstract: A new n-type semiconducting diamond is disclosed, which is doped with n-type dopant atoms. Such diamond is advantageously formed by chemical vapor deposition from a source gas mixture comprising a carbon source compound for the diamond, and a volatile hot wire filament for the n-type impurity species, so that the n-type impurity atoms are doped in the diamond during its formation. A corresponding chemical vapor deposition method of forming the n-type semiconducting diamond is disclosed. The n-type semiconducting diamond of the invention may be usefully employed in the formation of diamond-based transistor devices comprising pn diamond junctions, and in other microelectronic device applications.

Abstract: Ta—Al—N is formed on a semiconductor device structure, such as a wiring line, to prevent interdiffusion between surrounding layers. The Ta—Al—N material serves as a diffusion between (i) two conductor layers, (ii) a semiconductor layer and a conductor layer, (iii) an insulator layer and a conductor layer, (iv) an insulator layer and a semiconductor layer, or (v) two semiconductor layers. Another use is to promote adhesion of adjacent layers, such as between (i) two conductor layers, (ii) a conductor layer and an insulator layer, (iii) a semiconductor layer and a conductor layer, or (iv) two semiconductor layers. The Ta—Al—N material also is used to form a contact or electrode. The Ta—Al—N material includes between 0.5% and 99.0% aluminum, between 0.5% and 99.0% tantalum, and between 0.5% and 99.0% nitrogen.

Abstract: Disclosed is a semiconductor device having an N-type MIS transistor formed in a first region and a P-type MIS transistor formed in a second region, wherein, the N-type MIS transistor includes a first gate insulating film formed on at least the bottom of a first concave portion formed in the first region and a first gate electrode formed on the first gate insulating film, the P-type MIS transistor includes a second gate insulating film formed on at least the bottom of a second concave portion formed in the second region and a second gate electrode formed on the second gate insulating film, each of the first and second gate electrodes includes at least one metal-containing film, and at least one of the first and second gate electrodes is of a laminate structure including a plurality of the metal-containing films, and the work function of the metal-containing film constituting at least a part of the first gate electrode and in contact with the first gate insulating film is smaller than the work function of the m

Abstract: The present invention mainly provides a method to locally form metal silicide on an integral circuit and to avoid the phenomenon of leakage current which is caused by metal silicide formed between the memory cells on the same word line. The method of the present invention achieves the above objectives by principally using a design rule to adequately arrange elements within a proper distance. In an embodiment, in order to form metal silicide layers on an integral circuit and to avoid metal silicide formed between two neighboring memory cell on the same word line, a dielectric layer is first formed in the spaced region between the two neighboring memory cells to be used as a mask. Thus, in a following selective etching process, a part of the silicon substrate within the above spaced region can be protected and not exposed. Therefore, no metal silicide is formed in the spaced region, and the above objective is achieved.

Abstract: A semiconductor barrier layer and manufacturing method therefor for copper interconnects which is a tantalum-titanium, tantalum-titanium nitride, tantalum-titanium sandwich. The tantalum in the tantalum-titanium alloy bonds strongly with the semiconductor dielectric, the tantalum-titanium nitride acts as the barrier to prevent diffusion of copper, and the titanium bonds strongly with the copper.

Abstract: A semiconductor device is constituted by embedding an Al wiring layer in a second object formed on a interlayer-insulating film on one principal plane of a semiconductor substrate and connecting with an Al wiring formed on the substrate and at least, an Nb liner film and NbAl alloy film are formed between the second object and the Al wiring layer.

Abstract: A conductive composition of tantalum nitride is disclosed for use as a conductive element in integrated circuits. The layer is shown employed in a memory cell, and in particular in a cell incorporating a high dielectric constant material such as Ta2O5. The tantalum nitride can serve as a barrier layer protecting an underlying contact plug, or can serve as the top or bottom electrode of the memory cell capacitor. The titanium nitride has a nitrogen content of between about 7% and 40%, thereby balancing susceptibility to oxidation with conductivity. In an illustrative embodiment, the titanium nitride layer is a bilayer formed of a thick portion having a low nitrogen concentration, and thin portion with a higher nitrogen concentration. The thick portion thus carries the bulk of the current with low resistivity, while the thinner portion is highly resistant to oxidation.

Abstract: A ferroelectric thin-film device comprises: a single crystal substrate; a conductive thin film formed on the single crystal substrate; and an oriented ferroelectric oxide thin film having a perovskite structure formed on the conductive thin film. The oriented ferroelectric thin film comprises a first layer having a composition changing from the interface with the conductive thin film in the thickness direction and a second layer having a constant composition formed on the first layer. The composition of the first layer and the composition of the second layer are substantially the same at the boundary between the first layer and the second layer.

Abstract: A typical integrated circuit interconnects millions of microscopic transistors and resistors with aluminum wires buried in silicon-dioxide insulation. Yet, aluminum wires and silicon-dioxide insulation are a less attractive combination than gold, silver, or copper wires combined with polymer-based insulation, which promise both lower electrical resistance and capacitance and thus faster, more efficient circuits. Unfortunately, conventional etch-based techniques are ineffective with gold, silver, or copper, and conventional polymer formation promote reactions with metals that undermine the insulative properties of polymer-based insulations. Accordingly, the inventor devised methods which use a liftoff procedure to avoid etching problems and a non-acid-polymeric precursor and non-oxidizing cure procedure to preserve the insulative properties of the polymeric insulator. The resulting interconnective structures facilitate integrated circuits with better speed and efficiency.

Abstract: A method for fabricating a thermally stable carbon-based low dielectric constant film such as a hydrogenated amorphous carbon film or a diamond-like carbon film in a parallel plate chemical vapor deposition process utilizing plasma enhanced chemical vapor deposition process is disclosed. Electronic devices containing insulating layers of thermally stable carbon-based low dielectric constant materials that are prepared by the method are further disclosed. In order to render the carbon-based low dielectric constant film thermally stable, i.e., at a temperature of at least 400° C., the films are heat treated at a temperature of not less than 350° C. for at least 0.5 hour. To enable the fabrication of thermally stable carbon-based low dielectric constant film, specific precursor materials such as cyclic hydrocarbons should be used, for instance, cyclohexane or benzene.

Abstract: A semiconductor device with high conductivity interconnection lines formed of high conductivity material, such as copper, is manufactured using tantalum nitride material as barrier material between an aluminum layer, such as the wire bonding layer, and the underlying high conductivity interconnection lines. The tantalum nitride material contains high nitrogen content.

Abstract: A semiconductor wafer includes a substrate, an aluminum layer on the substrate, an anti-reflection coating on the aluminum layer, a dielectric layer on the anti-reflection coating, and a via hole that passes through the dielectric layer and the anti-reflection coating down to a predetermined depth within the aluminum layer. A titanium layer is formed on the bottom and on the walls of the via hole. A physical vapor deposition process is then performed to form a first titanium nitride layer on the titanium layer. A chemical vapor deposition process is then performed to form a second titanium nitride layer on the first titanium nitride layer.

Abstract: A semiconductor device comprising a substrate, a conductor and an insulating film provided on the surface of the substrate, part of the surface of the substrate being electrically connected with the conductor through a contact hole made in the insulating film, wherein a barrier layer present between part of the surface of the substrate and the conductor is provided only on the bottom of the contact hole, and the barrier layer provided on the bottom comprises amorphous titanium silicon nitride.

Abstract: The present invention is directed toward the formation of implanted thermally and electrically conductive structures in a dielectric. An electrically conductive structure, such as an interconnect, is formed through ion implantation into several levels within a dielectric layer to penetrate into an electrically conductive region beneath the dielectric layer, such as a semiconductor substrate. Ion implantation continues in discreet, overlapping implantations of the ions from the electrical conductive region up to the top of the dielectric layer so as to form a continuous interconnect. Structural qualities achieved by the method of the present invention include a low interconnect-conductive region resistivity and a low thermal-cycle stress between the interconnect and the dielectric layer in which the interconnect has been implanted.

Abstract: A method of forming a conductive line structure is provided. An adhesion layer is formed on a substrate surface. A seed layer is formed on the adhesion layer. A conductor is formed on the seed layer to form a partially complete structure. The partially complete structure is exposed to an electrolyte and undergoes an anodization process. At least a portion of the seed layer and a portion of the conductor are transformed to seed layer metal oxide and conductor metal oxide, respectively. At least a portion of the adhesion layer is transformed to an adhesion layer metal oxide and a further portion of the conductor is transformed to the conductor metal oxide.

Abstract: A wiring layer of a semiconductor integrated circuit comprises a first conductive film made of a material containing Al. A material, which reacts with Al at a rate lower than that at which Ti reacts with Al, is provided on the first conductive film. A first barrier metal film is formed, and an interlayer insulating film is formed thereon. An opening is formed in the interlayer insulating film so as to expose the first barrier metal film. The opening is buried to form a second conductive film electrically connected to the first conductive film.

Abstract: A semiconductor memory device includes: a capacitor formed on a substrate and including a lower electrode, a dielectric film and an upper electrode; a selection transistor formed at the substrate; an electrically conductive plug for providing electrical connection between the selection transistor and the capacitor; and a diffusion barrier film provided between the electrically conductive plug and the lower electrode of the capacitor. The diffusion barrier film is a TaxSi1−xNy film or a HfxSi1−xNy film (where 0.2<x<1 and 0<y<1). The lower electrode includes an Ir film and an IrO2 film which are sequentially formed.