Abstract: One embodiment of the invention involves a refractory layer formed over a substrate during rapid thermal processing in which ambient hydrogen is used in a thermal processing chamber. Rapid thermal processing may occur at a temperature approximately in the range of 350° C. to approximately 550° C.

Abstract: A semiconductor device is constituted by embedding an Al wiring layer in a second object formed on an interlayer-insulating film on one principal plane of a semiconductor substrate and connecting with an Al wiring formed on the substrate and at least, an Nb liner film and NbAl alloy film are formed between the second object and the Al wiring layer.

Abstract: A microelectronic semiconductor interconnect structure barrier and method of deposition provide improved conductive barrier material properties for high-performance device interconnects. The barrier comprises a dopant selected from the group consisting of platinum, palladium, iridium, rhodium, and tin. The barrier can comprise a refractory metal selected from the group consisting of tantalum, tungsten titanium, chromium, and cobalt, and can also comprise a third element selected from the group consisting of carbon, oxygen and nitrogen. The dopant and other barrier materials can be deposited by chemical-vapor deposition to achieve good step coverage and a relatively conformal thin film with a good nucleation surface for subsequent metallization such as copper metallization in one embodiment, the barrier suppresses diffusion of copper into other layers of the device, including the inter-metal dielectric, pre-metal dielectric, and transistor structures.

Abstract: An interconnect structure and barrier layer for electrical interconnections is described incorporating a layer of TaN in the hexagonal phase between a first material such as Cu and a second material such as Al, W, and PbSn. A multilayer of TaN in the hexagonal phase and Ta in the alpha phase is also described as a barrier layer. The invention overcomes the problem of Cu diffusion into materials desired to be isolated during temperature anneal at 500° C.

Abstract: A method of forming a multi-layered interconnect structure is provided. A first conductive pattern is formed over an insulation layer. A first dielectric material is deposited over the first conductive pattern, and plugs are formed in the first dielectric material. A second conductive pattern is formed over the first dielectric material and plugs so as to form the multi-layered interconnect structure in part. Then, the first dielectric material is stripped away to leave the multi-layered interconnect structure exposed to air. A thin layer of second dielectric material is deposited so as to coat at least a portion of the interconnect structure. Next, a thin layer of metal is deposited so as to coat the at least a portion of the interconnect structure coated with the thin layer of second dielectric material. A third dielectric material is deposited over the interconnect structure to replace the stripped away first dielectric material.

Abstract: A dielectric film (110) is formed overlying a semiconductor device substrate (10). A dielectric post (204) having an outer peripheral boundary having sidewalls is formed over the dielectric film (110). A first conductive film (402) is deposited at least along the sidewalls of the dielectric post (204) to form a lower electrode. A capacitor dielectric film (1801) is deposited on the first conductive film, and a upper electrode (1802) is formed on the capacitor dielectric film (1801).

Abstract: A light-emitting semiconductor device such as a laser or LED includes a light-emitting region interposed between two GaN contact layers of different conductivity types. A metal electrical contact is provided directly on one of the contact layers and is formed of an annealed, at least partly alloyed metal layer including hafnium and gold. The metal layer may also include platinum, or platinum and titanium. Light-emitting semiconductor devices such as light-emitting diodes and lasers having such annealed, at least partly alloyed metal layer are particularly suitable for high current-density applications which result in higher operating temperatures, such they are capable of operating at higher temperatures without shorting.

Abstract: The present invention is directed toward the formation of implanted thermally and electrically conductive structures in a dielectric. An electrically conductive structure, such as an interconnect, is formed through ion implantation into several levels within a dielectric layer to penetrate into an electrically conductive region beneath the dielectric layer, such as a semiconductor substrate. Ion implantation continues in discreet, overlapping implantations of the ions from the electrical conductive region up to the top of the dielectric layer so as to form a continuous interconnect. Structural qualities achieved by the method of the present invention include a low interconnect-conductive region resistivity and a low thermal-cycle stress between the interconnect and the dielectric layer in which the interconnect has been implanted.

Abstract: Novel metal-alloy interconnections for integrated circuits. The metalalloy interconnections of the present invention comprise a substantial portion of either copper or silver alloyed with a small amount of an additive having a low residual resistivity and solid solubility in either silver or copper such that the resultant electrical resistivity is less than 3&mgr;&OHgr;-cm.

Abstract: This invention pertains to a device of a substrate and a ZrO2-based semiconductor disposed thereon and a method for depositing the semiconductor on the substrate. The semiconductor is typically in the form of a film of 1-20 weight % ZrO2 and 99-80 weight % In2O3 or SnO2 . The semiconductor is tunable in terms of optical transmission and electrical conductivity. Its transmission is in excess of about 80% over the wavelength range of 400-900 nm and its resistivity is from about 1.3×10−3 &OHgr;-cm to about 6.5×10−2 &OHgr;-cm. The deposition method is characterized by depositing in a chamber the semiconductor on a substrate by means of a physical vapor deposition whole maintaining a small oxygen pressure in the chamber.

Abstract: There is provided a semiconductor memory device with extremely less deterioration of characteristics of dielectric thin film and with high stability. A TaSiN barrier metal layer 13 is formed on a Pt upper electrode 12. This TaSiN barrier metal layer 13 has electrical conductivity and hydrogen-gas blocking property and besides has an amorphous structure stable in high temperature region without crystallizing even during firing for crystallization of an oxide ferroelectric thin film (SBT thin film) 11. Then, hydrogen gas generated during later formation of a second interlayer insulating film 15 is reliably blocked from invading into the oxide ferroelectric thin film 11, by which characteristic deterioration of the oxide ferroelectric thin film 11 due to hydrogen gas is prevented.

Abstract: A method of using polish stop film to control dishing during copper chemical mechanical polishing. In one embodiment, the method comprises several steps. One step involves depositing a polish stop layer above a metal layer disposed on a semiconductor wafer. Another step involves placing the semiconductor wafer onto a polishing pad of a chemical mechanical polishing machine. A further step involves removing the metal layer of the semiconductor wafer and also preferentially removing the polish stop layer using a chemical mechanical polishing process. The benefit of the polish stop layer is to prevent dishing of the metal layer within the trench. Another step involves ceasing the chemical mechanical polishing process when the metal layer is removed from desired areas of the semiconductor wafer and the semiconductor wafer is substantially planar.

Abstract: An Ir combination film has been provided that is useful in forming an electrode of a ferroelectric capacitor. The combination film includes tantalum and oxygen, as well as iridium. The Ir combination film effectively prevents oxygen diffusion, and is resistant to high temperature annealing in oxygen environments. When used with an underlying Ta or TaN layer, the resulting conductive barrier also suppresses to diffusion of Ir into any underlying Si substrates. As a result, Ir silicide products are not formed, which degrade the electrode interface characteristics. That is, the Ir combination film remains conductive, not peeling or forming hillocks, during high temperature annealing processes, even in oxygen. A method for forming an Ir composite film barrier layer and Ir composite film ferroelectric electrode are also provided.

Abstract: An interlayer insulation film is formed on a semiconductor substrate. A wiring is formed on a part of the surface area of the interlayer insulation film. This wiring has a laminated structure including two or more layers. That is, the wiring includes an underlayer or a first conductive layer which is made of Ta in an a phase, and an overlayer or a second conductive layer which is made of an Al alloy.

Abstract: A plurality of metal wires are formed on an underlying interlayer insulating film. Areas among the metal wires are filled with a buried insulating film of a silicon oxide film with a small dielectric constant (i.e., a first dielectric film), and thus, a parasitic capacitance of the metal wires can be decreased. On the buried insulating film, a passivation film of a silicon nitride film with high moisture absorption resistance (i.e., a second dielectric film) is formed, and thus, a coverage defect can be avoided. A bonding pad is buried in an opening formed in a part of a surface protecting film including the buried insulating film and the passivation film, so as not to expose the buried insulating film within the opening. Thus, moisture absorption through the opening can be prevented.

Abstract: A semiconductor device comprises a base layer, a barrier metal layer formed on the base layer and a metal interconnect formed on the barrier metal layer, the barrier metal layer being made of at least one element &agr; selected from metal elements and at least one element &bgr; selected from a group of boron, oxygen, carbon and nitrogen and having at least two compound films &agr;&bgr;n with different compositional ratios in atomic level arranged to form a laminate. When the elements &agr; contained in the compound films &agr;&bgr;n are same and identical and at least one of the at least two compound films &agr;&bgr;n is a compound film &agr;&bgr;x (x>1), the via resistance and the interconnect resistance of the device can be reduced, while maintaining the high barrier effect.

Abstract: A semiconductor device includes a source region and a gate disposed at the upper surface of a silicon substrate, which includes a drain region for the device. On the lower surface of the substrate is disposed a backmetal drain terminal comprising a stack that includes a first layer of tantalum and an outermost second layer of copper.

Abstract: A typical integrated circuit interconnects millions of microscopic transistors and resistors with aluminum wires buried in silicon-dioxide insulation. Yet, aluminum wires and silicon-dioxide insulation are a less attractive combination than gold, silver, or copper wires combined with polymer-based insulation, which promise both lower electrical resistance and capacitance and thus faster, more efficient circuits. Unfortunately, conventional etch-based techniques are ineffective with gold, silver, or copper, and conventional polymer formation promote reactions with metals that undermine the insulative properties of polymer-based insulations. Accordingly, the inventor devised methods which use a liftoff procedure to avoid etching problems and a non-acid-polymeric precursor and non-oxidizing cure procedure to preserve the insulative properties of the polymeric insulator. The resulting interconnective structures facilitate integrated circuits with better speed and efficiency.

Abstract: An article comprising a metal circuit and/or a heat-radiating metal plate formed on a ceramic substrate, wherein the metal circuit and/or the heat-radiating metal plate comprise either (1) the following first metal-second metal bonded product, wherein the first metal and the second metal are different, or (2) the following first metal-third metal-second metal bonded product, and wherein in (1) and (2), the first metal is bonded to the ceramic substrate; first metal: a metal selected from the group consisting of aluminum (Al), lead (Pb), platinum (Pt) and an alloy containing at least one of these metal components; second metal: a metal selected from the group consisting of copper (Cu), silver (Ag), gold (Au), aluminum (Al) and an alloy containing at least one of these metal components; and third metal: a metal selected from the group consisting of titanium (Ti), nickel (Ni), zirconium (Zr), molybdenum (Mo), tungsten (W) and an alloy containing at least one of these metal components.

Abstract: A high impedance load for an integrated circuit device provides an undoped, or lightly doped, layer of epitaxial silicon. The epitaxial silicon layer is formed over a conductive region in a substrate, such as a source/drain region. A highly conductive contact, such as a refractory metal silicide interconnect layer, is formed on top of the epitaxial silicon layer. Preferably, the epitaxial silicon layer is formed using solid phase epitaxy, from excess silicon in the silicide layer, by annealing the device after the silicide layer has been deposited.

Abstract: A structure and method for making copper interconnections in an integrated circuit are described. The structure is a damascene copper connector whose upper surface is coplanar with the upper surface of the insulating layer in which it is embedded. Out-diffusion of copper from the connector is prevented by two barrier layers. One is located at the interface between the connector and the insulating layer while the second barrier is an insulating layer which covers the upper surface of the connector. The damascene process involves filling a trench in the surface of the insulator with copper and then removing the excess by chem.-mech. polishing. Since photoresist is never in direct contact with the copper the problem of copper oxidation during resist ashing has been effectively eliminated.

Abstract: A microelectronic structure including adjacent material layers susceptible of adverse interaction in contact with one another, and a barrier layer interposed between said adjacent material layers, wherein said barrier layer comprises a binary, ternary or higher order metal nitride-carbide material, whose metal constituents are different from one another and include at least one metal selected from the group consisting of transition metals Ti, V, Cr, Zr, Nb, Mo, Hf, Ta, W, Sc and Y, and optionally further including Al and/or Si. The barrier layer is stoichiometrically constituted to be amorphous or nanocrystalline in character, and may be readily formed by techniques such as chemical vapor deposition, sputtering, and plasma-assisted deposition, to provide a diffusional barrier of appropriate resistivity character for structures such as DRAMs or non-volatile ferroelectric memory cells.

Abstract: An electrode substrate comprises a backing substrate carrying thereon a metal electrode layer and/or a recording layer, the layer or layers having a smooth surface area with a surface roughness of less than 1 nm by more than 1 &mgr;m2. The smooth surface of the metal electrode layer and/or the recording layer is formed by firstly forming the layer on another substrate having a corresponding smooth surface and then peeling another substrate off the layer after the layer is bonded to the surface of the backing substrate, whereby the smooth surface profile of another substrate is transferred to the surface of the layer formed on the backing substrate.

Abstract: A semiconductor device and a method of manufacture therefor. The semiconductor device includes: (1) a substrate having a recess therein, (2) an aluminum-alloy layer located over at least a portion of the substrate and filling at least a portion of the recess and (3) a protective metal layer at least partially diffused in the aluminum-alloy layer, the metal protective layer having a high affinity for oxygen and acting as a sacrificial target for oxygen during a reflow of the aluminum-alloy layer.

Abstract: The present invention is directed to a method for forming semiconductor devices and semiconductor device precursors having gradual slope contacts. The method for forming a semiconductor precursor includes the steps of: forming a layer of conductive material in a first layer; forming a layer of a hard mask material onto at least a portion of the first layer; etching the layer of hard mask material to expose a portion of the first layer; forming facets on the layer of hard mask material; and forming a via in the first layer such that the via extends through the first layer to expose at least a portion of the layer of conductive material.

Abstract: A semiconductor device and a process for production thereof, said semiconductor device having a new electrode structure which has a low resistivity and withstands heat treatment at 400.degree. C. and above. Heat treatment at a high temperature (400-700.degree. C.) is possible because the wiring is made of Ta film or Ta-based film having high heat resistance. This heat treatment permits the gettering of metal element in crystalline silicon film. Since this heat treatment is lower than the temperature which the gate wiring (0.1-5 .mu.m wide) withstands and the gate wiring is protected with a protective film, the gate wiring retains its low resistance.

Abstract: A semiconductor, and manufacturing method therefor, is provided with a barrier/adhesion layer, having cobalt, nickel, or palladium for semiconductors having conductive materials of copper, silver or gold. The barrier/adhesion layer can be alloyed with between about 0.2% and 4% tantalum, molybdenum, or tungsten to increase barrier effectiveness and lower resistivity.

Abstract: A high temperature metallization system for use with a semiconductor device (23). The semiconductor device (23) has a multi-layer metallization system (36). An adhesion layer (37) of the metallization system (36) is formed on a semiconductor substrate (20). A barrier layer (38) that contains a nickel alloy is formed on the adhesion layer (37). A protective layer (39) is formed on the barrier layer (38). The barrier layer (38) inhibits solder components from diffusing toward the semiconductor substrate (20) during high temperature processing.

Abstract: A process for producing titanium that includes forming gaseous titanium and then transforming the gaseous titanium into solid titanium through condensation. The titanium gas is formed by vaporizing titania with an electron beam in the presence of carbon. The gas-containing vapor is cooled to form a titanium liquid or solid.

Abstract: Ta--Al--N is formed on a semiconductor device structure, such as a wiring line, to prevent interdiffusion between surrounding layers. The Ta--Al--N material serves as a diffusion between (i) two conductor layers, (ii) a semiconductor layer and a conductor layer, (iii) an insulator layer and a conductor layer, (iv) an insulator layer and a semiconductor layer, or (v) two semiconductor layers. Another use is to promote adhesion of adjacent layers, such as between (i) two conductor layers, (ii) a conductor layer and an insulator layer, (iii) a semiconductor layer and a conductor layer, or (iv) two semiconductor layers. The Ta--Al--N material also is used to form a contact or electrode. The Ta--Al--N material includes between 0.5% and 99.0% aluminum, between 0.5% and 99.0% tantalum, and between 0.5% and 99.0% nitrogen.

Abstract: An improved and novel process for fabricating unique interconnect conducting lines and via contact structures has been developed. Using this special self aligned dual damascene process, special interconnect conducting lines and via contacts are formed which have low parasitic capacitance (low RC time constants). The invention incorporates the use of double etch stop or etch barrier layers. The key process step of this invention is special patterning of the etch stop or etch barrier layer. This is the advantage of this invention over Prior Art processes that need a continuous, thick stop layer that has a etching selectivity to silicon dioxide, SiO.sub.2 (increasing parasitic capacitance). However, in this invention a self aligned dual damascene process and structure is presented that is easier to process and has low parasitic capacitance. Repeating the self aligned dual damascene processing steps, constructs multilevel conducting structures.

Abstract: A reactor for corona destruction of volatile organic compounds (VOCs), a multi-surface catalyst for the reactor and a method of making the catalyst for the reactor. The reactor has a catalyst of a high dielectric material with an enhanced surface area. A catalyst layer stack is formed by depositing a high dielectric layer on a substrate and, then depositing a conductive layer on the dielectric layer. The catalyst layer stack is bombarded by low RF energy ions to form an enhanced surface area and to form a protective layer over the conductive layer. Catalyst layer stacks may be joined back to form double-sided catalyst layer stacks. The catalyst layer stack may be diced into small pieces that are used in the reactor or the whole catalyst layer stack may be used.

Abstract: Novel metal-alloy interconnections for integrated circuits. The metal-alloy interconnections of the present invention comprise a substantial portion of either copper or silver alloyed with a small amount of an additive having a low residual resistivity and solid solubility in either silver or copper such that the resultant electrical resistivity is less than 3 .mu..OMEGA.-cm.

Abstract: The invention includes field effect transistors and methods of forming field effect transistors. In one implementation, a field effect transistor includes a semiconductive channel region and a gate construction operatively proximate the channel region. The gate construction includes a conductive gate region and a gate dielectric region intermediate the channel region and the conductive gate region. The gate dielectric region includes a Ta.sub.2 O.sub.5 comprising layer and a SiO.sub.2 comprising layer intermediate the Ta.sub.2 O.sub.5 comprising layer and the channel region. The conductive gate region includes at least two different material layers, with one of the at least two layers comprising a first conductive material and another of the at least two layers comprising a conductive metal nitride which is received intermediate the Ta.sub.2 O.sub.5 comprising layer and the one layer. In one implementation in a field effect transistor gate, the gate dielectric region includes a Ta.sub.2 O.sub.

Abstract: The present invention relates to a high performance, high reliability antifuse using conductive electrodes. The problem of switch-off of the programmed antifuses is solved by reducing the thermal conductivity of the conductive electrodes. This is achieved by using lower thermal conductivity conductors for the electrodes or by using thinner electrodes to increase thermal resistance. According to a first aspect of the present invention, the problem of switch-off in conductor-to-conductor antifuses is solved by utilizing conductive electrode materials having a relatively lower thermal conductivity than prior art electrode materials. According to a second aspect of the present invention, the problem of switch-off in conductor-to-conductor antifuses is solved by utilizing relatively thin electrodes, thus increasing their thermal resistance.

Abstract: A ferroelectric thin-film device comprises: a single crystal substrate; a conductive thin film formed on the single crystal substrate; and an oriented ferroelectric oxide thin film having a perovskite structure formed on the conductive thin film. The oriented ferroelectric thin film comprises a first layer having a composition changing from the interface with the conductive thin film in the thickness direction and a second layer having a constant composition formed on the first layer. The composition of the first layer and the composition of the second layer are substantially the same at the boundary between the first layer and the second layer.

Abstract: An interconnection structure for a semiconductor circuit is provided employing a conductor structure electrically connected to conductive wiring located on a different level than the conductor structure. The conductor structure comprises a relatively low resistivity metal. A barrier layer of a corrosion resistant metal is located intermediate the relatively low resistivity metal and wiring to thereby separate the wiring and relatively low resistivity metal.

Abstract: A wiring layer 17' of a semiconductor device is formed, at first, by forming a Cu--Ta film 15 by adding 0.5 weight % of Ta in Cu on a barrier metal layer, and then, by forming a cap metal layer on the film 15. The wiring layer 17' is then etched with a high temperature RIE method. After this, the wiring layer 17' is heat-treated at about 450 .degree. C. for about 120 minutes in a hydrogen reduction atmosphere. With this heat treatment, Ta is precipitated at the grain boundaries of Cu of the Cu--Ta layer 15. Since Ta does not tend to be alloyed with Cu easily and has low solid solubility in Cu crystal, Ta is precipitated at the grain boundaries of Cu by the above heat treatment. When Ta is precipitated at the grain boundaries of Cu such way, grain boundary diffusion is suppressed to generate less voids, so that the resistance to EM is improved.

Abstract: Disclosed is a semiconductor device, comprising a semiconductor substrate, a cell transistor formed in the semiconductor substrate, an interlayer dielectric film in which is formed a contact hole communicating with a part of the cell transistor, a contact plug buried in the contact hole formed in the interlayer dielectric film, a capacitor lower electrode formed of a ruthenium/tantalum laminate film consisting of a tantalum film and a ruthenium film formed on the tantalum film, the lower electrode being formed on interlayer dielectric film and connected to the contact plug, a capacitor dielectric film formed on the ruthenium film included in the capacitor lower electrode and consisting of a metal oxide, and a capacitor upper electrode formed on the capacitor dielectric film, the ruthenium film exhibiting (00n) dominant orientation, where n denotes a positive integer.

Abstract: An electric solid state device comprises a substrate, an amorphous thin film formed on the substrate, and a conductive thin film formed on the amorphous thin film. In this device, an interatomic distance calculated from a peak position of a halo pattern appearing in diffraction measurement of the material of the amorphous thin film is substantially equal to an interplanar space between those two adjacent specific crystal planes of the material of the conductive thin film, which are defined at least by respective atomic strings arranged in a predetermined direction in the respective planes and separated from each other by the smallest interatomic distance possible.

Abstract: In a semiconductor device such as a thin film transistor a semiconductor region is formed and an insulating film is formed on the semiconductor region to have a contact hole extending to the semiconductor region. An electrically conductive metal layer is formed of aluminum to fill the contact hole. An electrically conductive protection layer is formed on the metal layer to prevent oxidation of the metal layer during manufacturing of the semiconductor device. Material of the protection layer is more difficult to be oxidized than aluminum. A transparent electrode is formed on the protection layer such that the electrode is electrically connected to the semiconductor region. The protection layer may be formed of titanium or a laminate layer of a titanium layer and a titanium nitride layer.

Abstract: An active matrix base presented can be readily manufactured using existing fabrication technologies, and driven by either sequential-stagger TFT or reverse-stagger TFT. The bonded interface of the matrix base has low values of electrical resistance in the terminal sections, and maintains stable resistance even after being exposed to high temperature, high humidity conditions. These results are obtained because the component materials are chosen to prevent surface oxidation at the connecting electrodes. The connecting terminals for contact with the drive circuit is made of a nitride film of a high melting point metal or a high electrical conductivity metal, at least in the interface region with the tape carrier package. The metal which can be used includes chrome, tantalum, niobium, titanium, molybdenum and tungsten, or its alloy made mostly from the element, and the high electrical conductivity metal includes aluminum or an alloy of mostly aluminum.

Abstract: A barrier material deposited as a barrier film layer in a semiconductor device to reduce the interdiffusion of materials of varying electrical conductivity comprising adjacent layers in a semiconductor device is provided. The barrier material contains a transition metal, aluminum, silicon and nitrogen as essential ingredients. Suitable transition metals are tantalum and titanium. The material provides excellent resistance to diffusion across the range of temperatures occurring in an integrated circuit manufacturing process. The material also exhibits good adhesion to materials used in semiconductor processes.

Abstract: An insulated-gate field effect transistor with the structure capable of weakening an electric field near or around the drain thereof. To this end, the transistor of the top gate type has its gate electrode which is formed of two kinds of metal layers (4, 5) capable of being anodized while carefully selecting materials and anodization process conditions in such a way as to let anodization of the lowermost metal layer (4) be faster in progress than that of its overlying metal layer (5). This ensures that an intensity-decreased electric field is applied to a portion (20) underlying an anodized part of the lower metal layer not only through a gate insulation film (3) but also through an anodized oxide (17). A weak inversion layer as created by this electric field may cause the electric field to decrease in intensity near or around the drain.

Abstract: A semiconductor device including, a wiring layer whose main component is copper being formed on a base via a barrier layer of amorphous tantalum carbide.

Abstract: By treating the silicon-oxide insulating layer of a semiconductor device with an aqueous metal-salt solution of a metal of an ion radius of less than 0.110 nm, for example, Sc, La or Zr, before a platinum electrode layer is provided on the insulating layer, the platinum layer shows excellent adhesive properties.

Abstract: In a semiconductor memory device, a tantalum silicon nitride film or hafnium silicon nitride film is provided, as a diffusion barrier layer, between a polysilicon plug which electrically connects a source/drain region to a lower platinum electrode of a capacitor, formed on a silicon substrate, and the lower platinum electrode.The tantalum silicon nitride film has a composition of Ta.sub.X Si.sub.1-X N.sub.Y wherein 0.75 .ltoreq.X.ltoreq.0.95 and 1.0 .ltoreq.Y.ltoreq.1.1.The hafnium silicon nitride film has a composition of Hf.sub.X Si.sub.1-X N.sub.Y wherein 0.2<X<1.0 and 0<Y<1.0.

Abstract: A thin-film electron emitter device is provided with a multilayer structure including upper and lower electrodes with an insulative or dielectric layer being sandwiched therebetween. The upper or "top" electrode is itself formed as a multilayer structure. For example, in one embodiment, the upper electrode is formed as a three layer lamination of an interface layer formed on the insulative layer, an intermediate or "middle" layer stacked on the interface layer and a surface layer stacked on or above the middle layer. The middle layer is made of a chosen material which is greater in sublimation enthalpy than the surface layer and yet less than the interface layer. When appropriate, the surface layer may be omitted providing two-layer structure rather than the three-layer structure.

Abstract: A layered structure is described incorporating a noble metal silicide, a noble metal and an oxygen-rich barrier layer between the noble metal silicide and noble metal. A silicon-contributing substrate may also be present in addition to or without the noble metal silicide. The invention overcomes a problem in fabricating capacitors containing high-epsilon dielectric materials or ferroelectric memory elements containing ferroelectric material, namely that silicon diffuses through the electrode in one direction and oxygen diffuses through the electrode in the other direction during the high temperature (400-700.degree. C.) deposition and processing of the dielectric.

Abstract: A semiconductor device having a semiconductor substrate and a wiring layer, which is doped with an impurity, located on the substrate. The semiconductor device has upper and lower wiring layers apart from each other. An electric insulating film electrically insulates between the upper and lower wiring layers. The insulating film has a contact hole. A wiring material is packed with the contact hole to electrically connect the upper and lower wiring layers. The impurity is contained in the lower wiring layer to decrease its resistivity.