Abstract: A semiconductor device and a method of fabricating the same include an electrode having a nickel layer with impurities. The electrode having a nickel layer with impurities can be a gate electrode or a capacitor electrode. The electrode having a nickel layer with impurities may include a combination of a pure nickel layer and a nickel layer with impurities.

Abstract: A semiconductor device includes a semiconductor substrate on which an electrode and a Cu bump are stacked. On the electrode and the Cu bump, a metal bump layer is provided. The metal bump layer comprises (i) a solder layer via which the semiconductor device is bonded and electrically connected to the mounting substrate by metal bonding and (ii) a Cu layer. A intermetallic compound can be formed by interdiffusion of the Cu layer and the solder layer.

Abstract: An electronic device bond pad includes an Al layer located over an electronic device substrate. The Al layer includes an intrinsic group 10 metal located therein.

Abstract: A conventional semiconductor device has a problem that reduction of a connection resistance value between wiring layers is difficult because of an oxide film formed between the wiring layers. In a semiconductor device of this invention, a first metal layer is embeded in opening regions which connect a first wiring layer and a second wiring layer and an opening is formed in a spin coated resin film formed on the first metal layer. In the opening, a Cr layer forming a plating metal layer and a Cu plated layer are connected to each other. With this structure, the spaces among crystal grains in portions in the Cr layer on the first metal layer are wide, which causes the portions to be coarse. In the coarse portions in the Cr layer, an alloy layer formed of the second metal layer and the Cu plated layer is formed, and thus, the connection resistance value is reduced.

Abstract: The invention relates to a flip-chip module with a semiconductor chip with contact posts, wherein the contact posts are connected electrically and mechanically to a substrate. Provided between the substrate and the semiconductor chip is a spacer, which is coupled mechanically to the substrate and/or the semiconductor chip. By this means, thermal stresses in the flip-chip module are absorbed by the spacer and kept away from the semiconductor chip. The invention also relates to a method for the production of a flip-chip module, in which firstly a spacer is located between the semiconductor chip and the substrate, after which the contact posts are soldered to the contact points of the substrate. Through the provision of the spacer the distance between the semiconductor chip and the substrate is set precisely, thereby improving the quality of the soldering points.

Abstract: Interconnections are formed over an interlayer insulating film which covers MISFETQ1 formed on the principal surface of a semiconductor substrate, while dummy interconnections are disposed in a region spaced from such interconnections. Dummy interconnections are disposed also in a scribing area. Dummy interconnections are not formed at the peripheries of a bonding pad and a marker. In addition, a gate electrode of a MISFET and a dummy gate interconnection formed of the same layer are disposed. Furthermore, dummy regions are disposed in a shallow trench element-isolation region. After such dummy members are disposed, an insulating film is planarized by the CMP method.

Abstract: In a semiconductor integrated circuit requiring a large number of pads, an internal circuit is arranged in the center portion, and a plurality of two kinds of I/O circuits for inputting and outputting signals from and to the outside and many pads are arranged along four sides of the semiconductor integrated circuit. The plurality of I/O circuits that are of one of the foregoing two kinds are one-pad I/O circuits on which one pad is arranged in a direction toward the internal circuit, whereas the plurality of I/O circuits that are of the other of the foregoing two kinds are two-pad I/O circuits on which two pads are arranged in zigzag relationship in a direction toward the internal circuit. The number of arranged pads equals to the number of pads required for the semiconductor integrated circuit. The one-pad I/O circuits and the two-pad I/O circuits are provided with power source wirings for supplying power thereto.

Abstract: A metal electrode is used for a pair with a semiconductor so as to sandwich a high-dielectric constant thin film between the metal electrode and the semiconductor. A metal electrode 13 comprises a metal film 11 formed of a first electrode material, and a characteristic control film 10 containing a second electrode material. The characteristic control film 10 is formed between the high-dielectric constant thin film 9 and the metal film 11. C is added to the characteristic control film 10. The addition of C reduces the crystal grain diameter of the material constituting the characteristic control film 10, and suppresses fluctuation of a Vth (threshold voltage).

Abstract: An integrated circuit package system includes: interconnection pads; a first device mounted below the interconnection pads; a bond wire, or a solder ball connecting the first device to the interconnection pads; a lead connected to the interconnection pad or to the first device; an encapsulation having a top surface encapsulating the first device; and a recess in the top surface of the encapsulation with the interconnection pads exposed therefrom.

Abstract: A method and device for input/output connections is provided. Devices and methods for connection structure are shown with improved mechanical properties such as hardness and abrasion resistance. Land grid array structures are provided that are less expensive to manufacture due to reductions in material cost such as gold. Ball grid array structures are provided with improved resistance to corrosion during fabrication. Ball grid array structures are also provided with improved mechanical properties resulting in improved shock testing results.

Abstract: A method and resulting device for maintaining non-porous nickel layer at a nickel/passivation interface of a semiconductor device in a nickel/gold electroless plating process. The method can include determining a thickness of a gold layer of the semiconductor device; determining an electroless plating rate and plating time of the gold layer to reach the determined thickness; determining a thickness of nickel under the gold layer to maintain the non-porous nickel layer at the nickel/passivation interface at a termination of an electroless gold plating process; and following the determinations, sequentially electroless plating of each of the nickel layer and gold layer on the device layer to the determined thicknesses.

Abstract: A package includes a first plated area, a second plated area, a die attached to the first plated area, and a bond coupling the die to the second plated area. The package further includes a molding encapsulating the die, the bond, and the top surfaces of the first and second plated areas, such that the bottom surfaces of the first and second plated areas are exposed exterior to the package. Additional embodiments include a method of making the package.

Abstract: A low resistance electrode and a compound semiconductor light emitting device including the same are provided. The low resistance electrode deposited on a p-type semiconductor layer of a compound semiconductor light emitting device including an n-type semiconductor layer, an active layer, and the p-type semiconductor layer, including: a reflective electrode which is disposed on the p-type semiconductor layer and reflects light being emitted from the active layer; and an agglomeration preventing electrode which is disposed on the reflective electrode layer in order to prevent an agglomeration of the reflective electrode layer during an annealing process.

Abstract: An integrated circuit structure includes a semiconductor substrate including a front side and a backside. A through-silicon via (TSV) penetrates the semiconductor substrate, and has a back end extending to the backside of the semiconductor substrate. A redistribution line (RDL) is over the backside of the semiconductor substrate and connected to the back end of the TSV. The integrated circuit structure further includes a passivation layer over the RDL; an opening in the passivation layer, wherein a portion of the RDL is exposed through the opening; and a nickel layer in the opening and contacting the RDL.

Abstract: A packaging substrate having an electrical connection structure and a method for fabricating the same are provided. The packaging substrate have a substrate body with a plurality of conductive pads on a surface thereof; a solder mask layer disposed on the substrate body with a plurality of openings corresponding to the conductive pads, the size of each of the openings being larger than each of the conductive pads; and electroplated solder bumps for covering the conductive pads to provide better bond strength and reliability.

Abstract: A method of packaging an integrated circuit, including providing a lead frame having lead fingers, where the lead frame has a gold layer thereon on a top surface and a bottom surface. An integrated circuit die is attached to the lead frame. The gold layer is substantially removed from portions of the top surface of the lead frame. The integrated circuit die is wire bonded to the lead fingers with a plurality of wire stitches subsequent to substantially removing the gold. The die is encapsulated in a mold compound to form a packaged integrated circuit.

Abstract: A semiconductor device is provided with a silicon substrate, with a surface for soldering the silicon substrate to a ceramic substrate, and an electrode making contact with the surface of the silicon substrate. The electrode comprises a first conductor layer, a second conductor layer, and a third conductor layer. The first conductor layer makes contact with the surface of the silicon substrate and includes aluminum and silicon. The second conductor layer makes contact with the first conductor layer and includes titanium. The third conductor layer is separated from the first conductor layer by the second conductor layer and includes nickel.

Abstract: A semiconductor device with its package size close to its chip size has a stress absorbing layer, allows a patterned flexible substrate to be omitted, and allows a plurality of components to be fabricated simultaneously. There is: a step of forming electrodes on a wafer; a step of providing a resin later as a stress relieving layer on the wafer, avoiding the electrodes; a step of forming a chromium layer as wiring from electrodes over the resin layer; and step of forming solder balls as external electrodes on the chromium layer over the resin layer; and a step of cutting the wafer into individual semiconductor chips; in the steps of forming the chromium layer and solder balls, metal thin film fabrication technology is used during the wafer process.

Abstract: Semiconductor chip packages have die asymmetrically arranged on the respective substrates. Two such packages having complementary arrangements can be stacked, one inverted with respect to the other, such that the two die are situated side-by-side in the space between the two substrates. Also, multipackage modules include stacked packages, each having the die asymmetrically arranged on the substrate. Adjacent stacked packages have complementary asymmetrical arrangements of the die, and one package is inverted with respect to the other in the stack, such that the two die are situated side-by-side in the space between the two substrates. Also, methods are disclosed for making the packages and for making the stacked package modules.

Abstract: A semiconductor apparatus includes an aluminum electrode film formed on a semiconductor chip; and a nickel plated layer formed on the aluminum electrode film, wherein a concentration of sodium and potassium present in the nickel plated layer and at an interface between the nickel plated layer and the aluminum electrode film is 3.20×1014 atoms/cm2 or less.

Abstract: A semiconductor device includes a silicon substrate, and a NiSi layer provided on the silicon substrate aiming to suppress oxidation of the surface of a NiSi layer and the resistivity increase. The NiSi layer includes a bottom NiSi region and a top NiSi region. The bottom NiSi region provided in contact with silicon surface, and containing substantially no nitrogen. The top NiSi region is a nitrided NiSi region provided in contact with the bottom NiSi region, and containing nitrogen. The NiSi layer has a total thickness of 50 nm or below.

Abstract: A method of producing an ohmic contact and a resulting ohmic contact structure are disclosed. The method includes the steps of forming a deposited film of nickel and silicon on a silicon carbide surface at a temperature below which either element will react with silicon carbide and in respective proportions so that the atomic fraction of silicon in the deposited film is greater than the atomic fraction of nickel, and heating the deposited film of nickel and silicon to a temperature at which nickel-silicon compounds will form with an atomic fraction of silicon greater than the atomic fraction of nickel but below the temperature at which either element will react with silicon carbide. The method can further include the step of annealing the nickel-silicon compound to a temperature higher than the heating temperature for the deposited film, and within a region of the phase diagram at which free carbon does not exist.

Abstract: Provided is a method and system for designing an integrated circuit (IC) substrate, the substrate being formed to include at least one die. The method includes providing at least portions of IC power and a grounding function on a metal 2 substrate layer and utilizing all of a metal 3 substrate layer for the grounding function. Portions of the metal 2 layer and a metal 4 layer are utilized for the IC power, wherein all of the IC power is centralized underneath the die.

Abstract: A semiconductor structure and a bonding method are disclosed that includes a device wafer, a substrate wafer, and a metal bonding system between the device wafer and the substrate wafer. The metal bonding system includes gold, tin, and nickel, and includes at least one discrete layer of gold and tin that is at least about 88 percent gold by weight.

Abstract: A method of activating a metal structure on an intermediate semiconductor device structure toward metal plating. The method comprises providing an intermediate semiconductor device structure comprising at least one first metal structure and at least one second metal structure on a semiconductor substrate. The at least one first metal structure comprises at least one aluminum structure, at least one copper structure, or at least one structure comprising a mixture of aluminum and copper and the at least one second metal structure comprises at least one tungsten structure. One of the at least one first metal structure and the at least one second metal structure is activated toward metal plating without activating the other of the at least one first metal structure and the at least one second metal structure. An intermediate semiconductor device structure is also disclosed.

Abstract: A semiconductor device exhibits a first metal layer, made of a first metal, with at least one contiguous subsection. At least one second metal layer, made of a second metal, is placed on the contiguous subsection of the first metal layer. The second metal is harder than the first metal. The second metal layer is structured to form at least two layer regions, which are disposed on the contiguous subsection of the first metal layer. The second metal exhibits a boron-containing or phosphorus-containing metal or a boron-containing or phosphorus-containing metal alloy.

Abstract: An LGA substrate includes a core (110), having build-up dielectric material (150), at least one metal layer (125), and solder resist (155) formed thereon, an electrically conductive land grid array pad (120) electrically connected to the metal layer, a nickel layer (121) on the electrically conductive land grid array pad, a palladium layer (122) on the nickel layer, and a gold layer (123) on the palladium layer.

Abstract: A semiconductor apparatus includes a semiconductor device formed to a first surface of a semiconductor substrate, a blocking film provided in a first via-hole, the first via-hole formed with a concave shape to the first surface of the semiconductor substrate, a first via line connected to an electrode of the semiconductor device in contact with the blocking film, a second via line formed inside a second via-hole, electrically connected with the first via line with the blocking film interposed therebetween and being apart of a wiring formed to a second surface, the second via-hole formed with a concave shape to the second surface opposing the first surface of the semiconductor substrate so as to reach the blocking film. The blocking film includes at least one kind of group 8 element.

Abstract: In integrated circuit technology; an electromigration and diffusion sensitive conductor of a metal such as copper and processing procedure therefore is provided, wherein, at a planarized chemical mechanical processed interfacing surface, the conductor metal is positioned in a region of a selectable low K eff dielectric material surrounded by a material selected to be protection from outdiffusion and a source of a film thickness cap that is to form over the conductor metal and/or serve as a catalytic layer for electroless selective deposition of a CoWP capping .

Abstract: A semiconductor device of improved stress-migration resistance and reliability includes an insulating film having formed therein a lower interconnection consisting of a barrier metal film and a copper-silver alloy film, on which is then formed an interlayer insulating film. In the interlayer insulating film is formed an upper interconnection consisting of a barrier metal film and a copper-silver alloy film. The lower and the upper interconnections are made of a copper-silver alloy which contains silver in an amount more than a solid solution limit of silver to copper.

Abstract: Some embodiments include semiconductor processing methods in which a copper barrier is formed to be laterally offset from a copper component, and in which nickel is formed to extend across both the barrier and the component. The barrier may extend around an entire lateral periphery of the component, and may be spaced from the component by an intervening ring of electrically insulative material. The copper component may be a bond pad or an interconnect between two levels of metal layers. Some embodiments include semiconductor constructions in which nickel extends across a copper component, a copper barrier is laterally offset from the copper component, and an insulative material is between the copper barrier and the copper component.

Abstract: This invention provides a semiconductor device and a manufacturing method thereof which can minimize deterioration of electric characteristics of the semiconductor device without increasing an etching process. In the semiconductor device of the invention, a pad electrode layer formed of a first barrier layer and an aluminum layer laminated thereon is formed on a top surface of a semiconductor substrate. A supporting substrate is further attached on the top surface of the semiconductor substrate. A second barrier layer is formed on a back surface of the semiconductor substrate and in a via hole formed from the back surface of the semiconductor substrate to the first barrier layer. Furthermore, a re-distribution layer is formed in the via hole so as to completely fill the via hole or so as not to completely fill the via hole. A ball-shaped terminal is formed on the re-distribution layer.

Abstract: An electronic device and the production thereof is disclosed. One embodiment includes an integrated component having a layer containing a nickel-palladium alloy.

Abstract: Semiconductor devices and methods are disclosed for improving electrical connections to integrated circuits. A process flow and device with a dual/single damascene interconnect structure overlying an existing interconnect structure in a semiconductor wafer is provided. A capping layer is formed thereon that comprises nickel/palladium layers within a bond pad opening. The layers are polished using a chemical mechanical polishing (CMP) technique so that the capping layers are within the opening.

Abstract: A method and device for input/output connections is provided. Devices and methods for connection structure are shown with improved mechanical properties such as hardness and abrasion resistance. Land grid array structures are provided that are less expensive to manufacture due to reductions in material cost such as gold. Ball grid array structures are provided with improved resistance to corrosion during fabrication. Ball grid array structures are also provided with improved mechanical properties resulting in improved shock testing results.

Abstract: A method of fabricating a semiconductor device having a pair of shallow silicided source and drain junctions with minimal leakage is disclosed. The semiconductor device typically has a MISFET structure with NiSi regions partially making up the source and drain regions. The fabrication method includes the steps of providing silicon surfaces having Si{110} crystal planes on both sides of this gate electrode and forming a plurality of nickel silicide (NiSi) regions, each having a rectangular planar shape whose shorter sides being equal or less than 0.5 ?m in length and running along a Si<100> direction.

Abstract: An oxide or nitride semiconductor layer is formed over a substrate. A first conductive layer including a first element and a second element, and a second conductive layer including the second element are formed over the semiconductor layer. The first element is oxidized or nitrogenized near an interface region between the first conductive layer and the oxide or nitride semiconductor layer by heat treatment or laser irradiation. The Gibbs free energy of oxide formation of the first element is lower than those of the second element or any element in the oxide or nitride semiconductor layer.

Abstract: A transparent, electrically conductive composite includes a layer of molybdenum oxide or nickel oxide deposited on a layer of zinc oxide layer. The molybdenum component exists in a mixed valence state in the molybdenum oxide. The nickel component exists in a mixed valence state in the nickel oxide. The composite may be utilized in various electronic devices, including optoelectronic devices. In particular, the composite may be utilized as a transparent conductive electrode. As compared to conventional transparent conduct oxides such as indium tin oxide, the composite exhibits superior properties, including a higher work function.

Abstract: A semiconductor device includes a substrate, a metal layer, an alloy layer and a Sn—Ag—Cu-based solder ball. The metal layer is configured to be formed on the substrate. The alloy layer is configured to be formed on the metal layer. The Sn—Ag—Cu-based solder ball is configured to be placed on the alloy layer. The alloy layer includes Ni and Zn as essential elements.

Abstract: An integrated circuit structure includes a semiconductor substrate including a front side and a backside. A through-silicon via (TSV) penetrates the semiconductor substrate, and has a back end extending to the backside of the semiconductor substrate. A redistribution line (RDL) is over the backside of the semiconductor substrate and connected to the back end of the TSV. The integrated circuit structure further includes a passivation layer over the RDL; an opening in the passivation layer, wherein a portion of the RDL is exposed through the opening; and a nickel layer in the opening and contacting the RDL.

Abstract: A method for forming a via in an integrated circuit packaging substrate includes embedding an interfacial adhesion layer at a base of a via, and heating the materials at the base of the via. Embedding the interfacial adhesion layer further includes placing a conductive material over the interfacial adhesion layer. An interfacial layer material is deposited within at the base of opening and a conductive material is placed over the interfacial material. The interfacial layer material is a material that will diffuse into the conductive material at the temperature produced by heating the materials at the base of the via opening. Heating the materials at the base of the via opening includes directing energy from a laser at the base of the opening. An integrated circuit packaging substrate includes a first layer of conductive material, and a second layer of conductive material.

Abstract: A thin film electrode for ohmic contact of a p-type GaN semiconductor includes first and second electrode layers sequentially stacked on a p-type GaN layer. The first electrode layer may include an Ni-based alloy, a Cu-based alloy, a Co-based alloy, or a solid solution capable of forming a p-type thermo-electronic oxide or may include a Ni-oxide doped with at least one selected from Al, Ga, and In. The second electrode layer may include at least one selected from the group consisting of Au, Pd, Pt, Ru, Re, Sc, Mg, Zn, V, Hf, Ta, Rh, Ir, W, Ti, Ag, Cr, Mo, Nb, Ca, Na, Sb, Li, In, Sn, Al, Ni, Cu, and Co. Furthermore, a method of fabricating the thin film electrode is provided.

Abstract: In a thin-film transistor substrate including a substrate, a thin-film transistor semiconductor layer, a source/drain electrode, and a transparent pixel electrode, the source/drain electrode includes a thin film of an aluminum alloy containing 0.1 to 6 atomic percent of nickel as an alloy element, and the aluminum alloy thin film is directly connected to the thin-film transistor semiconductor layer.

Abstract: A microcircuit package having a ductile layer between a copper flange and die attach. The ductile layer absorbs the stress between the flange and semiconductor device mounted on the flange, and can substantially reduce the stress applied to the semiconductor device. In addition, the package provides the combination of copper flange and polymeric dielectric with a TCE close to copper, which results in a low stress structure of improved reliability and conductivity.

Abstract: An LED array chip (2), which is one type of a semiconductor light emitting device, includes an array of LEDs (6), a base substrate (4) supporting the array of the LEDs (6), and a phosphor film (48). The array of LEDs (6) is formed by dividing a multilayer epitaxial structure including a light emitting layer into a plurality of portions. The phosphor film (48) covers an upper surface of the array of the LEDs (6) and a part of every side surface of the array of LEDs (6). Here, the part extends from the upper surface to the light emitting layer.

Abstract: A semiconductor device and a method of fabricating the same include an electrode having a nickel layer with impurities. The electrode having a nickel layer with impurities can be a gate electrode or a capacitor electrode. The electrode having a nickel layer with impurities may include a combination of a pure nickel layer and a nickel layer with impurities.

Abstract: Disclosed herein is a method of depositing a nanolaminate film for next-generation non-volatile floating gate memory devices by atomic layer deposition. The method includes the steps of: introducing a substrate into an atomic layer deposition reactor; forming on the substrate a first high-dielectric-constant layer by alternately supplying an oxygen source and a metal source selected from among an aluminum source, a zirconium source and a hafnium source; forming on the first high-dielectric-constant layer a nickel oxide layer by alternately supplying a nickel source and an oxygen source; and forming on the nickel oxide layer a second high-dielectric-constant layer by alternately supplying an oxygen source and a metal source selected from among an aluminum source, a zirconium source and a hafnium source.

Abstract: A semiconductor package includes: a semiconductor chip having a first surface, and a second surface that is opposite to the first surface and allows a semiconductor device to be formed thereon; bonding pads disposed on the second surface of the semiconductor chip; and a metal ion barrier layer disposed on the first surface of the semiconductor chip, and preventing metal ions from penetrating into the semiconductor chip through the first surface of the semiconductor chip. Accordingly, the semiconductor package can obtain a superior semiconductor device by minimizing moisture absorption and effectively blocking the penetration of metal ions.

Abstract: A thin die Package Substrate is described that may be produced using existing chemistry. In one example, a package substrate is built over a support material. A dry film photoresist layer is formed over the package substrate. The support material is removed from the package substrate. The dry film photoresist layer is removed from the substrate and the substrate is finished for use with a package.

Abstract: A semiconductor package and a fabrication method are disclosed. The fabrication method includes applying a sacrificial layer on one surface of a metal carrier, applying an insulation layer on the sacrificial layer, and forming through holes in the sacrificial layer and the insulation layer to expose the metal carrier; forming a conductive metallic layer in each through hole; forming a patterned circuit layer on the insulation layer to be electrically connected to the conductive metallic layer; mounting at least a chip on the insulation layer and electrically connecting the chip to the patterned circuit layer; forming an encapsulant to encapsulate the chip and the patterned circuit layer; and removing the metal carrier and the sacrificial layer to expose the insulation layer and conductive metallic layer to allow the conductive metallic layer to protrude from the insulation layer.