Abstract: A substrate for device bonding is provided, which enables bonding of a device with high bond strength to an Au electrode formed on a substrate such as aluminum nitride by soldering the device at a low temperature using a soft solder metal having a low melting point such as an Au—Sn-based solder having an Au content of 10% by weight. The substrate for device bonding comprises a substrate having an Au electrode layer formed on its surface and in which (i) a layer composed of a platinum group element, (ii) a layer composed of at least one transition metal element selected from the group consisting of Ti, V, Cr and Co, (iii) a barrier metal layer composed of at least one metal selected from the group consisting of Ag, Cu and Ni and (iv) a solder layer composed of a solder containing Sn or In as a main component are laminated in this order on the Au electrode layer.

Abstract: Interconnections are formed over an interlayer insulating film which covers MISFETQ1 formed on the principal surface of a semiconductor substrate, while dummy interconnections are disposed in a region spaced from such interconnections. Dummy interconnections are disposed also in a scribing area. Dummy interconnections are not formed at the peripheries of a bonding pad and a marker. In addition, a gate electrode of a MISFET and a dummy gate interconnection formed of the same layer are disposed. Furthermore, dummy regions are disposed in a shallow trench element-isolation region. After such dummy members are disposed, an insulating film is planarized by the CMP method.

Abstract: A semiconductor device includes a semiconductor substrate, a first metal film on a back surface of the semiconductor substrate, a second metal film on the first metal film, and a third metal film on the second metal film. The first metal film forms an alloy with a solder. The second metal film causes isothermal solidification of the solder. The third metal film improves solder wetting properties or inhibits oxidation. Further, in a method for die-bonding a semiconductor device, a specific metal is diffused into a solder, when the solder melts, to transform the solder into a high melting point alloy, thereby causing isothermal solidification of the solder. The specific metal is different from the metal of the solder.

Abstract: Methods and compositions for electrolessly depositing Co, Ni, or alloys thereof onto a substrate in manufacture of microelectronic devices. Grain refiners, levelers, oxygen scavengers, and stabilizers for electroless Co and Ni deposition solutions.

Abstract: A TFT includes a gate electrode, an active layer, a source electrode, a drain electrode, and a buffer layer. The gate electrode is formed on the substrate; the active layer is formed on the gate electrode. The source and drain electrodes, formed on the active layer, are separated by a predetermined distance. The buffer layer is formed between the active layer and the source and drain electrodes. The buffer layer has a substantially continuously varying content ratio corresponding to a buffer layer thickness. The buffer layer is formed to suppress oxidation of the active layer, and reduce contact resistance.

Abstract: Methods and compositions for electrolessly depositing Co, Ni, or alloys thereof onto a substrate in manufacture of microelectronic devices. Grain refiners, levelers, oxygen scavengers, and stabilizers for electroless Co and Ni deposition solutions.

Abstract: Methods and compositions for electrolessly depositing Co, Ni, or alloys thereof onto a substrate in manufacture of microelectronic devices. Grain refiners, levelers, oxygen scavengers, and stabilizers for electroless Co and Ni deposition solutions.

Abstract: A semiconductor device and a manufacturing method thereof are disclosed. The method includes the steps of providing a carrier board having conductive circuits disposed thereon and a plurality of chips with active surfaces having solder pads disposed thereon, wherein conductive bumps are disposed on the solder pads; mounting chips on the carrier board; filling the spacing between the chips with a dielectric layer and forming openings in the dielectric layer at periphery of each chip to expose the conductive circuits; forming a metal layer in the openings of the dielectric layer and at periphery of the active surface of the chips for electrically connecting the conductive bumps and the conductive circuits; and cutting along the dielectric layer between the chips and removing the carrier board to separate each chip and exposing the conductive circuits from the non-active surface.

Abstract: A semiconductor device includes an effective wire formed above a substrate in a multilayer interconnection structure and having a first electrode pad in a top layer; a first reinforcing material formed in the multilayer interconnection structure like surrounding the effective wire; a protective film configured to protect a final surface of the multilayer interconnection structure; and a second reinforcing material formed at a position in contact with the protective film and also between an area in which the effective wire is formed and a chip area end, the second reinforcing material being constituted by a film pattern whose Young's modulus is larger than that of a conductor constituting the first electrode pad and that of a conductor constituting the first reinforcing material.

Abstract: A method for forming a wire bonding substrate is disclosed. A substrate comprising a first surface and a second surface is provided. A through hole is formed in the substrate. A conductive layer is formed on the first surface and the second surface of the substrate and covers a sidewall of the through hole. The conductive layer on the first surface of the substrate is patterned to form at least a first conductive pad, and the conductive layer on the second surface of the substrate is patterned to form at least a second conductive pad. An insulating layer is formed on the first surface and the second surface of the substrate and covers the first conductive pad and the second conductive pad. The insulating layer is recessed until top surfaces of the first conductive pad and the second conductive pad are exposed. A first metal layer is electroplated on the first conductive pad by applying current from the second conductive pad to the first conductive pad through the conductive layer passing the through hole.

Abstract: The invention provides a CSP type semiconductor device with high reliability. The semiconductor device includes a pad electrode formed on a semiconductor substrate, a first passivation film covering an end portion of the pad electrode and having a first opening on the pad electrode, a plating layer formed on the pad electrode in the first opening, a second passivation film covering an exposed portion of the pad electrode between an end portion of the first passivation film and the plating layer, covering an end portion of the plating layer, and having a second opening on the plating layer, and a conductive terminal formed on the plating layer in the second opening.

Abstract: Interconnections are formed over an interlayer insulating film which covers MISFETQ1 formed on the principal surface of a semiconductor substrate, while dummy interconnections are disposed in a region spaced from such interconnections. Dummy interconnections are disposed also in a scribing area. Dummy interconnections are not formed at the peripheries of a bonding pad and a marker. In addition, a gate electrode of a MISFET and a dummy gate interconnection formed of the same layer are disposed. Furthermore, dummy regions are disposed in a shallow trench element-isolation region. After such dummy members are disposed, an insulating film is planarized by the CMP method.

Abstract: The laminated structure includes a substrate of low dielectric constant material of silicon compound and an electroless copper plating layer laminated thereon with a barrier layer. The barrier layer is interposed between the substrate and the copper layer, and the barrier layer is formed by electroless plating. And the laminated structure is characterized in that the barrier layer is formed on the substrate with a monomolecular layer of organosilane compound and a palladium catalyst which are interposed between the substrate and the barrier layer, the palladium catalyst modifies the terminal, adjacent to the barrier layer, of the monomolecular layer, and the barrier layer includes an electroless NiB plating layer which is disposed on the substrate side, and a electroless CoWP plating layer.

Abstract: A device comprises a multi-layered thin film having excellent adhesion due to the method of fabricating the same. More particularly, the device includes a multi-layered thin film consisting of a tantalum nitride layer, a tantalum layer formed on the tantalum nitride layer, and a gold thin film formed on the tantalum layer.

Abstract: Structures and methods for fabrication of an under bump metallization (UBM) structure having a metal seed layer and electroless nickel deposition layer are disclosed involving a UBM structure comprising a semiconductor substrate, at least one final metal layer, a passivation layer, a metal seed layer, and a metallization layer. The at least one final metal layer is formed over at least a portion of the semiconductor substrate. Also, the passivation layer is formed over at least a portion of the semiconductor substrate. In addition, the passivation layer includes a plurality of openings. Additionally, the passivation layer is formed of a non-conductive material. The at least one final metal layer is exposed through the plurality of openings. The metal seed layer is formed over the passivation layer and covers the plurality of openings. The metallization layer is formed over the metal seed layer. The metallization layer is formed from electroless deposition.

Abstract: Interconnections are formed over an interlayer insulating film which covers MISFETQ1 formed on the principal surface of a semiconductor substrate, while dummy interconnections are disposed in a region spaced from such interconnections. Dummy interconnections are disposed also in a scribing area. Dummy interconnections are not formed at the peripheries of a bonding pad and a marker. In addition, a gate electrode of a MISFET and a dummy gate interconnection formed of the same layer are disposed. Furthermore, dummy regions are disposed in a shallow trench element-isolation region. After such dummy members are disposed, an insulating film is planarized by the CMP method.

Abstract: A method for fabricating a conductive layer is provided. First, a substrate is provided and a patterned adhesion layer is formed on the substrate. Next, a chemical plating process is performed to form a first metal layer on the patterned adhesion layer by placing the substrate in an electroplating solution and the electroplating solution is shocked. Thereafter, a second metal layer is formed on the first metal layer by performing a plating process.

Abstract: A semiconductor component has a semiconductor body and also a metal/insulation structure arranged above the semiconductor body and having a plurality of metal regions and insulation regions laterally adjoining one another. The metal regions serve for supplying the semiconductor body with electric current. Furthermore, the semiconductor component has a passivation layer arranged on the metal/insulation structure. The passivation layer includes a metal or a metal-containing compound.

Abstract: A leadframe comprises a die mounting area, a plurality of lead fingers and a metal deposit having a negative electrochemical potential with respect to a standard H2 half cell. A semiconductor package comprises the leadframe and a semiconductor chip having a plurality of contact areas mounted to the die mounting area and electrically connected to the inner ends of the lead fingers of the leadframe by a plurality of bond wires. The semiconductor chip, the bond wires and inner portions of the lead fingers are encapsulated by a plastic housing.

Abstract: In a semiconductor device according to the present invention, a plurality of opening regions 5 to 8 are formed in an insulating film on a pad electrode 3. A metal layer 9 formed on the pad electrode 3 has a plurality of concave portions 10 to 13 formed therein by covering the opening regions 5 to 8. Moreover, in a peripheral portion at a bottom of each of the concave portions 10 to 13 in the metal layer 9, the metal layer 9 and a Cu plating layer 19 react with each other. By use of this structure, the metal reaction area serves as a current path on the pad electrode 3. Thus, a resistance value on the pad electrode 3 is reduced.

Abstract: Methods and compositions for electrolessly depositing Co, Ni, or alloys thereof onto a substrate in manufacture of microelectronic devices. Grain refiners, levelers, oxygen scavengers, and stabilizers for electroless Co and Ni deposition solutions.

Abstract: An apparatus comprising an insulating substrate having first and second surfaces and a plurality of metal-filled vias extending from the first to the second surface. The first and second surfaces have contact pads, each one comprising a connector stack to at least one of the vias. The stack comprises a seed metal layer in contact with the via metal capable of providing an adhesive and conductive layer for electroplating on its surface, a first electroplated support layer secured to the seed metal layer, a second electroplated support layer, and at least one reflow metal bonding layer on the second support layer. The electrolytic plating process produces support layers substantially pure (at least 99.0%), free of unwanted additives such as phosphorus or boron, and exhibiting closely controlled grain sizes. Reflow metal connectors provide attachment to chip contact pads and external parts.

Abstract: The present invention discloses a structure of package comprising: a substrate with die receiving through holes, conductive connecting through holes and contact metal pads; a base attached on a portion of the lower surface of the substrate; multiple dice disposed within the die receiving through holes and attached on the base; multiple dielectric layers formed on the multiple dice and the substrate; multiple re-distribution layers (RDL) formed within the multiple dielectric layers and coupled to the multiple dice; a top layer formed over the RDL; and pluralities of terminal pads formed on the backside of the substrate and coupled to the RDL through the connecting through holes. The RDL is made from an alloy comprising Ti/Cu/Au alloy or Ti/Cu/Ni/Au alloy.

Abstract: A semiconductor device having nickel silicide and a method for fabricating nickel silicide. A semiconductor substrate having a plurality of doped regions is provided. Subsequently, a nickel layer is formed on the semiconductor substrate, and a first rapid thermal process (RTP) is performed to react the nickel layer with the doped regions disposed thereunder. Thereafter, the unreacted nickel layer is removed, and a second rapid thermal process is performed to form a semiconductor device having nickel silicide. The second rapid thermal process is a spike anneal process whose process temperature is between 400 and 600° C.

Abstract: A semiconductor package and a fabrication method are disclosed. The fabrication method includes applying a sacrificial layer on one surface of a metal carrier, applying an insulation layer on the sacrificial layer, and forming through holes in the sacrificial layer and the insulation layer to expose the metal carrier; forming a conductive metallic layer in each through hole; forming a patterned circuit layer on the insulation layer to be electrically connected to the conductive metallic layer; mounting at least a chip on the insulation layer and electrically connecting the chip to the patterned circuit layer; forming an encapsulant to encapsulate the chip and the patterned circuit layer; and removing the metal carrier and the sacrificial layer to expose the insulation layer and conductive metallic layer to allow the conductive metallic layer to protrude from the insulation layer.

Abstract: This invention provides a structure and method for improved transmission line operation on integrated circuits. One method of the invention includes forming transmission lines in an integrated circuit. The method includes forming a first layer of electrically conductive material on a substrate. A first layer of insulating material is formed on the first layer of the electrically conductive material. A pair of layered high permeability shielding lines are formed on the first layer of insulating material. The pair of layered high permeability shielding lines include layered permalloy and/or Ni45Fe55 films. A transmission line is formed on the first layer of insulating material and between and parallel with the pair of layered high permeability shielding lines.

Abstract: A process includes annealing one or more plated conductive leads at a predetermined temperature. The one or more plated conductive leads are plated with one or more layers, where each layer comprises a material. The predetermined temperature is greater than or equal to approximately a melting point of one of the materials. The annealing can reduce growth formations, such as whiskers, on the one or more conductive leads. Lead frames and other devices having plated conductive leads may be subjected to the process, and the resultant plated conductive leads will have fewer growth formations than plated conductive leads not subjected to the process. The plated conductive leads may be trimmed and formed prior to or after the anneal.

Abstract: The invention includes methods of electroless plating of nickel selectively on exposed conductive surfaces relative to exposed insulative surfaces. The electroless plating can utilize a bath which contains triethanolamine, maleic anhydride and at least one nickel salt.

Abstract: Methods of forming a multi-level metal line of a semiconductor device are disclosed. One example method includes subsequently stacking first and second metal layers, wherein a conductive etching stopper layer is interposed at an interface between the first and second metal layers; forming first and second metal layer pattern by patterning the first metal layer, the etching stopper layer, and the second metal layer, wherein the first metal layer pattern is formed as a lower metal line; forming a connection contact in form of a plug by selectively etching the second metal layer pattern until the etching stopper layer is exposed; forming an interlayer insulating layer to cover the connection contact and the first metal layer pattern; and exposing an upper surface of the connection contact by planarizing the interlayer insulating layer.

Abstract: A semiconductor device includes a silicon substrate, and a NiSi layer provided on the silicon substrate aiming to suppress oxidation of the surface of a NiSi layer and the resistivity increase. The NiSi layer includes a bottom NiSi region and a top NiSi region. The bottom NiSi region provided in contact with silicon surface, and containing substantially no nitrogen. The top NiSi region is a nitrided NiSi region provided in contact with the bottom NiSi region, and containing nitrogen. The NiSi layer has a total thickness of 50 nm or below.

Abstract: A method and apparatus for making a package having improved heat conduction characteristics and high frequency response. A relatively thick package substrate, such as copper, has a wiring layer bonded to one face, leaving the opposite face exposed, for example, to be a surface for connection to a heat sink. One ore more chips are bonded to the wiring layer, and an array of connectors, such as solder balls are provided around the periphery of the chip(s) for connection to a printed circuit board. In some embodiments, the printed circuit board has a hole that the chip(s) extend into to allow smaller external-connection solder balls. In some embodiments, a second heat sink is connected to the back of the chip through the PCB hole.

Abstract: A chip structure comprising a chip, a redistribution layer, a second passivation layer and at least a bump is provided. The chip has a first passivation layer and at least a bonding pad. The first passivation layer exposes the bonding pad and has at least a recess. The redistribution layer is formed over the first passivation layer and electrically connected to the bonding pad. Furthermore, the redistribution layer also extends from the bonding pad to the recess. The second passivation layer is formed over the first passivation layer and the redistribution layer. The second passivation layer also has an opening that exposes the redistribution layer above the recess. The bump passes through the opening and connects electrically with the redistribution layer above the recess.

Abstract: A semiconductor device having a nonconductive cap layer comprising a first metal element. The nonconductive cap layer comprises a first metal nitride, a first metal oxide, or a first metal oxynitride over conductive lines and an insulating material between the conductive lines. An interface region may be formed over the top surface of the conductive lines, the interface region including the metal element of the cap layer. The cap layer prevents the conductive material in the conductive lines from migrating or diffusing into adjacent subsequently formed insulating material layers. The cap layer may also function as an etch stop layer.

Abstract: Interconnections are formed over an interlayer insulating film which covers MISFETQ1 formed on the principal surface of a semiconductor substrate, while dummy interconnections are disposed in a region spaced from such interconnections. Dummy interconnections are disposed also in a scribing area. Dummy interconnections are not formed at the peripheries of a bonding pad and a marker. In addition, a gate electrode of a MISFET and a dummy gate interconnection formed of the same layer are disposed. Furthermore, dummy regions are disposed in a shallow trench element-isolation region. After such dummy members are disposed, an insulating film is planarized by the CMP method.

Abstract: There is provided a surface treatment method for an electronic part, which uses a metal not containing lead and tin and having excellent solder wettability, is economical and has high reliability. In the surface treatment method for the electronic part in which a soldered part is subjected to a surface treatment of structure of three layers of nickel, palladium and gold, the palladium layer and the gold layer are formed by an electrolytic plating treatment, a thickness of the palladium layer is in a range of 0.007 to 0.1 ?m, a thickness of the gold layer is in a range of 0.003 to 0.02 ?m, and a relation of the thickness of the gold layer<the thickness of the palladium layer is established.

Abstract: A semiconductor integrated circuit device has a first MOS transistor and a second MOS transistor. The first MOS transistor has a first source, a first gate electrode, and a first wiring metal connected to the first source and overlapping the first gate electrode. The second MOS transistor has a second source, a second gate electrode, and a second wiring metal connected to the second source. The first wiring metal of the first MOS transistor and the second wiring metal are positioned so that they do not overlap the second gate electrode.

Abstract: A circuit device is provided in which the bonding reliability of a brazing material such as soft solder is improved. A circuit device of the present invention includes conductive patterns, a bonding material which fixes circuit elements to the conductive patterns, and sealing resin which covers the circuit elements. The circuit device has a structure in which Pb-free solder containing Bi is used as the bonding material. Since the melting temperature of Bi is high in comparison with that of a general solder, the melting of the bonding material is suppressed when the circuit device is mounted. Further, Ag or the like may be mixed into the bonding material in order to enhance the wettability of the bonding material.

Abstract: A semiconductor package includes a substrate formed of a board material, a semiconductor die bonded to the substrate, and an encapsulant on the die. The package also includes an array of external contacts formed as multi layered metal bumps that include a base layer, a bump layer, and a non-oxidizing outer layer. The external contacts are smaller and more uniform than conventional solder balls, and can be fabricated using low temperature deposition processes, such that package warpage is decreased. Further, the external contacts can be shaped by etching to have generally planar tip portions that facilitate bonding to electrodes of a supporting substrate. Die contacts on the substrate can also be formed as multi layered metal bumps having generally planar tip portions, such that the die can be flip chip mounted to the substrate.

Abstract: A semiconductor package includes a substrate formed of a board material, a semiconductor die bonded to the substrate, and an encapsulant on the die. The package also includes an array of external contacts formed as multi layered metal bumps that include a base layer, a bump layer, and a non-oxidizing outer layer. The external contacts are smaller and more uniform than conventional solder balls, and can be fabricated using low temperature deposition processes, such that package warpage is decreased. Further, the external contacts can be shaped by etching to have generally planar tip portions that facilitate bonding to electrodes of a supporting substrate. Die contacts on the substrate can also be formed as multi layered metal bumps having generally planar tip portions, such that the die can be flip chip mounted to the substrate.

Abstract: Disclosed is an Al alloy film for wiring, which consists of, by atom, 0.2 to 1.5% Ge and 0.2 to 2.5% Ni and the balance being essentially Al, wherein a total amount of Ge and Ni is not more than 3.0%. The invention is also directed to a sputter target material having the same chemical composition as that of the Al alloy film.

Abstract: A semiconductor carrier film includes (i) a base film having insulating property, (ii) a barrier layer provided on the base film, the barrier layer including nickel-chrome alloy as a main component, and (iii) a wire layer provided on the barrier layer, the wire layer being made of conductive material including copper, and a ratio of chrome in the barrier layer is 15% to 50% by weight. A semiconductor device is formed by bonding a semiconductor element to the wire layer. The semiconductor carrier film and the semiconductor device are suitable for attaining finer pitches and higher outputs, because insulating resistance between adjacent terminals is less likely to deteriorate then in conventional art even in the environment of high temperature and moisture.

Abstract: In an electronic device comprising a first electrodes consisting of a metal oxide and a second electrode consisting of an aluminum alloy film directly contacted and electrically connected to the first electrode, the contact interface between the aluminum alloy film and the first electrode is constructed so that at least a part of alloy components constituting the aluminum alloy film exist as a precipitate or concentrated layer. This construction enables direct contact between the aluminum alloy film and the electrode consisting of a metallic oxide and allows elimination of a barrier metal in such an electronic device, and manufacturing technology therefor.

Abstract: A columnar bump formed of copper etc. is formed on a wiring film of a semiconductor chip through an interconnected film and an adhesive film in a wafer unit by electrolytic plating in which package formation is possible. An oxidation prevention film is formed of such as gold on an upper surface or a part of the upper surface and side surface. A wet prevention film of such as an oxide film is formed on the columnar bump side as needed. If this bump is soldered to the pad on a packaging substrate, solder gets wet in the whole region of the columnar bump upper surface and only a part of the side surface. Stabilized and reliable junction form can be thus formed. Moreover, since the columnar bump does not fuse, the distance between a semiconductor board and a packaging board is not be narrowed by solder.

Abstract: Conductive paths in an integrated circuit are formed using multiple undifferentiated carbon nanotubes embedded in a conductive metal, which is preferably copper. Preferably, conductive paths include vias running between conductive layers. Preferably, composite vias are formed by forming a metal catalyst pad on a conductor at the via site, depositing and etching a dielectric layer to form a cavity, growing substantially parallel carbon nanotubes on the catalyst in the cavity, and filling the remaining voids in the cavity with copper. The next conductive layer is then formed over the via hole.

Abstract: A method of forming a magneto-resistive memory element includes forming a groove in a layer of insulating material. A liner is formed conformably within the groove and the groove is filled with copper and then planarized. The electrically conductive material is provided an upper surface that is recessed relative to the upper surface of the layer of insulating material. A cap, which can be conductive (e.g., Ta) or resistive (e.g., TiAIN), is disposed over the electrically conductive material and within the groove. A surface of the cap that faces away from the electrically conductive material, is formed with an elevation substantially equal to that of the edge of the liner, or the cap can extend over the liner edge. At least one layer of magneto-resistive material is disposed over a portion of the cap. Advantageously, the cap can protect the copper line from harmful etch processes required for etching a MRAM stack, while keeping the structure planar after CMP.

Abstract: An electrode structure includes a first layer of conductive material and a dielectric layer formed on a surface of the first layer. An opening is formed in the dielectric layer to expose a portion of the surface of the first layer. A binding layer is formed on the dielectric layer and on the exposed portion of the surface of the first layer and a second layer of conductive material is formed on the conductive binding layer. The binding layer can be an oxide and the second layer a conductive material that is diffusible into an oxide. The electrode structure can be annealed to cause conductive material from the second layer to be chemisorbed into the binding layer to improve adhesion between the first and second layers. A programmable cell can be formed by forming a doped glass layer in the electrode structure.

Abstract: Semiconductor devices and methods of forming the semiconductor devices using an HTS (High Temperature Superconductor) layer in combination with a typical diffusion layer between the dielectric material and the copper (or other metal) conductive wiring. The HTS layer includes a superconductor material comprised of barium copper oxide and a rare earth element. The rare earth element yttrium is particularly suitable. For semiconductor devices having other semiconductor circuits or elements above the wiring, a capping layer of HTS material is deposited over the wiring before a cover layer of dielectric is deposited.

Abstract: Described is a method for producing high purity tantalum, the high purity tantalum so produced and sputtering targets of high purity tantalum. The method involves purifying starting materials followed by subsequent refining into high purity tantalum.

Abstract: In an electronic device comprising a first electrodes consisting of a metal oxide and a second electrode consisting of an aluminum alloy film directly contacted and electrically connected to the first electrode, the contact interface between the aluminum alloy film and the first electrode is constructed so that at least a part of alloy components constituting the aluminum alloy film exist as a precipitate or concentrated layer. This construction enables direct contact between the aluminum alloy film and the electrode consisting of a metallic oxide and allows elimination of a barrier metal in such an electronic device, and manufacturing technology therefor.

Abstract: A chemical leadframe roughening process includes cleaning and chemically micro-etching a raw copper leadframe to remove organic material and oxide material from the surface. The surface of the leadframe is then roughened using an organic and peroxide solution, resulting in a finely pitted surface morphology. The roughened leadframe is cleaned to remove organic material, and then is plated with a lead-free plating material (such as a layered plating of nickel-palladium-gold (NiPdAu)) having a reflow temperature higher than the reflow temperature of lead-based solder. The plated leadframe exhibits the desired finely pitted morphology that is believed to provide for greater bonding with the mold compound used to make a finished integrated circuit package, thereby improving the moisture sensitivity level (MSL) performance of the package.