Abstract: Embodiments of apparatus and methods for forming dual metal interconnects are described herein. Other embodiments may be described and claimed.

Abstract: The formation of devices in semiconductor material is provided using an HF/HCL cleaning process. In one embodiment, the method includes forming at least one hard mask overlaying at least one layer of resistive material, forming at least one opening to a working surface of a silicon substrate of the semiconductor device, and cleaning the semiconductor device with a diluted HF/HCL process. The HF/HCL process includes applying a dilute of HF for a select amount of time and applying a dilute of HCL for a specific amount of time. After cleaning with the diluted HF/HCL process, a silicide contact junction is formed in the at least one opening to the working surface of the silicon substrate, and interconnect metal layers are formed.

Abstract: An implantable hermetically sealed microelectronic device and method of manufacture are disclosed. The microelectronic device of the present invention is hermetically encased in a insulator, such as alumina formed by ion bean assisted deposition (“IBAD”), with a stack of biocompatible conductive layers extending from a contact pad on the device to an aperture in the hermetic layer. In a preferred embodiment, one or more patterned titanium layers are formed over the device contact pad, and one or more platinum layers are formed over the titanium layers, such that the top surface of the upper platinum layer defines an external, biocompatible electrical contact for the device. Preferably, the bottom conductive layer is larger than the contact pad on the device, and a layer in the stack defines a shoulder.

Abstract: Provided, is a reliable semiconductor device with a layered interconnect structure that may develop no trouble of voids and interconnect breakdowns, in which the layered interconnect structure comprises a conductor film and a neighboring film as so layered on a semiconductor substrate that the neighboring film is contacted with the conductor film.

Abstract: Metal nanoplates are grown on n-type and p-type semiconductor wafer substrates through galvanic reactions between substantially pure aqueous metal solutions and the substrates. The morphology of the resulting metal nanoplates that protrude from the substrate can be tuned by controlling the concentration of the metal solution and the reaction time of the solution with the semiconductor wafer. Nanoplate size gradually increases with prolonged growth time and the nanoplate thicknesses increases in a unique stepwise fashion due to polymerization and fusion of adjacent nanoplates. Further, the roughness of the nanoplates can also be controlled. In a particular embodiment, Ag nanoplates are grown on a GaAs substrate through reaction with a solution of AgNO3 with the substrate.

Abstract: A semiconductor device includes: a P-type semiconductor layer formed in a surface region of a semiconductor substrate; a first gate insulating film formed on the P-type semiconductor layer; a first gate electrode; and a first source region and a first drain region formed in the P-type semiconductor layer to interpose a region under the first gate electrode in a direction of gate length. The first gate electrode includes: a first silicide film formed on the first gate insulating film and containing nickel silicide having a first composition ratio of nickel to silicon as a main component; a conductive film formed on the first silicide film; and a second silicide film formed on the conductive film and containing nickel silicide having a second composition ratio of nickel to silicon as a main component. The second composition ratio is larger than the first composition ratio.

Abstract: An integrated circuit containing a vertical interconnect that includes a region of interconnect metal continuously surrounding one or more dielectric pillars. The vertical interconnect electrically contacts a top surface of a lower conductive structure. An upper conductive structure contacts a top surface of the vertical interconnect. A process of forming an integrated circuit that includes forming a vertical interconnect that has a region of interconnect metal continuously surrounding one or more dielectric pillars. The vertical interconnect electrically contacts a top surface of a lower conductive structure, and an upper conductive structure contacts a top surface of the vertical interconnect.

Abstract: A semiconductor device including at least one conductive structure is provided. The conductive structure includes a silicon-containing conductive layer, a refractory metal salicide layer and a protection layer. The refractory metal salicide layer is disposed over the silicon-containing conductive layer. The protection layer is disposed over the refractory metal salicide layer. Another semiconductor device including at least one conductive structure is also provided. The conductive structure includes a silicon-containing conductive layer, a refractory metal alloy salicide layer and a protection layer. The refractory metal alloy salicide layer is disposed over the silicon-containing conductive layer. The refractory metal alloy salicide layer is formed from a reaction of silicon of the silicon-containing conductive layer and a refractory metal alloy layer which includes a first refractory metal and a second refractory metal. The protection layer is disposed over the refractory metal alloy salicide layer.

Abstract: The present invention relates to a method for forming self-aligned metal silicide contacts over at least two silicon-containing semiconductor regions that are spaced apart from each other by an exposed dielectric region. Preferably, each of the self-aligned metal silicide contacts so formed comprises at least nickel silicide and platinum silicide with a substantially smooth surface, and the exposed dielectric region is essentially free of metal and metal silicide. More preferably, the method comprises the steps of nickel or nickel alloy deposition, low-temperature annealing, nickel etching, high-temperature annealing, and aqua regia etching.

Abstract: A substrate for device bonding is provided, which enables bonding of a device with high bond strength to an Au electrode formed on a substrate such as aluminum nitride by soldering the device at a low temperature using a soft solder metal having a low melting point such as an Au—Sn-based solder having an Au content of 10% by weight. The substrate for device bonding comprises a substrate having an Au electrode layer formed on its surface and in which (i) a layer composed of a platinum group element, (ii) a layer composed of at least one transition metal element selected from the group consisting of Ti, V, Cr and Co, (iii) a barrier metal layer composed of at least one metal selected from the group consisting of Ag, Cu and Ni and (iv) a solder layer composed of a solder containing Sn or In as a main component are laminated in this order on the Au electrode layer.

Abstract: A method for forming a metal/metal oxide structure that includes forming metal oxide regions, e.g. ruthenium oxide regions, at grain boundaries of a metal layer, e.g., platinum. Preferably, the metal oxide regions are formed by diffusion of oxygen through grain boundaries of the metal layer, e.g., platinum, to oxidize a metal layer thereon, e.g, ruthenium layer. The structure is particularly advantageous for use in capacitor structures and memory devices, such as dynamic random access memory (DRAM) devices.

Abstract: One or more embodiments of the present invention relate to structures obtained by methods (a) for growing a film by an intermixing growth process, or (b) by depositing a film, which film includes chalcogenides of copper and/or silver (but excluding oxides), such as, for example, copper sulfide (CuSX and/or Cu2SX, where 0.7?X?1.3; and X=1.0 for stoichiometric compounds).

Abstract: An interconnect structure that includes a dielectric material having a dielectric constant of about 3.0 or less is provided. This low k dielectric material has at least one conductive material having an upper surface embedded therein. The dielectric material also has a surface layer that is made hydrophobic prior to the formation of the noble metal cap. The noble metal cap is located directly on the upper surface of the at least one conductive material. Because of the presence of the hydrophobic surface layer on the dielectric material, the noble metal cap does not substantially extend onto the hydrophobic surface layer of the dielectric material that is adjacent to the at least one conductive material and no metal residues from the noble metal cap deposition form on this hydrophobic dielectric surface.

Abstract: A semiconductor device is provided, which includes a substrate, an insulator film formed over the substrate, and plural metal wirings with different widths containing copper as a main component and an impurity which is different from copper. The plural metal wirings includes a first metal wiring having a concentration profile where the concentration of the impurity metal increases from the center part of the stacking direction to the surface and the second metal wiring having a concentration profile where the concentration of the impurity metal decreases from the bottom surface of the stacking direction to the surface. Moreover, the width of the second metal wiring may be larger than the width of the first metal wiring.

Abstract: An improved reliability of a junction region between a bonding wire and an electrode pad in an operation at higher temperature is presented. A semiconductor device includes a semiconductor chip provided on a lead frame, which are encapsulated with an encapsulating resin. Lead frames are provided in both sides of the lead frame. A portion of the lead frame is encapsulated with the encapsulating resin to function as an inner lead. The encapsulating resin is composed of a resin composition that contains substantially no halogen. Further, an exposed portion of the Al pad provided in the semiconductor chip is electrically connected to the inner lead via the AuPd wire.

Abstract: A ruthenium film deposition method is disclosed. In one embodiment of the method, a first ruthenium film is deposited by using a PEALD process until a substrate is substantially entirely covered with the first ruthenium film. Then, a second ruthenium film is deposited on the first ruthenium film by using a thermal ALD process having a higher deposition speed than that of the PEALD process. In the method, a ruthenium metal film having a high density is formed in a short time by combining a PEALD process of depositing a ruthenium film at a low deposition speed and a deposition process of depositing a ruthenium film at a higher deposition speed. Accordingly, it is possible to form a ruthenium film having high density, a smooth surface, good adhesiveness, and a short incubation period.

Abstract: A method of manufacturing a non-volatile memory bitcell comprises the steps of depositing a first layer of conductive material on a substrate and patterning and etching the first layer of conductive material to form three non-linearly disposed electrodes. The method also comprises the steps of depositing a first layer of sacrificial material on the electrodes and the substrate and providing an elongate cantilever structure on the first layer of sacrificial material such that the cantilever structure and at least a portion of each electrode overlap each other. The method also includes the steps of depositing a second layer of sacrificial material on the cantilever structure and the first layer of sacrificial material and providing a capping layer on the second layer of sacrificial material and providing holes in the capping layer such that at least a portion of the second layer of sacrificial material is exposed.

Abstract: The embodiments of the invention generally relate to an etching process, and more particularly to an etch processing for improving the yield of dielectric contacts on nickel silicides. An oxygen-free feedgas is used in an etching process to reduce or eliminate residuals, including oxidation and consumption of the silicide layer, at the contact surface.

Abstract: An interconnect structure is provided that has enhanced electromigration reliability without degrading circuit short yield, and improved technology extendibility. The inventive interconnect structure includes a dielectric material having a dielectric constant of about 3.0 or less. The dielectric material has at least one conductive material embedded therein. A noble metal cap is located directly on an upper surface of the at least one conductive region. The noble metal cap does not substantially extend onto an upper surface of the dielectric material that is adjacent to the at least one conductive region, and the noble cap material does not be deposited on the dielectric surface. A method fabricating such an interconnect structure utilizing a low temperature (about 300° C. or less) chemical deposition process is also provided.

Abstract: A method for fabrication a metal interconnect that includes a ruthenium layer and minimizes void formation comprises forming a barrier layer on a substrate having a trench, depositing a ruthenium layer on the barrier layer, depositing an alloy-seed layer on the ruthenium layer, using an electroless plating process to deposit a copper seed layer on the alloy-seed layer, and using an electroplating process to deposit a bulk metal layer on the copper seed layer. The alloy-seed layer inhibits void formation issues at the ruthenium-copper interface and improves electromigration issues. The electroless copper seed layer inhibits the alloy-seed layer from dissolving into the electroplating bath and reduces electrical resistance across the substrate during the electroplating process.

Abstract: A method for forming germano-silicide contacts atop a Ge-containing layer that is more resistant to etching than are conventional silicide contacts that are formed from a pure metal is provided. The method of the present invention includes first providing a structure which comprises a plurality of gate regions located atop a Ge-containing substrate having source/drain regions therein. After this step of the present invention, a Si-containing metal layer is formed atop the said Ge-containing substrate. In areas that are exposed, the Ge-containing substrate is in contact with the Si-containing metal layer. Annealing is then performed to form a germano-silicide compound in the regions in which the Si-containing metal layer and the Ge-containing substrate are in contact; and thereafter, any unreacted Si-containing metal layer is removed from the structure using a selective etch process. In some embodiments, an additional annealing step can follow the removal step.

Abstract: The present invention substantially removes dry etch residue from a dry plasma etch process 110 prior to depositing a cobalt layer 124 on silicon substrate and/or polysilicon material. Subsequently, one or more annealing processes 128 are performed that cause the cobalt to react with the silicon thereby forming cobalt silicide regions. The lack of dry etch residue remaining between the deposited cobalt and the underlying silicon permits the cobalt silicide regions to be formed substantially uniform with a desired silicide sheet and contact resistance. The dry etch residue is substantially removed by performing a first cleaning operation 112 and then an extended cleaning operation 114 that includes a suitable cleaning solution. The first cleaning operation typically removes some, but not all of the dry etch residue. The extended cleaning operation 114 is performed at a higher temperature and/or for an extended duration and substantially removes dry etch residue remaining after the first cleaning operation 112.

Abstract: A method for forming a metal/metal oxide structure that includes forming metal oxide regions, e.g., ruthenium oxide regions, at grain boundaries of a metal layer, e.g., platinum. Preferably, the metal oxide regions are formed by diffusion of oxygen through grain boundaries of the metal layer, e.g., platinum, to oxidize a metal layer thereon, e.g., ruthenium layer. The structure is particularly advantageous for use in capacitor structures and memory devices, such as dynamic random access memory (DRAM) devices.

Abstract: A semiconductor package using Ag or Ag alloy wire which can maintain superior reliability against a noble metal and lower its manufacturing cost is provided. The semiconductor package comprises a semiconductor substrate. A semiconductor chip is attached to the package substrate and has one or more pads which comprise a noble metal. And one or more wires are bonded so as to electrically connect the one or more pads and the package substrate and comprise Ag or Ag alloy.

Abstract: A metallization layer that includes a tantalum layer located on the component, a tantalum silicide layer located on the tantalum layer, and a platinum silicide layer located on the tantalum silicide layer. In another embodiment the invention is a component having a metallization layer on the component. In another embodiment, the metallization layer has a post-annealing adhesive strength to silicon of at least about 100 MPa as measured by a mechanical shear test after exposure to a temperature of about 600° C. for about 30 minutes, and the metallization layer remains structurally intact after exposure to a temperature of about 600° C. for about 1000 hours. The metallization is useful for bonding with brazing alloys.

Abstract: A method and an apparatus are provided in which non-directional and directional metal (e.g. Ni) deposition steps are performed in the same process chamber. A first plasma is formed for removing material from a target; a secondary plasma for increasing ion density in the material is formed in the interior of an annular electrode (e.g. a Ni ring) connected to an RF generator. Material is deposited non-directionally on the substrate in the absence of the secondary plasma and electrical biasing of the substrate, and deposited directionally when the secondary plasma is present and the substrate is electrically biased. Nickel silicide formed from the deposited metal has a lower gate polysilicon sheet resistance and may have a lower density of pipe defects than NiSi formed from metal deposited in a solely directional process, and has a lower source/drain contact resistance than NiSi formed from metal deposited in a solely non-directional process.

Abstract: An article includes a polymeric film having a major surface, a discontinuous layer of a catalytic material on the major surface, and a metal pattern on the catalytic material. The discontinuous layer of catalytic material has an average thickness of less than 200 angstroms. Methods of forming these articles are also disclosed.

Abstract: A semiconductor structure includes first and second conductive lines which cross each other. The second conductive lines are electrically insulated from the first conductive lines via an insulating material. The second conductive lines include first and second sections. First sections are arranged beneath crossing first conductive lines and include a semiconductor material. The second sections are disposed between adjacent first conductive lines and include a metal-semiconductor compound. A method of manufacturing a semiconductor structure involves forming initial second conductive lines, forming first conductive lines and providing a metal-semiconductor compound on an exposed surface of the initial second conductive lines, thereby obtaining second conductive lines. Forming the metal-semiconductor compound is performed after forming the first conductive lines.

Abstract: An integrated circuit (IC) may include a substrate, a first dielectric layer adjacent the substrate, and at least one trench in the first dielectric layer. The IC may also include a metal liner within the at least one trench, and a first conductive region including copper within the at least one trench. A cap layer including metal may be provided on the first conductive region. A second dielectric layer may be over the first conductive region and the cap layer. A dielectric etch stop and diffusion barrier layer may be over the second dielectric layer, and a via may be over the first conductive region and through the second dielectric layer and the cap layer. A diffusion barrier layer may be on sidewalls of the via, and an alloy seed layer including copper and at least one of tantalum, molybdenum, chromium, and tungsten may be over the diffusion barrier.

Abstract: An interconnect includes an opening formed in a dielectric layer. A conductive barrier is deposited in the opening, over which a first conductive layer is deposited. A conductive oxide is deposited over the first conductive layer, and a second conductive layer, formed from the same material as the first conductive layer, is deposited over the conductive liner.

Abstract: In a semiconductor device having a package structure in which lead terminals connected to electrodes on both of the upper and lower surfaces of a semiconductor chip are exposed from both of the upper and lower surfaces and side surfaces of a sealing body formed of resin, electrodes of the semiconductor chip and the lead terminals are connected by Pb-free connection parts each having a configuration of connection layer/stress buffer layer/connection layer. In each connection part, the connection layer is formed of an inter-metallic compound layer having a melting point of 260° C. or higher or Pb-free solder having a melting point of 260° C. or higher, and the stress buffer layer is formed of a metal layer having a melting point of 260° C. or higher and having a function to buffer the thermal stress.

Abstract: A method for making a filed-effect semiconductor device includes the steps of forming a gate electrode on a semiconductor layer composed of a gallium nitride-based compound semiconductor represented by the formula AlxInyGa1?x?yN, wherein x+y=1, 0?x?1, and 0?y?1; and forming a source electrode and a drain electrode by self-alignment using the gate electrode as a mask. A field-effect semiconductor device fabricated by the method is also disclosed.

Abstract: The present invention provides a method for enhancing uni-directional diffusion of a metal during silicidation by using a metal-containing silicon alloy in conjunction with a first anneal in which two distinct thermal cycles are performed. The first thermal cycle of the first anneal is performed at a temperature that is capable of enhancing the uni-directional diffusion of metal, e.g., Co and/or Ni, into a Si-containing layer. The first thermal cycle causes an amorphous metal-containing silicide to form. The second thermal cycle is performed at a temperature that converts the amorphous metal-containing silicide into a crystallized metal rich silicide that is substantially non-etchable as compared to the metal-containing silicon alloy layer or a pure metal-containing layer. Following the first anneal, a selective etch is performed to remove any unreacted metal-containing alloy layer from the structure.

Abstract: An integrated circuit (IC) chip, semiconductor wafer with IC chips in a number of die locations and a method of making the IC chips on the wafer. The IC chips have plated chip interconnect pads. Each plated pad includes a noble metal plated layer electroplated to a platable metal layer. The platable metal layer may be copper and the noble metal plated layer may be of gold, platinum, palladium, rhodium, ruthenium, osmium, iridium or indium.

Abstract: A method of producing electrical contacts having reduced interface roughness as well as the electrical contacts themselves are disclosed herein. The method of the present invention comprises (a) forming an alloy layer having the formula MX, wherein M is a metal selected from the group consisting of Co and Ni and X is an alloying additive, over a silicon-containing substrate; (b) optionally forming an optional oxygen barrier layer over said alloy layer; (c) annealing said alloy layer at a temperature sufficient to form a MXSi layer in said structure; (d) removing said optional oxygen barrier layer and any remaining alloy layer; and optionally (e) annealing said MXSi layer at a temperature sufficient to form a MXSi2 layer in said structure.

Abstract: A conductive material is provided in an opening formed in an insulative material. The process involves first forming a conductive material over at least a portion of the opening and over at least a portion of the insulative material which is outside of the opening. Next, a metal-containing fill material is formed over at least a portion of the conductive material which is inside the opening and which is also over the insulative material outside of the opening. The metal-containing material at least partially fills the opening. At least a portion of both the metal-containing fill material and the conductive material outside of the opening is then removed. Thereafter, at least a portion of the metal-containing fill material which is inside the opening is then removed.

Abstract: A semiconductor integrated circuit device is provided which includes a wire having a diameter equal to or less than 30 ?m, and a connected member molded by a resin. The connected member includes a metal layer including a palladium layer provided at a portion to which said wire is connected. A solder containing Pb as a main composition metal is provided at a portion outside a portion molded by the resin.

Abstract: Provided is a reliable semiconductor device with a layered interconnect structure that may develop no trouble of voids and interconnect breakdowns, in which the layered interconnect structure comprises a conductor film and a neighboring film as so layered on a semiconductor substrate that the neighboring film is contacted with the conductor film.

Abstract: An integrated circuit (IC) may include a substrate, a first dielectric layer adjacent the substrate, and at least one trench in the first dielectric layer. The IC may also include a metal liner within the at least one trench, and a first conductive region including copper within the at least one trench. A cap layer including metal may be provided on the first conductive region. A second dielectric layer may be over the first conductive region and the cap layer. A dielectric etch stop and diffusion barrier layer may be over the second dielectric layer, and a via may be over the first conductive region and through the second dielectric layer and the cap layer. A diffusion barrier layer may be on sidewalls of the via, and an alloy seed layer including copper and at least one of tantalum, molybdenum, chromium, and tungsten may be over the diffusion barrier.

Abstract: A highly reliable semiconductor device having a multilayer structure including an insulating film, an adjacent conductive film, and a main conductive film in which adhesive fractures, voids and disconnections are unlikely to occur. Regarding main constituent elements of the adjacent conductive film and the main conductive film, lattice mismatching is made small, the melting point the adjacent conductive film is set to be not less than 1.4 times that of the main constituent element of the main conductive film, the adjacent conductive film contains at least one different kind of element, the difference between the atomic radius of an added element and that the atomic radius the adjacent conductive film is set to be not more than 10%, and/or bond energy between the added element and silicon (Si) is not less than 1.9 times that of the main constituent element of the adjacent conductive film and silicon (Si).

Abstract: In semiconductor devices, a semiconductor device is provided which is high in reliability while suppressing changes in characteristics such as threshold voltages. In a semiconductor device which has a gate dielectric film above a semiconductor substrate and also has above the gate dielectric film a gate electrode film made of silicon germanium chosen as its main constituent material, or alternatively in a semiconductor device which has beneath the gate dielectric film a channel made of silicon as its main constituent material and which has below the channel a channel underlayer film made of silicon germanium as its main constituent material, a specifically chosen dopant, such as cobalt (Co) or carbon (C) or nitrogen (N), is added to the gate electrode and the channel underlayer film, for use as the unit for suppressing diffusion of germanium in the gate electrode or in the channel underlayer film.

Abstract: Solder ball bond pads and wire bond pads may be selectively coated so that the wire bond bond pads have a thicker gold coating than the solder ball bond pads. This may reduce the embrittlement of solder ball joints while providing a sufficient thickness of gold for the wire bonding process. In general, gold coatings are desirable on electrical contact surfaces to prevent oxidation. However, the thickness of gold which is necessary on solder ball bond pads may be less and excessive gold may be disadvantageous. Thus, by masking the solder ball bond pads during the gold coating of the wire bond bond pads, a differential gold thickness may be achieved which is more advantageous for each application.

Abstract: A method for forming a metal/metal oxide structure that includes forming metal oxide regions, e.g.. ruthenium oxide regions, at grain boundaries of a metal layer, e.g., platinum. Preferably, the metal oxide regions are formed by diffusion of oxygen through grain boundaries of the metal layer, e.g., platinum, to oxidize a metal layer thereon, e.g, ruthenium layer. The structure is particularly advantageous for use in capacitor structures and memory devices, such as dynamic random access memory (DRAM) devices.

Abstract: The present invention provides a structure for a semiconductor device, capable of eliminating the generation of defective products due to poor connection. In the present semiconductor device, an n-type high concentration diffusion layer 2 is selectively formed on the P-type silicon substrate 1, and on the diffusion layer 2, a silicon oxide film 3 is formed as a first interlayer insulating film 3. A silicon plug 4 is disposed on the n-type high concentration diffusion layer 2. On the top end surface of the polysilicon plug 4, a silicide pad 5 is formed in a self-aligning manner such that the width of the silicide pad 5 is larger than that of the polysilicon plug 4. A second interlayer insulating film is formed so as to cover the first interlayer insulating film 3 and the silicide pad 5, and a tungsten plug 7 is disposed on the silicide pad 5. On the second interlayer insulating film, wiring 8, made of an aluminum-copper alloy and connected to the tungsten plug, is formed.

Abstract: A ball grid array for a flip-chip assembly. The ball grid array includes a plurality of bumps bonded between an active surface of a semiconductor die and a top surface of a printed circuit board or any type of substrate carrier. The plurality of balls include at least one bump having a core material and an outer layer. The rigidity of the core material is greater than that of the material of the outer layer. Additionally, the melting temperature of the core material is higher than the material of the outer layer. By this arrangement, the core material with an outer layer provides bumps that are substantially uniform in height. In addition, the balls only procure marks or deformation to the core material during burn-in testing and reflow.

Abstract: A method for making a filed-effect semiconductor device includes the steps of forming a gate electrode on a semiconductor layer composed of a gallium nitride-based compound semiconductor represented by the formula AlxInyGa1-x-yN, wherein x+y=1, 0?x?1, and 0?y?1; and forming a source electrode and a drain electrode by self-alignment using the gate electrode as a mask. A field-effect semiconductor device fabricated by the method is also disclosed.

Abstract: Semiconductor devices exhibiting reduced gate resistance and reduced silicide spiking in source/drain regions are fabricated by forming thin metal silicide layers on the gate electrode and source/drain regions and then selectively resilicidizing the gate electrodes. Embodiments include forming the thin metal silicide layers on the polysilicon gate electrodes and source/drain regions, depositing a dielectric gap filling layer, as by high density plasma deposition, etching back to selectively expose the silicidized polysilicon gate electrodes and resilicidizing the polysilicon gate electrodes to increase the thickness of the metal silicide layers thereon. Embodiments further include resilicidizing the polysilicon gate electrodes including a portion of the upper side surfaces forming mushroom shaped metal silicide layers.

Abstract: A semiconductor triode comprises a gate electrode provided on a channel layer, wherein there is interposed an insulating metal oxide layer between a top surface of the channel layer and the gate electrode.

Abstract: An alloy or composite is deposited in a recess feature of a semiconductor substrate by sputtering an alloy or composite target into a recess, to form a first layer of deposited material. The first layer of deposited material is resputtered at a low angle and low energy, to redeposit the first layer of deposited material onto the bottom of the recess as a second layer of deposited material having a different stoichiometry than that of the first deposited material. In a further embodiment, a sputtering chamber ambient is comprised of argon and nitrogen. In yet a further embodiment, the resputtering step is followed by deposition of at least one layer of material with a different stoichiometry than that of the second deposited layer, to form a “graded” stoichiometry of material deposited in the recess.

Abstract: The present invention is directed to a method of manufacturing silicide used to reduce a contact resistance at a contact of a semiconductor device and a semiconductor device with the silicide manufactured by the same method. The method comprises the steps of: (a) cleaning a semiconductor substrate with a transistor formed thereon, the transistor including a source electrode, a drain electrode and a gate electrode; (b) placing the cleaned semiconductor substrate into a sputter chamber in a deposition equipment, and forming silicide at the same time of depositing a metal film under a state where the semiconductor substrate is heated at a temperature of 450-600° C.; (c) removing residual metal film not used for the formation of silicide; and (d) annealing the semiconductor substrate.