Abstract: This invention relates to contact structures for use in integrated circuits and methods of fabricating contact structures. In one embodiment, a contact structure includes a conductive layer, one or more barrier layers formed above the conductive layer, and a barrier structure encircling the polysilicon layer and the one or more barrier layers. In an alternate embodiment, a contact structure is fabricated by forming a polysilicon layer on a substrate, forming a tungsten nitride layer above the polysilicon layer, and etching the polysilicon layer and the tungsten nitride layer to a level below the surface of a substrate structure. A silicon nitride layer is formed above the tungsten nitride layer, and a ruthenium silicide layer is formed above the silicon nitride layer. The ruthenium silicide layer is then polished.

Abstract: A conductive connection forming method includes forming a first layer comprising a first metal on a substrate and forming a second layer comprising a second metal different from the first metal on the first layer. At least a part of the first layer may be transformed to an alloy material comprising the first and second metals. A conductive connection may be formed to the alloy material. The alloy material may be less susceptible to formation of metal oxide compared to the first metal. By way of example, transforming the first layer may comprise annealing the first and second layer. An exemplary first metal comprises copper, and an exemplary second metal comprises aluminum, titanium, palladium, magnesium, or two or more such metals. The alloy material may be an intermetallic. A conductive connection may be formed to the alloy layer.

Abstract: A leadframe for use with integrated circuit chips comprising a leadframe base made of aluminum or aluminum alloy having a surface layer of zinc; a first layer of nickel on said zinc layer, said first nickel layer deposited to be compatible with aluminum and zinc; a layer of an alloy of nickel and a noble metal on said first nickel layer; a second layer of nickel on said alloy layer, said second nickel layer deposited to be suitable for lead bending and solder attachment; and an outermost layer of noble metal, whereby said leadframe is suitable for solder attachment to other parts, for wire bonding, and for corrosion protection.

Abstract: The wet etch stage of the salicide process normally used to fabricate polysilicon and silicon-based semiconductor transistors may not be appropriate for germanium-based transistors because the wet etch chemicals at such temperatures will dissolve the germanium leaving no source, gate, or drain for the transistor. In embodiments of the invention, nickel is blanket deposited over the source, drain, and gate regions of the germanium-based transistor, annealed to cause the nickel to react with the germanium, and wet etched to remove un-reacted nickel from dielectric regions (e.g., shallow trench isolation (STI) regions) but leave NiGe in the source, gate, and drain regions. The wet etch is a mild oxidizing solution at room temperature.

Abstract: A method of forming a rhodium-containing layer on a substrate, such as a semiconductor wafer, using complexes of the formula LyRhYz is provided. Also provided is a chemical vapor co-deposited platinum-rhodium alloy barriers and electrodes for cell dielectrics for integrated circuits, particularly for DRAM cell capacitors. The alloy barriers protect surrounding materials from oxidation during oxidative recrystallization steps and protect cell dielectrics from loss of oxygen during high temperature processing steps. Also provided are methods for CVD co-deposition of platinum-rhodium alloy diffusion barriers.

Abstract: An interconnection structure preferably including one or more conductors that have a central region filled with an insulator, and a method of fabricating such an interconnection structure for preferably making an electrical connection to the conductor(s). The method preferably includes the steps of depositing and patterning a first insulator over a substrate to form an aperture opening to the substrate; depositing and polishing a first conductor to leave the first conductor in the aperture; depositing and patterning a second insulator to form an opening through the second insulator and a recess in the aperture; depositing one or more second conductors to line the opening and the recess, and to form a central region of the interconnection structure; depositing a third insulator to at least partially fill the central region; and making an electrical connection to the second conductor(s).

Abstract: Disclosed is a layer to electrically connect targets during a circuit edit of an integrated circuit and systems and methods for forming the layer. The layer contains a conductive material, such as gold or another metal, which has been physically deposited by sputtering, thermal evaporation, and other physical deposition technique.

Abstract: An electrode for a semiconductor device superior in die-bonding and wire-bonding characteristics with a submount and its manufacturing method are provided. The electrode is formed by ohmic-contacting the surface of a semiconductor, which comprises a substrate electrode E1 having a layer structure formed on the surface of the semiconductor and a surface electrode E2 formed by covering the surface and/or side face of the substrate electrode E1. The surface electrode is manufactured by a vacuum evaporation system or sputtering system provided with a holder which is tilted with respect to a material of the surface electrode and able to rotate on its axis and orbit the material.

Abstract: A gas sensor having a pn junction including two discrete electrical conductive-type layers, namely, a first semiconductor layer and a second semiconductor layer, disposed in contact with each other. Ohmic electrodes are formed on the respective surfaces of the semiconductor layers. A catalytic layer containing a metallic catalytic component which dissociates hydrogen atom from a molecule having hydrogen atom is formed on one of the ohmic electrodes. The pn junction diode-type gas sensor has a simple constitution, exhibits a small change in diode characteristics with time in long-term service and is capable of detecting a gas concentration of a molecule having a hydrogen atom, for example, H2, NH3, H2S, a hydrocarbon and the like, contained in a sample gas.

Abstract: A semiconductor device includes a middle inter-level insulating film disposed on or above a semiconductor substrate, a conductive layer disposed on the middle inter-level insulating film, and an upper inter-level insulating film disposed on the middle inter-level insulating film and the conductive layer. The upper inter-level insulating film includes first, second, and third wiring grooves distant from each other. The second and third wiring grooves use the conductive layer as their bottoms. The side surfaces of the first, second, and third wiring grooves are covered with in-groove barrier layers. First, second, and third wiring layers are buried in the first, second, and third wiring grooves. The first, second, and third wiring layers are derived from the same wiring film, and have a thickness larger than that of the conductive layer. The second and third wiring layers are electrically connected to the conductive layer.

Abstract: A highly reliable semiconductor device having a multilayer structure including an insulating film, an adjacent conductive film, and a main conductive film in which adhesive fractures, voids and disconnections are unlikely to occur. Regarding main constituent elements of the adjacent conductive film and the main conductive film, lattice mismatching is made small, the melting point the adjacent conductive film is set to be not less than 1.4 times that of the main constituent element of the main conductive film, the adjacent conductive film contains at least one different kind of element, the difference between the atomic radius of an added element and that the atomic radius the adjacent conductive film is set to be not more than 10%, and/or bond energy between the added element and silicon (Si) is not less than 1.9 times that of the main constituent element of the adjacent conductive film and silicon (Si).

Abstract: Disclosed is a method of fabricating a semiconductor memory device including the step of irradiating ultraviolet rays on a metal interconnection at a bonding pad part, so that the metal interconnection can be prevented from being corroded because of a corrodent element in the process of erasing charges stored in a charge storage part. An oxide coating film is formed on the surface of the metal interconnection at the bonding pad part, and ultraviolet rays are irradiated onto the oxide coating film for erasing of charges from the floating gate.

Abstract: A novel contact structure and method for a multilayer gettering contact metallization is provided utilizing a thin layer of a pure metal as the initial layer formed on a semiconductor cap layer. During formation of the contact structure, this thin metal layer reacts with the cap layer and the resulting reacted layer traps mobile impurities and self-interstitials diffusing within the cap layer and in nearby metal layers, preventing further migration into active areas of the semiconductor device. The contact metallization is formed of pure metal layers compatible with each other and with the underlying semiconductor cap layer such that depth of reaction is minimized and controllable by the thickness of the metal layers applied. Thin semiconductor cap layers, such as InGaAs cap layers less than 200 nm thick, may be used in the present invention with extremely thin pure metal layers of thickness 10 nm or less, thus enabling an increased level of integration for semiconductor optoelectronic devices.

Abstract: A trench MOSFET is formed in a structure which includes a P-type epitaxial layer overlying an N+ substrate. A trench is formed in the epitaxial layer. A deep implanted N layer is formed below the trench at the interface between the substrate and the epitaxial layer, and N-type dopant is implant through the bottom of the trench to form an N region in the epitaxial layer below the trench but above and separated from the deep N layer. The structure is heated to cause the N layer to diffuse upward and the N region to diffuse downward. The diffusions merge to form a continuous N-type drain-drift region extending from the bottom of the trench to the substrate. Alternatively, the drain-drift region may be formed by implanting N-type dopant through the bottom of the trench at different energies, creating a stack of N-type regions that extend from the bottom of the trench to the substrate.

Abstract: A method of manufacturing a semiconductor device having an improved ohmic contact system. The improved ohmic contact system comprises a thin reactive layer of platinum deposited on a portion of the base layer. The improved ohmic contact system further comprises a thick refractory layer of titanium or other suitable material deposited on the thin reactive layer. Both the reactive layer and the refractory layer are substantially free of gold. The improved ohmic contact system and method for forming the same eliminate base contact punchthrough on high performance semiconductor devices, such as heterojunction bipolar transistors, minimize raw material costs, and decrease manufacturing costs.

Abstract: The use of an intermetal dielectric (IMD) layer and an organic etch-stop layer are disclosed in forming a dual damascene in order to reduce the RC delay and the overall dielectric constant of the damascene interconnect. The disclosed IMD layer is an FSG and the etch-stop layer is an organic spin-on-glass (SOG). A dual damascene structure utilizing the IMD layer and the organic etch-stop layer is also disclosed.

Abstract: A semiconductor wafer provided with columnar electrodes which have plated nickel, palladium, and gold films successively formed at the top thereof, or have a plated solder film at their top. The semiconductor wafer can be preferably used for producing a chip-sized semiconductor device provided with columnar electrodes to which an external connection terminal, such as a solder ball, is to be bonded. Methods of producing the semiconductor wafer and device by use of plating are also disclosed.

Abstract: Metal films (for instance, gold films or palladium films) to constitute bumps are formed on a metal base by electrolytic plating. Then, a circuit wiring including inner leads is formed by electrolytic plating with a metal so that the inner leads are connected to the respective metal films.

Abstract: An integrated circuit device, and a method of manufacturing the same, comprises an epitaxial nickel silicide on (100) Si, or a stable nickel silicide on amorphous Si, fabricated with a cobalt interlayer. In one embodiment the method comprises depositing a cobalt (Co) interface layer between the Ni and Si layers prior to the silicidation reaction. The cobalt interlayer regulates the flux of the Ni atoms through the cobalt/nickel/silicon alloy layer formed from the reaction of the cobalt interlayer with the nickel and the silicon so that the Ni atoms reach the Si interface at a similar rate, i.e., without any orientation preference, so as to form a uniform layer of nickel silicide. The nickel silicide may be annealed to form a uniform crystalline nickel disilicide. Accordingly, a single crystal nickel silicide on (100) Si or on amorphous Si is achieved wherein the nickel silicide has improved stability and may be utilized in ultra-shallow junction devices.

Abstract: A process is described for forming a common input-output (I/O) site that is suitable for both wire-bond and solder bump flip chip connections, such as controlled-collapse chip connections (C4). The present invention is particularly suited to semiconductor chips that use copper as the interconnection material, in which the soft dielectrics used in manufacturing such chips are susceptible to damage due to bonding forces. The present invention reduces the risk of damage by providing site having a noble metal on the top surface of the pad, while providing a diffusion barrier to maintain the high conductivity of the metal interconnects. Process steps for forming an I/O site within a substrate are reduced by providing a method for selectively depositing metal layers in a feature formed in the substrate. Since the I/O sites of the present invention may be used for either wire-bond or solder bump connections, this provides increased flexibility for chip interconnection options, while also reducing process costs.

Abstract: A leadframe for use with integrated circuit chips, comprising a leadframe base made of aluminum or aluminum alloy having a surface layer of zinc; a first layer of nickel on said zinc layer, said first nickel layer deposited to be compatible with aluminum and zinc; a layer of an alloy of nickel and a noble metal on said first nickel layer; a second layer of nickel on said alloy layer, said second nickel layer deposited to be suitable for lead bending and solder attachment; and an outermost layer of noble metal, whereby said leadframe is suitable for solder attachment to other parts, for wire bonding, and for corrosion protection.

Abstract: This invention provides a semiconductor device comprising gate insulating films 13, 21 formed on the main surface of a silicon substrate 11; gate electrodes 14, 22 consisting of polycrystalline silicon; and a high-density doped layer 17, wherein a part of the side of the gate electrode 22 is electrically connected with the high-density doped layer via a metal silicide layer 23.

Abstract: A MOSFET semiconductor device includes a substrate, a gate electrode, a gate oxide. first and second sets of sidewall spacers and nickel suicide layers. The gate oxide is disposed between the gate electrode and the substrate, and the substrate includes source/drain regions. The gate electrode has first and second opposing sidewalls, and the first set of sidewall spacers are formed undoped silicon oxide and are respectively disposed adjacent the first and second sidewalls. The second set of sidewall spacers are formed from silicon nitride and are respectively disposed adjacent the first set of sidewall spacers. The nickel silicide layers are disposed on the source/drain regions and the gate electrode. The second set of sidewall spacers being formed from undoped silicon oxide prevents the formation of nickel silicide on the second set of sidewall spacers. A method of manufacturing the semiconductor device is also disclosed.

Abstract: A semiconductor device includes a semiconductor substrate, a first interlayer dielectric film covering the semiconductor substrate, a second interlayer dielectric film covering the first interlayer dielectric, an opening having an upper-layer opening penetrating the second interlayer dielectric film, and a lower-layer opening penetrating the first interlayer dielectric film down to the surface of the semiconductor substrate and being connected to the upper-layer opening. The lower-layer opening being arranged such that diameter of the lower-layer reduces gradually from the upper-layer opening toward the semiconductor substrate. A conductive film covering at least the bottom surface of the lower-layer opening and side walls of the lower-layer and upper-layer openings.

Abstract: An integrated circuit and manufacturing method therefor is provided for an integrated circuit on a semiconductor substrate grated circuit having a semiconductor device. A dielectric layer is on the semiconductor substrate and has an opening provided therein. A barrier layer lines the opening, and a first conductor core fills the opening over the barrier layer. A second dielectric layer is formed on the first dielectric layer and has a second channel and via opening provided therein. A shunt layer is in the via opening above the conductor core. A barrier layer lines the second channel and via opening over the shunt layer and the second dielectric layer. A conductor core fills the second channel and via opening over the barrier layer and the first conductor core to form the second channel and via.

Abstract: An electronic semiconductor device comprising a semiconductor base deposited on a semiconductor substrate by means of molecular beam epitaxy and source, drain and gate disposed on the base in a spaced relationghip to each other, the source and the drain comprising Pd/barrier/Au layers with the palladium layer being in contact with the device. The device is fabricated conventionally except the heat treating is at above about 170° C. for ¼-10 hours sufficient for the palladium layer to react with the base yielding reduced contact and access resistances and a narrower spacing between source and drain.

Abstract: A method for fabricating an interconnect with high aspect ratio contact members is provided. The interconnect is adapted to make electrical connections with a semiconductor component, such as a die, a wafer, or a chip scale package for testing. The method includes providing a substrate with projections, and forming a first conductive layer on the projections and substrate. The first conductive layer is then patterned using a resist mask having a thickness greater than a height of the projections. The resist mask can be a thick film resist that includes an epoxy resin, an organic solvent and a photo initiator. A second conductive layer is then formed on the projections, and patterned using a second resist mask having a thickness less than the height of the projections. Each contact member includes a projection with a tip portion having an exposed portion of the first conductive layer, and with a portion of the second conductive layer providing an electrical path to the projection.

Abstract: A semiconductor integrated circuit device is implemented by circuit components and a multi-layered wiring structure, and titanium nitride is used for a part of the integrated circuit such as a conductive plug, an accumulating electrode and a conductive line, wherein the titanium nitride layer is laminated on a titanium silicide layer so as to absorb thermal stress due to the titanium nitride layer.

Abstract: The crude Ti particles prepared by molten salt electrolysis or Iodide method are classified into each particle diameter according to contents of impurities, and the crude Ti particles having a desired particle diameter are selected from the crude Ti particles classified depending on each particle diameter. Otherwise, the crude Ti particles are acid-treated. Then they are electron-beam-melted. Through the above production process, there is prepared a highly purified Ti material having an oxygen content of not more than 350 ppm, Fe, Ni and Cr contents of not more than 15 ppm each, Na and K contents of not more than 0.5 ppm each, a reduction of area as a material characteristic of not less than 70%, and a thermal conductivity of not less than 16 W/m K. In short, the highly purified Ti material satisfying high purity, good processability and good thermal conductivity can be obtained.

Abstract: A monollithic CMOS integrated device formed in silicon carbide and method of fabricating same. The CMOS integrated device includes a layer of silicon carbide of a first conductivity type with a well region of a second conductivity type formed in the layer of silicon carbide. A MOS field effect transistor is formed in the well region and a complementary MOS field effect transistor is formed in the silicon carbide layer. The method of fabrication of CMOS silicon carbide includes formation of an opposite conductivity well region in a silicon carbide layer by ion implantation. Source and drain contacts are also formed by selective ion implantation in the silicon carbide layer and the well region. A gate dielectric layer is formed by deposition and reoxidation. A gate electrode is formed on the gate dielectric such that a channel region is formed between the source and the drain when a bias is applied to the gate electrode.

Abstract: A chip-type multi-layered electronic part in which terminal electrodes are prevented from oxidization when the electrical part is joined with a substrate, so that superior electrical bonding between the terminal electrodes and internal electrodes can be attained. Terminal electrodes 7 connected to internal electrodes 1 contain silver and palladium as the main ingredients in the weight ratio in a range of from 7:3 to 3:7, and further contain boron in a range of from 0.1 weight percent to 1.0 weight percent added to the main ingredients of 100 weight percent.

Abstract: A process for the formation of metal salicide regions and metal salicide exclusion regions in an integrated circuit (IC) that requires a minimum number of steps and is compatible with standard MOS processing techniques. In the process, an IC structure is first provided. The IC structure includes a plurality of MOS transistor structures with exposed silicon surfaces, such as source regions, drain regions and polysilicon gates. A metal layer (e.g., cobalt, titanium, tantalum, nickel or molybdenum) is then deposited over the IC structure, followed by the formation of a photoresist masking layer on those MOS transistor structures where metal salicide regions are to be formed. The metal layer from those MOS transistor structures where metal salicide exclusion regions are to be formed is then removed, followed by stripping of the photoresist masking layer from those MOS transistor structures where metal salicide regions are to be formed.

Abstract: Integrated circuit devices produced by a method in which devices are formed and packaged at the wafer scale. The integrated circuit device includes bond pads on a first side thereof, a layer of glass adhesively affixed to the first side, a layer of sealant covering the second side and edges thereof, and a metallization pattern on the layer of glass connected via an array of contact holes to the bond pads on the integrated circuit device. The device is advantageously formed with an etchable glass package and palladium metallization pattern.

Abstract: Certain embodiments of the present invention relate to a method for manufacturing a MOS field effect transistor in which a silicon-containing layer can be readily formed over source/drain regions. A polycrystal silicon layer (amorphous silicon layer) 17 is formed over the entire surface of a p type silicon substrate 11 by a CVD method. Then, the polycrystal silicon layer (amorphous silicon layer) 17, the polycrystal silicon layer 19, the sidewall dielectric layers 25a and 25b, and the field oxide layers 27a and 27b are polished by a CMP method. As a result, the polycrystal silicon layer (amorphous silicon layer) 17a is isolated from the polycrystal silicon layer 19 by the sidewall dielectric layer 25a. Also, the polycrystal silicon layer (amorphous silicon layer) 17b is isolated from the polycrystal silicon layer 19 by the sidewall dielectric layer 25b.

Abstract: The present invention provides a method for forming a substantially carbon- and oxygen-free conductive layer, wherein the layer can contain a metal and/or a metalloid material. According to the present invention, a substantially carbon- and oxygen-free conductive layer is formed in an oxidizing atmosphere in the presence of an organometallic catalyst using, for example, a chemical vapor deposition process. Such layers are particularly advantageous for use in memory devices, such as dynamic random access memory (DRAM) devices.

Abstract: The integrated semiconductor memory configuration has a semiconductor body in which selection transistors and storage capacitors are integrated. The storage capacitors have a dielectric layer configured between two electrodes. At least the upper electrode is constructed in a layered manner with a platinum layer, that is seated on the dielectric layer, and a thicker, base metal layer lying above the platinum layer.

Abstract: A semiconductor memory device includes: a capacitor formed on a substrate and including a lower electrode, a dielectric film and an upper electrode; a selection transistor formed at the substrate; an electrically conductive plug for providing electrical connection between the selection transistor and the capacitor; and a diffusion barrier film provided between the electrically conductive plug and the lower electrode of the capacitor. The diffusion barrier film is a TaxSi1−xNy film or a HfxSi1−xNy film (where 0.2<x<1 and 0<y<1). The lower electrode includes an Ir film and an IrO2 film which are sequentially formed.

Abstract: Methods and apparatus for depositing films on semiconductor wafers in chemical vapor deposition processes employing a catalyst to provide one or more activated gases to reduce the surface temperature of the semiconductor wafer needed to form the film thereon. The activated gas precursors can include hydrogen or hydrogen-bearing gases. The catalysts can be selected from ruthenium, rhodium, palladium, osmium, iridium, platinum, gold, silver, mercury, rhenium, copper, tungsten, and combinations thereof.

Abstract: Disclosed is a method for producing semiconductor elements including a metal layer (10) configured on a semiconductor substrate (5). The inventive method consists of the following steps: a silicon layer (15) is deposited on a metal layer (10); an etch mask is applied in order to structure the silicon layer (1%); the silicon layer is selectively etched (15) using the etch mask (25); and the metal layer (10) is structured in an etching process using a selectively etched silicon layer (15) as a hard mask.

Abstract: A layer comprising cobalt (Co) is formed on a p+ layer by vapor deposition, and layer comprising gold (Au) is formed thereon. The two layers are alloyed by a heat treatment to form a light-transmitting electrode. The light-transmitting electrode therefore has reduced contact resistance and improved light transmission properties, and gives a light-emitting patten which is stable over a long time. Furthermore, since cobalt (Co) is an element having a large work function, satisfactory ohmic properties are obtained.

Abstract: A dielectric film (110) is formed overlying a semiconductor device substrate (10). A dielectric post (204) having an outer peripheral boundary having sidewalls is formed over the dielectric film (110). A first conductive film (402) is deposited at least along the sidewalls of the dielectric post (204) to form a lower electrode. A capacitor dielectric film (1801) is deposited on the first conductive film, and a upper electrode (1802) is formed on the capacitor dielectric film (1801).

Abstract: The present invention is directed toward the formation of implanted thermally and electrically conductive structures in a dielectric. An electrically conductive structure, such as an interconnect, is formed through ion implantation into several levels within a dielectric layer to penetrate into an electrically conductive region beneath the dielectric layer, such as a semiconductor substrate. Ion implantation continues in discreet, overlapping implantations of the ions from the electrical conductive region up to the top of the dielectric layer so as to form a continuous interconnect. Structural qualities achieved by the method of the present invention include a low interconnect-conductive region resistivity and a low thermal-cycle stress between the interconnect and the dielectric layer in which the interconnect has been implanted.

Abstract: A semiconductor substrate adapted to giga-scale integration (GSI) comprises a support, at least the surface of which is made of semiconductor, an electroconductive material layer, an insulating layer and a semiconductor layer arranged sequentially in the above order. The electroconductive material layer has at least in part thereof an electroconductive reacted layer obtained by causing two metals, a metal and a semiconductor, a metal and a metal-semiconductor compound, a semiconductor and a metal-semiconductor compound, or two metal-semiconductor compounds to react each other. An electroconductive reaction terminating layer that is made of a material that does not react with the reacted layer is arranged between the reacted layer and the insulating layer or the support.

Abstract: In a trench capacitor type semiconductor memory device including a semiconductor substrate having a trench and first and second impurity diffusion source/drain regions, a capacitor electrode buried in the trench, and a substrate-side capacitor electrode and a capacitor insulating layer within the semiconductor substrate and adjacent to a lower portion of the capacitor electrode, a buried insulating layer is formed between the semiconductor substrate and an upper portion of the capacitor electrode. The buried insulating layer is thicker than the capacitor insulating layer. However the buried insulating layer on a surface of the second impurity diffusion source/drain region is thin, or in direct contact with the capacitor electrode. A silicide layer is formed on the second impurity diffusion source/drain region and the capacitor electrode.

Abstract: An article comprising a metal circuit and/or a heat-radiating metal plate formed on a ceramic substrate, wherein the metal circuit and/or the heat-radiating metal plate comprise either (1) the following first metal-second metal bonded product, wherein the first metal and the second metal are different, or (2) the following first metal-third metal-second metal bonded product, and wherein in (1) and (2), the first metal is bonded to the ceramic substrate; first metal: a metal selected from the group consisting of aluminum (Al), lead (Pb), platinum (Pt) and an alloy containing at least one of these metal components; second metal: a metal selected from the group consisting of copper (Cu), silver (Ag), gold (Au), aluminum (Al) and an alloy containing at least one of these metal components; and third metal: a metal selected from the group consisting of titanium (Ti), nickel (Ni), zirconium (Zr), molybdenum (Mo), tungsten (W) and an alloy containing at least one of these metal components.

Abstract: A leadframe having the desirable features of palladium plated leadframes, such as compatibility with both wire bonding and solder reflow, as well as good adhesion to molding compounds is provided by plating the interior lead frame portions with one microinch of palladium and the external leads which contact solder with three microinches of palladium. A low cost method for fabricating the leadframe based on a unique combination of proven processes is provided.

Abstract: An ohmic electrode structure includes an n-InxGa1−xAs layer where 0<x≦1; a Pt or Pd layer provided on the n-InxGa1−xAs layer; and at least one metal layer provided on the Pt or Pd layer. A semiconductor device includes a substrate; a first semiconductor layer having a p-type conductivity provided on the substrate; a second semiconductor layer having an n-type conductivity provided on the substrate; an ohmic contact layer provided on the first semiconductor layer; a barrier layer provided on the second semiconductor layer; a first electrode provided on the ohmic contact layer; and a second electrode provided on the barrier layer. The ohmic contact layer and the barrier layer are each formed of a material selected from the group consisting of Pt and Pd.

Abstract: A lead frame lead and method of fabrication of the leadframe. A leadframe is formed from one of copper or copper-based material having a layer of an alloy of palladium and nickel and a coating of palladium formed over the alloy on the leadframe. The coating of palladium is from about 3 to about 10 microinches and preferably about 3 microinches. The palladium/nickel layer is from about 10 to about 40 microinches and preferably about 10 microinches and is an alloy having from about 40 to about 90 percent by weight nickel and the remainder essentially palladium. A preferred ratio is 75 percent by weight nickel and 25 percent by weight palladium. A semiconductor device is fabricated by providing a copper or copper-based leadframe and forming a layer of the palladium/nickel alloy over the entire leadframe followed by a palladium layer thereover while maintaining the assembly temperature below about 180 degrees C during subsequent device assembly.

Abstract: An electrode substrate comprises a backing substrate carrying thereon a metal electrode layer and/or a recording layer, the layer or layers having a smooth surface area with a surface roughness of less than 1 nm by more than 1 &mgr;m2. The smooth surface of the metal electrode layer and/or the recording layer is formed by firstly forming the layer on another substrate having a corresponding smooth surface and then peeling another substrate off the layer after the layer is bonded to the surface of the backing substrate, whereby the smooth surface profile of another substrate is transferred to the surface of the layer formed on the backing substrate.

Abstract: A lead frame plating method including the steps of (a) forming an intermediate layer on the upper surface of a metal substrate, (b) submerging the metal substrate into a plating solution, and (c) forming a passive layer to a thickness of 0.01 to 1.5 microinches on the upper surface of the intermediate layer by applying a modulated current to the plating solution and the metal substrate.