Abstract: Disclosed is a low cost contact and interconnect layer and method for fabricating the same. A contact via is opened within an insulating layer, exposing a circuit node (e.g., transistor active area within a semiconductor substrate). The via is filled with a chemical vapor deposited (CVD) titanium silicide layer, forming electrical contact with the circuit node. The silicide layer may simultaneously form the interconnect layer for one embodiment. In other embodiments, the interconnect layer may comprise a metal strap over the titanium silicide layer, or a metal layer over an etched-back titanium silicide plug in the contact via. For any of these embodiments, the contact via may be opened after the formation of interconnect trenches, the via extending from the bottom of a trench to the circuit node. CVD provides good step coverage of the via within the trench, despite the higher aspect ratio. The interconnect layer is deposited and etched back, such that the interconnect lines are defined by the trenches.

Abstract: A method for use in the fabrication of semiconductor devices includes forming a layer of nitridated cobalt on a surface including silicon. A film cap including titanium is formed over the layer of cobalt and a thermal treatment is performed to form cobalt silicide from the layer of cobalt and the silicon. Further, a layer of cobalt or nickel may be formed over a titanium film on a surface including silicon. The titanium film is formed in an atmosphere including at least one of nitrogen and oxygen and a thermal treatment is performed for reversal and silicidation of the titanium film and the layer of cobalt or nickel to form cobalt silicide or cobalt nickel. The methods may be used for silicidation of a contact area, in forming a polycide line, or in use for other metal silicidation applications.

Abstract: A lead structure is provided in a semiconductor device, having a body of a lead having at least a part of which is in contact with an adhesive which bonds with an insulation tape, and a protection layer selectively provided on the body of the lead so that the protection layer coats at least the part of the body in contact with the adhesive to completely isolate the body of the lead from the adhesive, to prevent an ion migration of a material of the body and also to prevent leakage of currents from and into the body of the lead.

Abstract: A thin-film microstructure sensor includes a substrate having an insulation layer. A thin-film platinum temperature-sensitive resistor is provided on the insulation layer of the substrate, the thin-film platinum temperature-sensitive resistor comprising a platinum layer, the platinum layer having a maximum crystal grain size above a reference grain size of 800 .ANG.. The thin-film platinum temperature-sensitive resistor is formed by a sputtering process to provide a temperature coefficient of resistance TCR above a reference TCR level of 3200 ppm.

Abstract: A dual damascene process using selective tungsten chemical vapor deposition is provided for forming composite structures for local interconnects comprising line trenches with contact holes, and composite structures for intermetal interconnects comprising line trenches with via holes. It is shown that by forming a seed layer in judiciously selected portions of the dual damascene structure and depositing tungsten selectively in one step, contact holes and via holes can be formed free of voids and key-holes.

Abstract: A gallium nitride-based III-V Group compound semiconductor device has a gallium nitride-based III-V Group compound semiconductor layer provided over a substrate, and an ohmic electrode provided in contact with the semiconductor layer. The ohmic electrode is formed of a metallic material, and has been annealed.

Abstract: A method of controlling stresses in thin films that are deposited over semiconductor device substrates. During anneal process steps, grain growth of the film creates stresses in that can damage or destroy it. The stresses lead to warping and bowing and ultimately to film cracking which undermines desired low resistivity. The present invention imparts thermal stability to thin films by grain boundary stuffing (GBS) of preselected elements that resist film grain changes that cause the stresses. GBS implants the elements into the thin film at desired depths, but above the film-substrate interface, sufficient to prevent or lessen destructive grain growth. GBS provides for structural film stability required during severe thermal cycles that occur during subsequent processing of semiconductor devices.

Abstract: In a semiconductor chip for Si chip based liquid crystal having insulating films and interconnection layers formed on a semiconductor substrate, a thin interconnection layer made of TiN/Ti having strong erosion resistance is formed on an uppermost interlayer insulating film having a flat surface to substantially expose the thin uppermost interconnection layer to the surface of the chip, the uppermost insulating film is covered with a protection film made of p-SiN and a thin insulating film having a mirror-like flat surface is formed on the uppermost interconnection layer.

Abstract: It is intended to provide an electronic material which permits not only PZT but also SBT requiring high-temperature annealing to be used as the material of a dielectric film of a dielectric capacitor in vertical alignment with a transistor so as to connect the lower electrode of the dielectric capacitor to a diffusion layer of the transistor with a Si or W plug; its manufacturing method; and a ferroelectric capacitor and nonvolatile memory. There is also provided a semiconductor device permitting greater freedom in selecting the process temperature and time in a later step subsequent to formation of the plug. Used as the material of the lower electrode of the dielectric capacitor is a material expressed by the composition formula Pd.sub.a (Rh.sub.100-x-y-z Pt.sub.x Ir.sub.y Ru.sub.z).sub.b O.sub.c where a, b, c, x, y and z are composition ratios in atomic %) in which the composition ratios satisfy 70.gtoreq.a.gtoreq.20, 40.gtoreq.b.gtoreq.10, 60.gtoreq.c.gtoreq.15, a+b+c=100, 100>x.gtoreq.0, 100>y.

Abstract: A method for selective conductivity etching of a silicon carbide (SiC) semiconductor includes forming a p-type SiC layer on a substrate layer, forming an n-type SiC layer on the p-type SiC layer, and photoelectrochemically etching selected portions of the n-type SiC layer by applying a bias voltage to the n-type SiC layer in a hydrofluoric acid (HF) solution while exposing the layer to a pattern of UV light. The bias potential is selected so that the n-type SiC layer will photo-corrode and the p-type SiC layer will be inert and act as an etch stop. The light pattern exposure of the n-type SiC layer may be done by applying a photolithographic mask to the layer, by projecting a collimated light beam through a patterned mask, or by scanning with a focused micrometer-sized laser beam on the semiconductor surface.

Abstract: An iridium oxide local interconnect method for a ferroelectric memory cell includes the steps of forming a conductive layer that extends from a source/drain contact of the transistor proximate to an electrode contact of the ferroelectric capacitor and forming an iridium oxide local interconnect extending from the source/drain contact of the transistor to the electrode contact of the ferroelectric capacitor. The conductive layer is laterally terminated not less than one-half micron from the electrode contact of the ferroelectric capacitor. The conductive layer can include an upper iridium layer and a bottom titanium nitride layer, or can include a single layer of completely reacted titanium nitride. After the local interconnect is formed a top oxide layer is deposited. A late recovery anneal is then performed in oxygen at an elevated temperature to rejuvenate the electrical characteristics of the ferroelectric capacitor. Finally, a bit line contact is opened and metalized.

Abstract: A method for manufacturing a lead frame includes degreasing and activating the surface of a metal sheet, providing the plating solution containing nickel(II) sulfamate tetrahydrate, (Ni(H.sub.2 NSO.sub.3).sub.2.4H.sub.2 O), manganese(II) sulfamate tetrahydrate (Mn(H.sub.2 NSO.sub.3).sub.2.4H.sub.2), nickel (II) chloride hexahydrate (NiCl.sub.2.6H.sub.2 O) and boric acid, plating the metal sheet in the plating solution to form a Ni--Mn alloy layer, and forming a Pd or Pd alloy layer on the Ni--Mn alloy layer.

Abstract: Integrated circuit chips having large regions of different device density and topography are susceptible to local processing variations which give rise to systematic failures affecting some circuit regions and not others. Over-simplified test structures cannot signal these failures during processing. Memory chips have large regions of storage cell arrays serviced by sizeable peripheral regions consisting of logic circuits. The device density and configuration in each of these regions on the chip are quite different. During processing steps these regions present differently to the process agents such as chemical etchants and plasmas producing in local variations of processing rates occur which result in systematic under processing in one region or over processing in another. Memory chips are particularly prone to such variations and also lend themselves well to the design of product specific test structures for flagging these aberrations.

Abstract: An iridium layer (16) is formed on an inter-layer insulation film (12) and in an opening (14). The iridium layer (16) is constituted with a part to be a lower electrode (16a) of a capacitor and a part to be a wiring (16b) for coming into contact with a drain zone (6). On part of the lower electrode (16a) of the iridium layer (16) is formed a ferroelectric layer (18) made of PZT on which is further formed an iridium layer (20) as an upper electrode. Since the melting point of iridium is higher than that of aluminum, there is no possibility of iridium melting even if heat treatment is carried out after forming the iridium layer (16). Since reactivity between iridium and silicon is low, unnecessary silicon compound is not produced on the interface to provide favorable contact.

Abstract: A high conductivity interconnect structure is formed by electroplating or electroless plating of Cu or a Cu-base alloy on a seed layer comprising an alloy of a catalytically active metal, such as Cu, and a refractory metal, such as Ta. The seed layer also functions as a barrier/adhesion layer for the subsequently plated Cu or Cu-base alloy. Another embodiment comprises initially depositing a refractory metal barrier layer before depositing the seed layer.

Abstract: By treating the silicon-oxide insulating layer of a semiconductor device with an aqueous metal-salt solution of a metal of an ion radius of less than 0.110 nm, for example, Sc, La or Zr, before a platinum electrode layer is provided on the insulating layer, the platinum layer shows excellent adhesive properties.

Abstract: In a semiconductor memory device, a tantalum silicon nitride film or hafnium silicon nitride film is provided, as a diffusion barrier layer, between a polysilicon plug which electrically connects a source/drain region to a lower platinum electrode of a capacitor, formed on a silicon substrate, and the lower platinum electrode.The tantalum silicon nitride film has a composition of Ta.sub.X Si.sub.1-X N.sub.Y wherein 0.75 .ltoreq.X.ltoreq.0.95 and 1.0 .ltoreq.Y.ltoreq.1.1.The hafnium silicon nitride film has a composition of Hf.sub.X Si.sub.1-X N.sub.Y wherein 0.2<X<1.0 and 0<Y<1.0.

Abstract: A thin-film electron emitter device is provided with a multilayer structure including upper and lower electrodes with an insulative or dielectric layer being sandwiched therebetween. The upper or "top" electrode is itself formed as a multilayer structure. For example, in one embodiment, the upper electrode is formed as a three layer lamination of an interface layer formed on the insulative layer, an intermediate or "middle" layer stacked on the interface layer and a surface layer stacked on or above the middle layer. The middle layer is made of a chosen material which is greater in sublimation enthalpy than the surface layer and yet less than the interface layer. When appropriate, the surface layer may be omitted providing two-layer structure rather than the three-layer structure.

Abstract: A layered structure is described incorporating a noble metal silicide, a noble metal and an oxygen-rich barrier layer between the noble metal silicide and noble metal. A silicon-contributing substrate may also be present in addition to or without the noble metal silicide. The invention overcomes a problem in fabricating capacitors containing high-epsilon dielectric materials or ferroelectric memory elements containing ferroelectric material, namely that silicon diffuses through the electrode in one direction and oxygen diffuses through the electrode in the other direction during the high temperature (400-700.degree. C.) deposition and processing of the dielectric.

Abstract: A semiconductor memory device includes a memory cell capacitor for storing information, wherein the memory cell capacitor includes a capacitor insulation film of a double oxide on a lower electrode. The lower electrode has a layered structure of Ir/IrO.sub.2 /Ir or Ru/RuO.sub.2 /Ru acting as a diffusion barrier of oxygen or Pb. Further, the use of a Pt--Ir alloy is disclosed for the lower electrode.

Abstract: The invention relates to a process of forming a semiconductor structure. The process includes patterning a conductive layer with a top surface and opposing sides over an area of a semiconductor substrate, depositing a dielectric layer over the conductive layer, and etching the dielectric layer to form spacer portions adjacent the sides of the conductive layer and to expose the top surface and a portion of the conductive layer. The process may be used to form salicides wherein the thickness of the silicide layer of the conductive layer is greater than the thickness of the silicide layer in the diffusion region of a device. The invention also relates to a semiconductor device that includes a conductive layer with opposing side portions over an active area of a semiconductor substrate and a dielectric spacer adjacent to less than the entire portion of a side portion of the conductive layer.

Abstract: A semiconductor device in which mutual diffusion of doped impurities occurring through an upper silicide electrode layer is prevented. A silicide electrode layer is doped with both the same degree of p-type impurities as the concentration of p-type impurities of the lower gate electrode layer and the same degree of n-type impurities as the concentration of n-type impurities. As a result, the concentration of doped impurities of the gate electrode layer is balanced at the two sides of the interface of the pMOS side and nMOS side. Therefore, heat diffusion caused by subsequent heat treatment is prevented and the problem of mutual diffusion can be solved. The present invention is also suitable for the SALICIDE process.

Abstract: A gallium nitride-based III-V Group compound semiconductor device has a gallium nitride-based III-V Group compound semiconductor layer provided over a substrate, and an ohmic electrode provided in contact with the semiconductor layer. The ohmic electrode is formed of a metallic material, and has been annealed.

Abstract: An iridium layer (16) is formed on an inter-layer insulation film (12) and in an opening (14). The iridium layer (16) is constituted with a part to be a lower electrode (16a) of a capacitor and a part to be a wiring (16b) for coming into contact with a drain zone (6). On part of the lower electrode (16a) of the iridium layer (16) is formed a ferroelectric layer (18) made of PZT on which is further formed an iridium layer (20) as an upper electrode. Since the melting point of iridium is higher than that of aluminum, there is no possibility of iridium melting even if heat treatment is carried out after forming the iridium layer (16). Since reactivity between iridium and silicon is low, unnecessary silicon compound is not produced on the interface to provide favorable contact.

Abstract: A semiconductor device comprising a silicon-series material layer and a laminate structure formed on the silicon-series material layer, the laminate structure being composed of a refractory metal thin film and/or a refractory metal silicide thin film, wherein a content of a halogen atom in each of the refractory metal thin film and/or the refractory metal silicide thin film is 1% by weight or less based on an amount of each of the refractory metal thin film and/or the refractory metal silicide thin film. In accordance with the present invention, there is also provided a process of producing such a semiconductor device.

Abstract: This high-power semiconductor device comprises (a) a disk of refractory metal having flat faces at its opposite sides and (b) two wafers of a semiconductor material having a coefficient of expansion similar to that of the refractory metal, the wafers being alloyed to the faces of the refractory metal disk in substantially aligned relationship to each other to form an assembly of the wafer and the disk with alloyed joints between the wafers and the disk.

Abstract: A method of forming a multi-layer suicide gate structure for a MOS type semiconductor device that includes the processing steps of first providing a substrate, then depositing a gate oxide layer on the substrate, then depositing a first refractory metal silicide layer which has a first stoichometry on the gate oxide layer, and finally depositing a second refractory metal silicide layer which has a second stoichometry different than the first stoichometry on the first deposited refractory metal silicide layer.

Abstract: Generally, according to the present invention, the sidewall of the adhesion layer (e.g. TiN 36) in a lower electrode is pre-oxidized after deposition of an unreactive noble metal layer (e.g. Pt 38) but before deposition of an HDC material (e.g. BST 42). An important aspect of the present invention is that the pre-oxidation of the sidewall generally causes a substantial amount of the potential sidewall expansion (and consequent noble metal layer deformation) to occur before deposition of the HDC material. One embodiment of the present invention is a microelectronic structure comprising a supporting layer having a principal surface, and an adhesion layer overlying the principal surface of the supporting layer, wherein the adhesion layer comprises a top surface and an expanded, oxidized sidewall (e.g. TiO.sub.2 40).

Abstract: A semiconductor light emitting element includes a p-type electrode which in turn includes a contact electrode layer including at least a Pt layer. Particularly, the semiconductor light emitting element further includes a layered structure including at least an n-type cladding layer, an active layer, and a p-type cladding layer; and a p-type contact layer formed above the layered structure, and the contact electrode layer is formed on the p-type contact layer.

Abstract: The durability and reliability of a polymer layer/metal layer sensor structure is improved by the incorporation of a metal oxide, e.g., tantalum oxide (Ta.sub.2 O.sub.5), layer between the polymer, e.g., polyimide, and the metal, e.g., platinum. sensor element.

Abstract: A gallium nitride-based III-V Group compound semiconductor device has a gallium nitride-based III-V Group compound semiconductor layer provided over a substrate and an ohmic electrode provided in contact with the semiconductor layer. The ohmic electrode is formed of a metallic material, and has been annealed.

Abstract: A semiconductor die includes a metal layer deposited thereon for enhancing adhesion between the die and a mold compound package. The metal layer is substantially oxide free. The die is coated with a layer or layers of copper (Cu) and/or palladium (Pd) by electroplating or electroless coating techniques. The metal layer provides a uniform wetting surface for better adhesion of the die with the mold compound during encapsulation. The increased adhesion reduces delamination potential of the die from the package.

Abstract: This invention is a process for forming an effective titanium nitride barrier layer between the upper surface of a polysilicon plug formed in thick dielectric layer and a platinum lower capacitor plate in a dynamic random access memory which is being fabricated on a silicon wafer. The barrier layer process begins by etching the upper surface of the polysilicon plug using a selective polysilicon etch until it is recessed at least 1000 .ANG. below the upper surface of the thick dielectric layer. Using a collimated sputter source, a titanium layer having a thickness of 100-500 .ANG. is deposited over the surface of the in-process wafer, thus covering the upper surfaces of the polysilicon plugs. A layer of amorphous titanium carbonitride having a thickness of 100-300 .ANG. is then deposited via low-pressure chemical vapor deposition. This is followed by the deposition of a reactively sputtered titanium nitride layer having a thickness of 1000-2000 .ANG..

Abstract: A method of forming a multi-layer silicide gate structure for a MOS type semiconductor device that includes the processing steps of first providing a substrate, then depositing a gate oxide layer on the substrate, then depositing a first refractory metal silicide layer which has a first stoichometry on the gate oxide layer, and finally depositing a second refractory metal silicide layer which has a second stoichometry different than the first stoichometry on the first deposited refractory metal silicide layer.

Abstract: A ferroelectric memory device of an MFIS FET structure using a yttrium oxide film as a buffer film and a manufacturing method of the memory device are provided. The MFIS FET includes a p-type silicon substrate, a field oxide film formed in a device isolation region of the silicon substrate, a gate yttrium oxide film formed on the surface of the silicon substrate, a gate ferroelectric film formed on the gate yttrium oxide film, a gate TiN electrode formed on the gate ferroelectric film, and an n-type source/drain region formed in the silicon substrate of both sides of the gate TiN electrode. In this way, single crystals of the gate yttrium oxide film are easily formed resulting in the formation of a good-quality ferroelectric film on the yttrium oxide film.

Abstract: A method and a device directed to the same, for stabilizing cobalt silicide/single crystal silicon, amorphous silicon, polycrystalline silicon, germanide/crystalline germanium, polycrystalline germanium structures or other semiconductor material structures so that high temperature processing steps (above 750.degree. C.) do not degrade the structural quality of the cobalt silicide/silicon structure. The steps of the method include forming a silicide or germanide by either reacting cobalt with the substrate material and/or the codeposition of the silicide or germanide on a substrate, adding a selective element, either platinum or nitrogen, into the cobalt and forming the silicide germanide by a standard annealing treatment. Alternatively, the cobalt silicide or cobalt germanide can be formed after the formation of the silicide or germanide respectively. As a result, the upper limit of the annealing temperature at which the silicide or germanide will structurally degrade is increased.

Abstract: A semiconductor device which comprises a first insulator, a first conductor disposed on one side near a semiconductor substrate, a second conductor disposed on the opposite side to the substrate forming a tubular member together with the first conductor, and a second insulator surrounding the member. The first insulator is incorporated into the member, and the member and the first insulator constitute an electrical wiring. Since the wiring is composed of the first insulator and the first and second conductors surrounding the first insulator, an electric current flows the tubular member of the conductors. Therefore, when the device is operated by a high-frequency (for example 80 GHz or more) electric current, apparent increase of the wiring resistance due to the "skin effect" hardly occur and as a result, reduction of the operating speed can be prevented.

Abstract: A II-VI group compound semiconductor device having a p-type Zn.sub.x Mg.sub.1-x S.sub.y Se.sub.1-y (0.ltoreq.x.ltoreq.1, 0.ltoreq.y.ltoreq.1) semiconductor layer, on which an electrode layer is formed with at least metallic nitride layer lying between the semiconductor layer and the electrode layer.

Abstract: A semiconductor die includes a metal layer deposited thereon for enhancing adhesion between the die and a mold compound package. The metal layer is substantially oxide free. The die is coated with a layer or layers of copper (Cu) and/or palladium (Pd) by electroplating or electroless coating techniques. The metal layer provides a uniform wetting surface for better adhesion of the die with the mold compound during encapsulation. The increased adhesion reduces delamination potential of the die from the package.

Abstract: Generally, according to the present invention, the sidewall of the adhesion layer (e.g. TiN 36) in a lower electrode is pre-oxidized after deposition of an unreactive noble metal layer (e.g. Pt 38) but before deposition of an HDC material (e.g. BST 42). An important aspect of the present invention is that the pre-oxidation of the sidewall generally causes a substantial amount of the potential sidewall expansion (and consequent noble metal layer deformation) to occur before deposition of the HDC material. One embodiment of the present invention is a microelectronic structure comprising a supporting layer having a principal surface, and an adhesion layer overlying the principal surface of the supporting layer, wherein the adhesion layer comprises a top surface and an expanded, oxidized sidewall (e.g. TiO.sub.2 40).

Abstract: A thin film transistor structure having a first and a second polycrystalline silicon layer of different conductivity types (P and N) has a high resistance contact at the resultant P-N junction. This contact resistance is reduced by forming TiSi.sub.2 (titanium disilicide) or other refractory metal silicides such as cobalt or molybdenum in specific regions, namely the P-N junction contact. Titanium disilicide consumes the portion of the second polycrystalline silicon layer in the P-N contact junction and at the same time consumes a small portion of the underlying first polycrystalline silicon layer, such that the high resistance P-N junction now no longer exists.

Abstract: A semiconductor device comprises a silicon via-plug within a fine via-hole in direct contact with an inner wall of the via-hole. A metal silicide layer is formed between an interconnection layer and the silicon plug as well as between the silicon plug and a diffused layer formed in a substrate. Shape defects and excessive stresses formed within a fine via-hole are reduced because the via-hole is filled with the silicon plug substantially without a metallic film or a metal silicide film on a sidewall. The metal silicide film is formed by a heat treatment through silicidation reaction.

Abstract: The present invention includes a semiconductor device having a layer including an elemental metal and its conductive metal oxide, wherein the layer is capable being oxidized or reduced preferentially to an adjacent region of the device. The present invention also includes processes for forming the devices. Substrate regions, silicon-containing layers, dielectric layers, electrodes, barrier layers, contact and via plugs, interconnects, and ferroelectric capacitors may be protected by and/or formed with the layer. Examples of elemental metals and their conductive metal oxides that may be used with the present invention are: ruthenium and ruthenium dioxide, rhenium and rhenium dioxide, iridium and iridium dioxide, osmium and osmium tetraoxide, or the like.

Abstract: The present invention relates to a semiconductor device which has a wiring system including a wiring formed by completely surrounding a periphery of isolation films with a metal conductor as a main wiring material as viewed in a cross sectional profile and a contact opening and a through hole opening where the main wiring material is buried and a manufacturing method thereof.

Abstract: A semiconductor device which comprises a first insulator, a first conductor disposed on one side near a semiconductor substrate, a second conductor disposed on the opposite side to the substrate forming a tubular member together with the first conductor, and a second insulator surrounding the member. The first insulator is incorporated into the member, and the member and the first insulator constitute an electrical wiring. Since the wiring is composed of the first insulator and the first and second conductors surrounding the first insulator, an electric current flows through the tubular member of the conductors. Therefore, when the device is operated by a high-frequency (for example 80 GHz or more) electric current, apparent increase of the wiring resistance due to the "skin effect" hardly occurs and as a result, reduction of the operating speed can be prevented.

Abstract: A hot-electron transistor (10) is formed on substrate (12) having an outer surface. The present transistor includes subcollector layer (14) comprising Indium Gallium Arsenide formed outwardly from the outer surface of substrate (12). Collector barrier layer (18) comprising Indium Aluminum Gallium Arsenide is outwardly formed from subcollector layer (14), and collector barrier layer (18) minimizes leakage current in transistor (10). Outwardly from collector barrier layer (18) is formed base layer (20) comprising Indium Gallium Arsenide. Tunnel injector layer (21) comprising Aluminum Arsenide for ballistically transporting electrons in transistor (10) is outwardly formed from base layer (20), and emitter layer (24) comprising Indium Aluminum Arsenide is outwardly formed from tunnel injector layer (21).

Abstract: A method for connecting a silicon substrate to an electrical component via a platinum conductor. The resulting structure may be heated in the presence of oxygen to temperatures in excess of 800.degree. C. without destroying the electrical connection between the silicon substrate and components connected to the platinum conductor. The present invention utilizes a TiN or TiW buffer layer to connect the platinum conductor to the silicon substrate. The buffer layer is deposited as a single crystal on the silicon substrate. The platinum layer is then deposited on the buffer layer. The region of the platinum layer in contact with the buffer layer is also a single crystal.

Abstract: A bipolar transistor fabricated on a silicon layer has a base electrode with a multi-layered structure implemented by a titanium film, a titanium nitride film, a platinum film and a gold film, and the platinum film is regulated to 5 to 30 nanometers thick for decreasing the thermal stress between the platinum film and the titanium nitride film equal to or greater than 50 nanometers, thereby preventing the bipolar transistor from damage due to heat applications in later stages.

Abstract: A semiconductor device having a gold wiring layer for an element region is disclosed, in which the gold wiring layer is connected to the element region through a barrier metal layer, the barrier metal layer comprising first and second layers each containing titanium and a third layer sandwiched between the first and second layers and made of a selected one from platinum and palladium. The third layer effectively prevents gold in the gold wiring layer from diffusing into the element region and the second layer enhances the adhesion between the gold wiring layer and an insulating film.

Abstract: An interconnect structure is formed having a substrate (10). A conductive layer (14) is formed overlying the substrate (10). A conductive layer (18) is formed overlying the conductive layer (14). An opening (19) is etched through the conductive layer (18), exposing a top portion of conductive layer (14), and forming a sidewall of the conductive layer (18). An selective isotropic etch procedure is used to laterally recess the sidewall of the conductive layer (18). A sidewall spacer (22) is formed adjacent the sidewall of the conductive layer (18). A conductive layer (24) is formed within opening (19) and adjacent the spacer (22) to form an interconnection between conductive layers (24 and 14). The interconnection is self-aligned, and conductive layer (18) is reliably isolated from the interconnect due to the lateral recessed sidewall of the conductive layer (18).