Of Specified Configuration Patents (Class 257/773)
  • Patent number: 9030014
    Abstract: An upper surface of a plug (PL1) is formed so as to be higher than an upper surface of an interlayer insulating film (PIL) by forming the interlayer insulating film (PIL) on a semiconductor substrate (1S), completing a CMP method for forming the plug (PL1) inside the interlayer insulating film (PIL), and then, making the upper surface of the interlayer insulating film (PIL) to recede. In this manner, reliability of connection between the plug (PL1) and a wiring (W1) in a vertical direction can be ensured. Also, the wiring (W1) can be formed so as not to be embedded inside the interlayer insulating film (PIL), or a formed amount by the embedding can be reduced.
    Type: Grant
    Filed: June 14, 2010
    Date of Patent: May 12, 2015
    Assignee: Renesas Electronics Corporation
    Inventor: Takeshi Kawamura
  • Patent number: 9030021
    Abstract: Provided are a printed circuit board (PCB) having hexagonally aligned bump pads as a substrate of a semiconductor package, and a semiconductor package including the same. The PCB includes: a PCB body; a bottom metal layer at a bottom of the PCB body; and a top metal layer at a top of the PCB body, and the top metal layer includes: vias vertically connected to the PCB body; bump pads hexagonally aligned in a horizontal direction around the vias; and connection patterns connecting the vias to two or more of the bump pads. Accordingly, the number of bump pads in a unit area of the PCB may be increased.
    Type: Grant
    Filed: September 8, 2011
    Date of Patent: May 12, 2015
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Jik-ho Song
  • Patent number: 9029903
    Abstract: A light emitting diode package including a package body with a cavity, a plurality of light emitting diode (LED) chips in the cavity, a plurality of wires connected to the plurality of LED chips, and a plurality of lead frames in the package body, wherein the lead frames comprise a first lead frame electrically connected to a first electrode of a first LED chip, a second lead frame electrically connected to a second electrode of the first LED chip and a second electrode of a second LED chip, a third lead frame electrically connected to a first electrode of the second LED chip, and fourth lead frame electrically connected to a second electrode of a third LED chip. Further, ends of the lead frames are exposed outside of the package body and penetrate the package body, and the first electrodes are P electrodes and the second electrodes are N electrodes.
    Type: Grant
    Filed: June 10, 2013
    Date of Patent: May 12, 2015
    Assignee: LG Innotek Co., Ltd.
    Inventor: Won-Jin Son
  • Patent number: 9030022
    Abstract: A device includes a package component having conductive features on a top surface, and a polymer region molded over the top surface of the first package component. A plurality of openings extends from a top surface of the polymer region into the polymer region, wherein each of the conductive features is exposed through one of the plurality of openings. The plurality of openings includes a first opening having a first horizontal size, and a second opening having a second horizontal size different from the first horizontal size.
    Type: Grant
    Filed: October 24, 2011
    Date of Patent: May 12, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Meng-Tse Chen, Chun-Cheng Lin, Yu-Peng Tsai, Hsiu-Jen Lin, Ming-Da Cheng, Chung-Shi Liu
  • Publication number: 20150123129
    Abstract: In a wafer level chip scale packaging technique for MEMS devices, a deep trench is etched on a scribe line area between two CMOS devices of a CMOS substrate at first. After bonding of the CMOS substrate with a MEMS substrate, the deep trench is opened by thin-down process so that CMOS substrate is singulated while MEMS substrate is not (partial singulation). Electrical test pad on MEMS substrate is exposed and protection material can be filled through the deep trench around bonding layers. After filling the protection material, the wafer is diced to form packaged individual chips with protection from environment outside bonding layer.
    Type: Application
    Filed: November 5, 2013
    Publication date: May 7, 2015
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Yi-Chuan Teng, Jung-Huei Peng, Shang-Ying Tsai, Li-Min Hung, Yao-Te Huang, Chin-Yi Cho
  • Publication number: 20150123282
    Abstract: A semiconductor device includes an interlayer dielectric on a semiconductor substrate, a contact plug penetrating the interlayer dielectric, a pillar pattern disposed on the interlayer dielectric and having a central axis laterally offset from a central axis of the contact plug, a pad extending on the contact plug and along a sidewall of the pillar pattern, the pad being electrically connected to the contact plug, and a data storage portion on the pillar pattern and electrically connected to the pad.
    Type: Application
    Filed: August 15, 2014
    Publication date: May 7, 2015
    Inventor: Daeshik KIM
  • Publication number: 20150123273
    Abstract: A semiconductor device has an interposer frame mounted over a carrier. A semiconductor die has an active surface and bumps formed over the active surface. The semiconductor die can be mounted within a die opening of the interposer frame or over the interposer frame. Stacked semiconductor die can also be mounted within the die opening of the interposer frame or over the interposer frame. Bond wires or bumps are formed between the semiconductor die and interposer frame. An encapsulant is deposited over the interposer frame and semiconductor die. An interconnect structure is formed over the encapsulant and bumps of the first semiconductor die. An electronic component, such as a discrete passive device, semiconductor die, or stacked semiconductor die, is mounted over the semiconductor die and interposer frame. The electronic component has an I/O count less than an I/O count of the semiconductor die.
    Type: Application
    Filed: January 13, 2015
    Publication date: May 7, 2015
    Applicant: STATS ChipPAC, Ltd.
    Inventors: NamJu Cho, HeeJo Chi, HanGil Shin
  • Publication number: 20150123281
    Abstract: A semiconductor package substrate includes an insulating substrate; a circuit pattern on the insulating substrate; a protective layer on the insulating substrate, the protective layer covering the circuit pattern on the insulating substrate; a pad on the protective layer; and an adhesive member on the protective layer, wherein the pad includes a first pad buried in the protective layer, and a second pad on the first pad, the second pad protruding over the protective layer.
    Type: Application
    Filed: May 24, 2013
    Publication date: May 7, 2015
    Inventors: Sung Wuk Ryu, Dong Sun Kim, Seung Yul Shin
  • Patent number: 9024443
    Abstract: A semiconductor device according to the present embodiment includes a semiconductor substrate. A lower-layer wiring is provided above a surface of the semiconductor substrate. An interlayer dielectric film is provided on the lower-layer wiring and includes a four-layer stacked structure. A contact plug contains aluminum. The contact plug is filled in a contact hole formed in the interlayer dielectric film in such a manner that the contact plug reaches the lower-layer wiring. Two upper layers and two lower layers in the stacked structure respectively have tapers on an inner surface of the contact hole. The taper of two upper layers and the taper of two lower layers have different angles from each other.
    Type: Grant
    Filed: March 15, 2013
    Date of Patent: May 5, 2015
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Merii Inaba, Takeshi Hizawa
  • Patent number: 9024447
    Abstract: An apparatus comprises a first chip layer comprising a first component coupled to a first side of a first flex layer, the first component comprising a plurality of electrical pads. The first chip layer also comprises a first plurality of feed-thru pads coupled to the first side of the first flex layer and a first encapsulant encapsulating the first component, the first encapsulant having a portion thereof removed to form a first plurality of cavities in the first encapsulant and to expose the first plurality of feed-thru pads by way of the first plurality of cavities.
    Type: Grant
    Filed: March 13, 2012
    Date of Patent: May 5, 2015
    Assignee: General Electric Company
    Inventors: Christopher James Kapusta, James Sabatini
  • Patent number: 9024444
    Abstract: In a semiconductor device, a first contact-diffusion-layer is in a first well to be connected to the first well and extends in a channel width direction of a first transistor in a first well. A second contact-diffusion-layer is in the first well so as to be electrically connected to the first well and extends in a channel-length direction of the first transistor. A first contact on the first contact-diffusion-layer has a shape with a diameter in the channel-width direction larger than that in the channel-length direction when viewed from above the substrate. A second contact on the second contact-diffusion-layer has a shape with a diameter in the channel-width direction smaller than that of the first contact and a diameter in the channel-length direction almost equal to that of the first contact when viewed from above the substrate. A wiring is electrically connected to the first transistor through the second contact.
    Type: Grant
    Filed: June 5, 2014
    Date of Patent: May 5, 2015
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Kenichi Abe, Takuya Futatsuyama, Jumpei Sato
  • Publication number: 20150115456
    Abstract: A method of manufacturing a semiconductor chip comprising placing a plurality of die units each having an active front surface and a back surface facing front surface up on an encapsulant layer, encapsulating the plurality of die units on the active surface of the encapsulant layer with an encapsulant covering a front surface and four side surfaces of each of the plurality of die units, and exposing, through the encapsulation on the front surface, conductive interconnects electrically connecting a die bond pad to a redistribution layer.
    Type: Application
    Filed: December 29, 2014
    Publication date: April 30, 2015
    Inventor: Christopher M. Scanlan
  • Publication number: 20150115455
    Abstract: A memory can include a plurality of memory blocks, including a first block and a second block disposed over the first block. An isolation layer is disposed in this structure, between the first and second blocks to isolate the vertical conductors in the memory kernels of the first and second blocks. Access conductors are provided outside the kernels, such as adjacent the memory blocks or through regions of the blocks that only include decoding element. The access conductors are coupled to the decoding elements in the first and second blocks, and provide for connection of the memory cells to peripheral circuits.
    Type: Application
    Filed: October 31, 2013
    Publication date: April 30, 2015
    Applicant: MACRONIX INTERNATIONAL CO., LTD.
    Inventor: SHIH-HUNG CHEN
  • Publication number: 20150115454
    Abstract: Microelectronic packages having layered interconnect structures are provided, as are methods for the fabrication thereof. In one embodiment, the method includes forming a first plurality of interconnect lines in ohmic contact with a first bond pad row provided on a semiconductor. A dielectric layer is deposited over the first plurality of interconnect lines, the first bond pad row, and a second bond pad row adjacent the first bond pad row. A trench via is then formed in the dielectric layer to expose at least the second bond pad row therethrough. A second plurality of interconnect lines is formed in ohmic contact with the second bond pad row within the trench via. The second plurality of interconnect lines extends over the first bond pad row and is electrically isolated therefrom by the dielectric layer to produce at least a portion of the layered interconnect structure.
    Type: Application
    Filed: October 30, 2013
    Publication date: April 30, 2015
    Inventors: Alan J. Magnus, Trung Q. Duong, Zhiwei Gong, Scott M. Hayes, Douglas G. Mitchell, Michael B. Vincent, Jason R. Wright, Weng F. Yap
  • Publication number: 20150115465
    Abstract: A semiconductor device has a substrate. A conductive via is formed through the substrate. A plurality of first contact pads is formed over a first surface of the substrate. A plurality of second contact pads is formed over a second surface of the substrate. A dummy pattern is formed over the second surface of the substrate. An indentation is formed in a sidewall of the substrate. An opening is formed through the substrate. An encapsulant is deposited in the opening. An insulating layer is formed over second surface of the substrate. A dummy opening is formed in the insulating layer. A semiconductor die is disposed adjacent to the substrate. An encapsulant is deposited over the semiconductor die and substrate. The first surface of the substrate includes a width that is greater than a width of the second surface of the substrate.
    Type: Application
    Filed: July 11, 2014
    Publication date: April 30, 2015
    Inventors: Yaojian Lin, Kang Chen, Hin Hwa Goh, Il Kwon Shim
  • Publication number: 20150115457
    Abstract: A semiconductor device, including a substrate having an active region defined therein, a plurality of bit lines extending on the substrate in a first direction, a plurality of interconnection lines extending on the substrate in a second direction, a pad electrically connected to the plurality of interconnection lines and configured to apply an external voltage, a plurality of metal contacts electrically connecting the interconnection lines and the plurality of bit lines, and a plurality of bit line contacts that are in contact with the active region and electrically connect the plurality of bit lines and the active region, wherein a size of at least some of the bit line contacts and/or at least some of the metal contacts vary based on a distance of the respective bit line contact or the metal contact from the pad.
    Type: Application
    Filed: December 31, 2014
    Publication date: April 30, 2015
    Inventors: Sang-Jong KIM, Jae-Hyeon PARK, Sung-Hoon BAE, Jong-Wan MA
  • Patent number: 9018760
    Abstract: A solder interconnect structure is provided with non-wettable sidewalls and methods of manufacturing the same. The method includes forming a nickel or nickel alloy pillar on an underlying surface. The method further includes modifying the sidewall of the nickel or nickel alloy pillar to prevent solder wetting on the sidewall.
    Type: Grant
    Filed: November 19, 2013
    Date of Patent: April 28, 2015
    Assignee: International Business Machines Corporation
    Inventors: Charles L. Arvin, Raschid J. Bezama, Timothy H. Daubenspeck, Jeffrey P. Gambino, Christopher D. Muzzy, David L. Questad, Wolfgang Sauter, Timothy D. Sullivan, Brian R. Sundlof
  • Patent number: 9018755
    Abstract: A joint structure includes: a ceramic member; a metallized layer formed on a surface of the ceramic member; and a metal member joined to the metallized layer via a brazing material. The metal member includes a base part erected on the metallized layer, and an extended part extended from the base part to define a predetermined gap with respect to the metallized layer. The base part includes an end joined to the metallized layer by a brazing material layer including the brazing material, and a side joined to the metallized layer around the base part by a fillet including the brazing material formed on the metallized layer around the base part. The extended part defines a recess at a position facing the metallized layer on which the fillet is formed.
    Type: Grant
    Filed: April 8, 2014
    Date of Patent: April 28, 2015
    Assignee: NGK Spark Plug Co., Ltd.
    Inventors: Sadahiro Nishimura, Naoki Tsuda
  • Patent number: 9018044
    Abstract: In one embodiment, a chip-on-lead package structures includes an electronic chip having opposing major surfaces. One major surface of the electronic chip is attached to first and second leads. The one major surface is electrically connected to the first lead, and electrically isolated from the second lead. The other major surface where active device are formed may be electrically connected to the second lead.
    Type: Grant
    Filed: May 9, 2014
    Date of Patent: April 28, 2015
    Assignee: Semiconductor Components Industries, LLC
    Inventors: Atapol Prajuckamol, Bih Wen Fon, Jun Keat Lee
  • Patent number: 9018750
    Abstract: Disclosed is a package that includes a wafer substrate and a metal stack seed layer. The metal stack seed layer includes a titanium thin film outer layer. A resist layer is provided in contact with the titanium thin film outer layer of the metal stack seed layer, the resist layer forming circuitry. A method for manufacturing a package is further disclosed. A metal stack seed layer having a titanium thin film outer layer is formed. A resist layer is formed so as to be in contact with the titanium thin film outer layer of the metal stack seed layer, and circuitry is formed from the resist layer.
    Type: Grant
    Filed: August 10, 2012
    Date of Patent: April 28, 2015
    Assignee: Flipchip International, LLC
    Inventors: Robert Forcier, Douglas Scott
  • Publication number: 20150108651
    Abstract: The present disclosure relates to methods of forming a self-aligned contact and related apparatus. In some embodiments, the method forms a plurality of gate lines interspersed between a plurality of dielectric lines, wherein the gate lines and the dielectric lines extend in a first direction over an active area. One or more of the plurality of gate lines are into a plurality of gate line sections aligned in the first direction. One or more of the plurality of dielectric lines are cut into a plurality of dielectric lines sections aligned in the first direction. A dummy isolation material is deposited between adjacent dielectric sections in the first direction and between adjacent gate line sections in the first direction. One or more self-aligned metal contacts are then formed by replacing a part of one or more of the plurality of dielectric lines over the active area with a contact metal.
    Type: Application
    Filed: December 29, 2014
    Publication date: April 23, 2015
    Inventors: Neng-Kuo Chen, Shao-Ming Yu, Gin-Chen Huang, Chia-Jung Hsu, Sey-Ping Sun, Clement Hsingjen Wann
  • Publication number: 20150108652
    Abstract: A semiconductor device and its fabrication method are provided. A first dielectric layer is provided to cover a substrate. The first dielectric layer contains a plurality of first conductive layers. A portion of each first conductive layer is removed to form a plurality of first openings in the first dielectric layer. A second dielectric layer is formed in each first opening. A third dielectric layer having second-openings are formed on the first dielectric layer and on the second dielectric layers. Each second-opening exposes at least two adjacent second dielectric layers. Second dielectric layers exposed by a first second-opening are removed to form third openings to expose corresponding first conductive layers. Second conductive layers are formed in the third opening and the second-openings including the first second-opening. Stable electrical interconnections with high quality electrical isolations can be provided.
    Type: Application
    Filed: February 19, 2014
    Publication date: April 23, 2015
    Applicant: Semiconductor Manufactruing International (Shanghai) Corporation
    Inventor: ZHONGSHAN HONG
  • Publication number: 20150109864
    Abstract: An integrated circuit and methods for manufacturing and operating the same are provided. The integrated circuit comprises a fork architecture and a first conductive structure. The fork architecture comprises a handle portion and prong portions extending from the handle portion. The fork architecture comprises a stacked structure and a dielectric layer. The dielectric layer is between the first conductive structure and the handle portion of the stacked structure.
    Type: Application
    Filed: October 23, 2013
    Publication date: April 23, 2015
    Applicant: MACRONIX INTERNATIONAL CO., LTD.
    Inventors: Chih-Wei Hu, Teng-Hao Yeh
  • Patent number: 9013029
    Abstract: A joined body which is formed by, first, an aqueous solution containing an oxide film remover is disposed on a junction region of a first metal plate. Then, with the aqueous solution remaining on the first metal plate, a second metal plate is placed on the first metal plate. Thereafter, a load is applied to junction regions of the first metal plate and the second metal plate in the vertical direction, thereby joining the first metal plate and the second metal plate together to form a junction portion.
    Type: Grant
    Filed: August 8, 2012
    Date of Patent: April 21, 2015
    Assignee: Panasonic Intellectual Property Management Co., Ltd.
    Inventors: Masanori Minamio, Tatsuo Sasaoka
  • Patent number: 9013040
    Abstract: A memory device with die stacking is provided. A plurality of substrates layers are stacked together into a stack. Each substrate layer may include a substrate having a plurality of cavities to receive integrated circuit components within the thickness of the substrate. A plurality of conductive spheres are arranged between at least two adjacent substrate layers and are electrically coupled to the integrated circuit components in at least one of the two adjacent substrates. The two adjacent substrate layers of the stack include: (a) a first substrate having a first plurality of cavities to receive integrated circuit components, and (b) a second substrate having a second plurality of cavities to receive integrated circuit components, wherein the first plurality of cavities is offset from a second plurality of cavities.
    Type: Grant
    Filed: October 3, 2013
    Date of Patent: April 21, 2015
    Assignee: Sanmina Corporation
    Inventor: Jon Schmidt
  • Patent number: 9013002
    Abstract: An iridium interfacial stack (“IrIS”) and a method for producing the same are provided. The IrIS may include ordered layers of TaSi2, platinum, iridium, and platinum, and may be placed on top of a titanium layer and a silicon carbide layer. The IrIS may prevent, reduce, or mitigate against diffusion of elements such as oxygen, platinum, and gold through at least some of its layers.
    Type: Grant
    Filed: June 27, 2012
    Date of Patent: April 21, 2015
    Assignee: The United States of America as Represented by the Administrator of National Aeronautics and Space Administration
    Inventor: David James Spry
  • Patent number: 9013043
    Abstract: A semiconductor element includes: a transparent substrate; a stack structure formed on the transparent substrate and having a metal oxide layer partially exposed through sidewalls of the stack structure; a plurality of leads spacingly formed on the stack structure and extending to the sidewalls of the stack structure; an insulating film covering the exposed portions of the metal oxide layer; a metal film formed on the leads; and a solder mask layer disposed on the metal film, the stack structure and the insulating film. As such, the insulating film prevents short circuits from occurring between adjacent leads so as to improve the product yield.
    Type: Grant
    Filed: November 2, 2012
    Date of Patent: April 21, 2015
    Assignee: Xintec Inc.
    Inventor: Hung-Chang Chen
  • Patent number: 9013039
    Abstract: A method for handling and supporting a device wafer during a wafer thinning process and the resulting device are provided. Embodiments include forming a plurality of solder bumps on a first surface of a substrate having a first and a second surface; removing a portion from a periphery of the first surface of the substrate; forming a temporary bonding material on a first carrier; bonding the first surface of the substrate with the temporary bonding material of the first carrier; affixing the second surface of the substrate to a second carrier; and removing the temporary bonding material.
    Type: Grant
    Filed: August 5, 2013
    Date of Patent: April 21, 2015
    Assignee: GLOBALFOUNDRIES Inc.
    Inventor: Rahul Agarwal
  • Publication number: 20150102494
    Abstract: A method for forming voids corresponding to pads of SMT components is provided. The method comprises following steps: One or more condition parameters are inputted into a searching unit. The searching unit searches all of the pads with reference to the condition parameters to obtain a pre-selected group of pads. A judgment unit is provided to determine whether each pad of the pre-selected group of pads meets a pre-determined processing requirement to generate a to-be-processed group of pads. An execution unit executes a void formation step with reference to corner coordinates of each of the to-be-processed group of pads, so as to form at least a void at the portion of a contact surface corresponding to a corner of the pad. In an embodiment, four voids which are related to respective corners of each pad of the to-be-processed group are formed at the contact surface accordingly.
    Type: Application
    Filed: March 19, 2014
    Publication date: April 16, 2015
    Applicant: Wistron Corporation
    Inventors: Hui-Ying Chou, Lee-Chieh Kang
  • Publication number: 20150102484
    Abstract: A package structure is disclosed, which includes: a first substrate; a build-up layer formed on and electrically connected to the first substrate and having a cavity; at least an electronic element disposed in the cavity and electrically connected to the first substrate; a stack member disposed on the build-up layer so as to be stacked on the first substrate; and an encapsulant formed between the build-up layer and the stack member. The build-up layer facilitates to achieve a stand-off effect and prevent solder bridging.
    Type: Application
    Filed: December 20, 2013
    Publication date: April 16, 2015
    Applicant: SILICONWARE PRECISION INDUSTRIES CO., LTD
    Inventors: Chia-Cheng Chen, Ming-Chen Sun, Tzu-Chieh Shen, Liang-yi Hung, Wei-chung Hsiao, Yu-cheng Pai, Shih-Chao Chiu, Don-Son Jiang, Yi-Feng Chang, Lung-Yuan Wang
  • Publication number: 20150102493
    Abstract: A die according to an embodiment includes a contact pad configured to provide an electrical contact to a circuit element included in the die, a lateral edge closest to the contact pad and a cover layer including a protective structure, the protective structure including at least one elongated structure, wherein the cover layer includes an opening providing access to the contact pad to couple the contact pad electrically to an external contact, wherein the protective structure is arranged between the lateral edge and the contact pad. Using an embodiment may reduce a danger of contamination of a top side of a die during fabrication and packaging a chip.
    Type: Application
    Filed: October 16, 2013
    Publication date: April 16, 2015
    Inventor: Bernhard Knuepfer
  • Publication number: 20150102503
    Abstract: A fan out package includes a molding compound, a conductive plug in the molding compound, a dielectric covering the molding compound and a portion of the conductive plug, and an interconnect disposed over the dielectric and contacted with the conductive plug, wherein a width of the interconnect contacting the conductive plug is substantially smaller than a width of the conductive plug in the molding compound, and a width of the interconnect disposed over the dielectric is substantially greater than the width of the conductive plug in the molding compound.
    Type: Application
    Filed: December 22, 2014
    Publication date: April 16, 2015
    Inventors: JING-CHENG LIN, JUI-PIN HUNG, PO-HAO TSAI
  • Patent number: 9006902
    Abstract: A semiconductor device is provided having an insulating layer on a semiconductor substrate. The insulating layer and the semiconductor substrate define a through hole penetrating the semiconductor substrate and the insulating layer. A through electrode is provided in the through hole. A spacer is provided between the semiconductor substrate and the through electrode. An interconnection in continuity with the through electrode is provided on the insulating layer. A barrier layer covering a side and a bottom of the interconnection and a side of the through electrode is provided and the barrier layer is formed in one body.
    Type: Grant
    Filed: January 22, 2014
    Date of Patent: April 14, 2015
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Ju-Il Choi, Su-Kyoung Kim, Kun-Sang Park, Seong-Min Son, Jin-Ho An, Do-Sun Lee
  • Patent number: 9006098
    Abstract: A method of improving electrical interconnections between two electrical elements is made available by providing a meta-material overlay in conjunction with the electrical interconnection. The meta-material overlay is designed to make the electrical signal propagating via the electrical interconnection to act as though the permittivity and permeability of the dielectric medium within which the electrical interconnection is formed are different than the real component permittivity and permeability of the dielectric medium surrounding the electrical interconnection. In some instances the permittivity and permeability resulting from the meta-material cause the signal to propagate as if the permittivity and permeability have negative values. Accordingly the method provides for electrical interconnections possessing enhanced control and stability of impedance, reduced noise, and reduced loss.
    Type: Grant
    Filed: August 22, 2008
    Date of Patent: April 14, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventor: Christopher Wyland
  • Patent number: 9006884
    Abstract: A semiconductor device includes a substrate in which a cell region and a contact region are defined, a pad structure including a plurality of first conductive layers and a plurality of first insulating layers formed alternately with each other in the contact region of the substrate, wherein an end of the pad structure is patterned stepwise, portions of the first conductive layers exposed at the end of the pad structure are defined as a plurality of pad portions, and the plurality of pad portions have a greater thickness than unexposed portions of the plurality of first conductive layers.
    Type: Grant
    Filed: March 18, 2013
    Date of Patent: April 14, 2015
    Assignee: SK Hynix Inc.
    Inventors: Ki Hong Lee, Seung Ho Pyi, Seok Min Jeon
  • Patent number: 9006901
    Abstract: A thin power device comprises a substrate having a first set of first contact pads at a front surface of the substrate electrically connecting to a second set of second contact pads at a back surface of the substrate, a through opening opened from the front surface and through the substrate exposing a third contact pad at the back surface of the substrate, a semiconductor chip embedded into the through opening with a back metal layer at a back surface of the semiconductor chip attached on the third contact pad, and a plurality of conductive structures electrically connecting electrodes at a front surface of the semiconductor chip with the corresponding first contact pads in the first sets of first contact pads.
    Type: Grant
    Filed: July 19, 2013
    Date of Patent: April 14, 2015
    Assignee: Alpha & Omega Semiconductor, Inc.
    Inventors: Yuping Gong, Yan Xun Xue, Ming-Chen Lu, Ping Huang, Jun Lu, Hamza Yilmaz
  • Patent number: 9006872
    Abstract: In one embodiment, a semiconductor chip package includes an insulation frame having an opening part formed in a center thereof and a via hole formed around the opening part; a semiconductor chip disposed cm the opening part; a conductive part filling the via hole; an inner insulation layer formed on bottom surfaces of the semiconductor chip and the insulation frame so as to expose a bottom surface of the conductive part; and an inner signal pattern formed on the inner insulation layer and electrically connecting the semiconductor chip and the conductive part. Embodiments also relate to a semiconductor module including a vertical stack of a plurality of the semiconductor chip packages, and to a method for manufacturing the same.
    Type: Grant
    Filed: September 28, 2011
    Date of Patent: April 14, 2015
    Assignee: Nepes Corporation
    Inventor: Yong-Tae Kwon
  • Patent number: 9006890
    Abstract: The present disclosure relates to the field of fabricating microelectronic packages, wherein cavities are formed in a dielectric layer deposited on a first substrate to maintain separation between soldered interconnections. In one embodiment, the cavities may have sloped sidewalls. In another embodiment, a solder paste may be deposited in the cavities and upon heating solder structures may be formed. In other embodiments, the solder structures may be placed in the cavities or may be formed on a second substrate to which the first substrate may be connected. In still other embodiments, solder structures may be formed on both the first substrate and a second substrate. The solder structures may be used to form solder interconnects by contact and reflow with either contact lands or solder structures on a second substrate.
    Type: Grant
    Filed: January 14, 2013
    Date of Patent: April 14, 2015
    Assignee: Intel Corporation
    Inventors: Chuan Hu, Shawna M Liff, Gregory S Clemons
  • Patent number: 9006911
    Abstract: A method for forming patterns of dense conductor lines and their contact pads is described. Parallel base line patterns are formed over a substrate. Each of the base line patterns is trimmed. Derivative line patterns and derivative transverse patterns are formed as spaces on the sidewalls of the trimmed base line patterns, wherein the derivative transverse patterns are formed between the ends of the derivative line patterns and adjacent to the ends of the trimmed base line patterns. The trimmed base line patterns are removed. At least end portions of the derivative line patterns are removed, such that the derivative line patterns are separated from each other and all or portions of the derivative transverse patterns become patterns of contact pads each connected with a derivative line pattern.
    Type: Grant
    Filed: May 16, 2012
    Date of Patent: April 14, 2015
    Assignee: Nanya Technology Corporation
    Inventors: Jonathan Doebler, Scott Sills
  • Publication number: 20150097295
    Abstract: A semiconductor device has a semiconductor die with a plurality of bumps formed over a surface of the semiconductor die. A first conductive layer having first and second segments is formed over a surface of the substrate with a first vent separating an end of the first segment and the second segment and a second vent separating an end of the second segment and the first segment. A second conductive layer is formed over the surface of the substrate to electrically connect the first segment and second segment. The thickness of the second conductive layer can be less than a thickness of the first conductive layer to form the first vent and second vent. The semiconductor die is mounted to the substrate with the bumps aligned to the first segment and second segment. Bump material from reflow of the bumps is channeled into the first vent and second vent.
    Type: Application
    Filed: December 16, 2014
    Publication date: April 9, 2015
    Applicant: STATS CHIPPAC, LTD.
    Inventors: JaeHyun Lee, SunJae Kim, JoongGi Kim
  • Publication number: 20150097294
    Abstract: A method for processing a wafer in accordance with various embodiments may include: removing wafer material from an inner portion of the wafer to form a structure at an edge region of the wafer to at least partially surround the inner portion of the wafer, and printing material into the inner portion of the wafer using the structure as a printing mask. A method for processing a wafer in accordance with various embodiments may include: providing a carrier and a wafer, the wafer having a first side and a second side opposite the first side, the first side of the wafer being attached to the carrier, the second side having a structure at an edge region of the wafer, the structure at least partially surrounding an inner portion of the wafer; and printing material onto at least a portion of the second side of the wafer.
    Type: Application
    Filed: October 9, 2013
    Publication date: April 9, 2015
    Applicant: Infineon Technologies AG
    Inventors: Srinivasa Reddy Yeduru, Karl Heinz Gasser, Stefan Woehlert, Karl Mayer, Francisco Javier Santos Rodriguez
  • Publication number: 20150097293
    Abstract: Semiconductor devices and methods of manufacture thereof are disclosed. In some embodiments, a method of manufacturing a semiconductor device includes forming an insulating material layer over a workpiece, patterning an upper portion of the insulating material layer with a conductive line pattern, and forming a stop layer comprising a metal oxide or a metal nitride over the patterned insulating material layer. A masking material is formed over the stop layer, and the masking material is patterned with a via pattern. The via pattern of the masking material is transferred to a lower portion of the insulating material layer.
    Type: Application
    Filed: October 4, 2013
    Publication date: April 9, 2015
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Hsin-Chieh Yao, Chung-Ju Lee, Tien-I Bao, Shau-Lin Shue
  • Patent number: 9000587
    Abstract: A wafer-level package device and techniques for fabricating the device are described that include embedding a silicon chip onto an active device wafer or a passive device wafer, where the embedded silicon chip is a thin chip (e.g., <50 ?m). In implementations, the wafer-level package device that employs the techniques of the present disclosure includes an active device wafer, a thin integrated circuit chip, an encapsulation structure covering at least a portion of the active device wafer and the thin integrated circuit chip, a redistribution layer structure, and at least one solder bump for providing electrical interconnectivity. Once the wafer is singulated into semiconductor devices, each semiconductor device including the embedded thin integrated circuit chip may be mounted to a printed circuit board.
    Type: Grant
    Filed: June 28, 2013
    Date of Patent: April 7, 2015
    Assignee: Maxim Integrated Products, Inc.
    Inventors: Amit S. Kelkar, Vivek S. Sridharan
  • Patent number: 9000583
    Abstract: A microelectronic package includes a subassembly including a first substrate and first and second microelectronic elements having contact-bearing faces facing towards oppositely-facing first and second surfaces of the first substrate and each having contacts electrically connected with the first substrate. The contact-bearing faces of the first and second microelectronic elements at least partially overlie one another. Leads electrically connect the subassembly with a second substrate, at least portions of the leads being aligned with an aperture in the second substrate. The leads can include wire bonds extending through an aperture in the first substrate and joined to contacts of the first microelectronic element aligned with the first substrate aperture. In one example, the subassembly can be electrically connected with the second substrate using electrically conductive spacer elements.
    Type: Grant
    Filed: September 30, 2013
    Date of Patent: April 7, 2015
    Assignee: Tessera, Inc.
    Inventors: Belgacem Haba, Wael Zohni, Richard Dewitt Crisp
  • Patent number: 9000563
    Abstract: A capacitor of a semiconductor device includes a capacitor structure configured to include electrode layers and dielectric layers alternately stacked, edge regions each stepwise patterned, and a central region disposed between the edge regions, sacrificial layers disposed within the respective electrode layers in the edge regions of the capacitor structure, and support plugs formed in the central region of the capacitor structure and configured to penetrate the electrode layers and the dielectric layers.
    Type: Grant
    Filed: October 29, 2014
    Date of Patent: April 7, 2015
    Assignee: SK Hynix Inc.
    Inventors: Sun Mi Park, Sang Hyun Oh, Sang Bum Lee
  • Patent number: 8999765
    Abstract: Embodiments of the present description include methods for attaching a microelectronic device to a microelectronic substrate with interconnection structures after disposing of an underfill material on the microelectronic device, wherein filler particles within the underfill material may be repelled away from the interconnection structures prior to connecting the microelectronic device to the microelectronic structure. These methods may include inducing a charge on the interconnection structures and may include placing the interconnection structures between opposing plates and producing a bias between the opposing plates after depositing the underfill material on the interconnection structures.
    Type: Grant
    Filed: June 25, 2013
    Date of Patent: April 7, 2015
    Assignee: Intel Corporation
    Inventors: Manish Dubey, Rajendra C. Dias, Yonghao Xiu, Arjun Krishnan, Yiqun Bai, Purushotham Kaushik Muthur Srinath
  • Patent number: 9000598
    Abstract: The present disclosure is directed to orientation-independent device configuration and assembly. An electronic device may comprise conductive pads arranged concentrically on a surface of the device. The conductive pads on the device may mate with conductive pads in a device location in circuitry. Example conductive pads may include at least a first circular conductive pad and a second ring-shaped conductive pad arranged to concentrically surround the first conductive pad. The concentric arrangement of the conductive pads allows for orientation-independent placement of the device in the circuitry. In particular, the conductive pads of the device will mate correctly with the conductive pads of the circuitry regardless of variability in device orientation. In one embodiment, the device may also be configured for use with fluidic self-assembly (FSA). For example, a device housing may be manufactured with pockets that cause the device to attain neutral buoyancy during manufacture.
    Type: Grant
    Filed: September 27, 2013
    Date of Patent: April 7, 2015
    Assignee: OSRAM Sylvania Inc.
    Inventors: David W. Hamby, Adam M. Scotch, Sridharan Venk, Alan Lenef
  • Patent number: 8999759
    Abstract: A method for fabricating a packaging structure having an embedded semiconductor element includes: providing a substrate having opposite first and second surfaces and at least an opening penetrating the first and second surfaces; forming a first metallic frame around the periphery of the opening on the first surface; forming at least an opening inside the first metallic frame by laser ablation; disposing a semiconductor chip in the opening; forming a first dielectric layer on the first and second surfaces and the chip; forming a first wiring layer on the first dielectric layer of the first surface; and forming a first built-up structure on the first dielectric layer and the first wiring layer of the first surface. A shape of the opening is precisely controlled through the first metallic frame around the periphery of the predefined opening region, thereby allowing the chip to be precisely embedded in the substrate.
    Type: Grant
    Filed: May 23, 2013
    Date of Patent: April 7, 2015
    Assignee: Unimicron Technology Corporation
    Inventor: Kan-Jung Chia
  • Patent number: 9000597
    Abstract: A semiconductor device and a method of making a semiconductor device are disclosed. The method of manufacturing a semiconductor device comprises forming a material layer on a substrate, patterning a first semi-global region with a first main pattern and patterning a second semi-global region with a second main pattern, wherein the first main pattern is different than the second main pattern. The method further comprises introducing a first dummy pattern in the first semi-global region so that a first sidewall area surface density of the first main pattern and the first dummy pattern in the first semi-global region and a second sidewall area surface density of the second main pattern in the second semi-global region are substantially a same density.
    Type: Grant
    Filed: August 5, 2013
    Date of Patent: April 7, 2015
    Assignee: Infineon Technologies AG
    Inventors: Frank Huebinger, Steffen Rothenhaeusser, Kerstin Kaemmer
  • Publication number: 20150091177
    Abstract: Disclosed herein are an external connection terminal part, a semiconductor package having the external connection terminal part, and a method for manufacturing the same. According to a preferred embodiment of the present invention, the external connection terminal part includes an insulating material and metal plating pattern formed on both surfaces of the insulating material.
    Type: Application
    Filed: December 27, 2013
    Publication date: April 2, 2015
    Applicant: SAMSUNG ELECTRO-MECHANICS CO., LTD.
    Inventors: Chang Seob Hong, Eun Jung Jo, Kyu Hwan Oh, Kang Hyun Lee