Abstract: The semiconductor device has insulating films 40, 42 formed over a substrate 10; an interconnection 58 buried in at least a surface side of the insulating films 40, 42; insulating films 60, 62 formed on the insulating film 42 and including a hole-shaped via-hole 60 and a groove-shaped via-hole 66a having a pattern bent at a right angle; and buried conductors 70, 72a buried in the hole-shaped via-hole 60 and the groove-shaped via-hole 66a. A groove-shaped via-hole 66a is formed to have a width which is smaller than a width of the hole-shaped via-hole 66. Defective filling of the buried conductor and the cracking of the inter-layer insulating film can be prevented. Steps on the conductor plug can be reduced. Accordingly, defective contact with the upper interconnection layer and the problems taking place in forming films can be prevented.

Abstract: A semiconductor package with enhanced mobility of ball terminals is revealed. A chip is attached to the substrate by a die-attaching material where the substrate has at least a stepwise depression on the covered surface to make the substrate thickness be stepwise decreased from a central line of the die-attaching area toward two opposing sides of the substrate. The die-attaching material is filled in the stepwise depression. Therefore, the thickness of the die-attaching material under cross-sectional corner(s) of the chip becomes thicker so that a row of the ball terminals away from the central line of the die-attaching area can have greater mobility without changing the appearance, dimensions, thicknesses of the semiconductor package, nor the placing plane of the ball terminals. Accordingly, the row of ball terminals located adjacent the edges or corners of the semiconductor package can withstand larger stresses without ball cracks nor ball drop.

Abstract: A tooling method for fabricating semiconductor devices includes identifying two adjacent device lines having a device-to-device spacing width in an active region of a substrate, performing an operation to selectively define a first region as a region between the two adjacent device lines overlapping the active region, forming a first block pattern corresponding to the first region on a photomask when the device-to-device spacing width is equal to a predetermined value, and transferring the first block pattern to the substrate.

Abstract: The present invention provides an apparatus and method for use in processing semiconductor workpieces. The new apparatus and method allows for the production of thinner workpieces that at the same time remain strong. Particularly, a chuck is provided that includes a body, a retainer removeably attached to the body and a seal forming member. When a workpiece is placed on the chuck body and the retainer is engaged to the body, a peripheral portion of the back side of the workpiece is covered by the retainer while an interior region of the back side of the workpiece is exposed. The exposed back side of the workpiece is then subjected to a wet chemical etching process to thin the workpiece and form a relatively thick rim comprised of semiconductor material at the periphery of the workpiece. The thick rim or hoop imparts strength to the otherwise fragile, thinned semiconductor workpiece.

Abstract: It is conceivable that the problem that a signal is delayed by resistor of a wiring in producing a display which displays large area becomes remarkable. The present invention provides a manufacturing process using a droplet discharge method suitable for a large-sized substrate. In the present invention, after forming a base layer 11 (or base pretreatment) which enhances adhesiveness over a substrate in advance and forming an insulating film, a mask having a desired pattern shape is formed, and a desired depression is formed by using the mask. A metal material is filled in the depression having a mask 13 and a sidewall made from an insulating film by a droplet discharge method to form an embedded wiring (a gate electrode, a capacitor wiring, lead wiring or the like. Afterwards, it is flattened by a planarization processing, for example, a press or a CMP processing.

Abstract: A semiconductor device, including methods and arrangements for making the same, are described. The device includes an integrated circuit die having a plurality of bond pads. At least one bond pad on the active surface of the die is an extended I/O pad. Each extended I/O pad extends to at least one peripheral side edge of the die.

Abstract: A wiring substrate on which an electronic component is flip-chip bonded, including a substrate main body, a solder resist which is formed on the substrate main body and having an opening, and a plurality of conductive pattern formed on the substrate main body, including exposure surfaces exposed from the opening of the solder resist. The conductive patterns include, a narrow interval group, a wide interval group, an interval between the adjacent conductive patterns belonging to the narrow interval group is narrower than an interval between the adjacent conductive patterns belonging to the wide interval group, an exposure length of the conductive patterns of the narrow interval group is shorter than an exposure length of the conductive patterns of the wide interval group.

Abstract: An arrangement of integrated circuit dice, includes first die including a first electrical coupling site and a second die comprising a second electrical coupling site, wherein the second die is stacked onto the first die such that the first electrical coupling site is at least partially exposed, wherein the first electrical coupling site and the second electrical coupling site are directly electrically connected, and a third die arranged above the first die and the second die such that a recess is formed, wherein one of the first electrical coupling sites is arranged in the recess.

Abstract: An active matrix substrate is provided with first inspection wirings (70, 75) capable of inputting inspection signals to first switching wirings that are not adjacent to each other among the first switching wirings (69, 74) and to second switching wirings that are not adjacent to each other among the second switching wirings (69, 74), and second inspection wirings (72, 77) capable of inputting inspection signals to first switching wirings that are not adjacent to each other and not connected to the first inspection wirings among the first switching wirings (69, 74) and to second switching wirings that are not adjacent to each other and not connected to the first inspection wirings among the second switching wirings (69, 74).

Abstract: A semiconductor integrated circuit has: a power pad placed on a chip; and a circuit group connected to the power pad through a power wiring structure. The power wiring structure includes: a plurality of first power wirings and a plurality of second power wirings that are formed in different wiring layers and overlap with each other at a plurality of intersections; and vias connecting the plurality of first power wirings and the plurality of second power wirings. The circuit group includes a first functional block placed on a first region. The vias are not placed at a part of the plurality of intersections within a second region located between the first region and the power pad.

Abstract: A method and system for reducing the inductance on an integrated circuit. The method and system comprises providing a first differential line, including a first input and a first output, the first differential line including at least two bondwire traces which are coupled in parallel. The method and system also comprises providing a second differential line including a second input and a second output, the second differential line including at least two bondwire traces which are coupled in parallel, the first differential line being of opposite polarity to the second differential line. The method and system further comprises cross-coupling of the first input with the second input and the first output with the second output to reduce the inductance caused by bondwire traces. A technique in accordance with the invention uses the coupling factor K to help to further reduce the inductance.

Abstract: A semiconductor package is disclosed including a first capture pad isolated from an adjacent second capture pad by an insulator; a first plurality of electrically active vias connecting the first capture pad to the second capture pad; a third capture pad isolated from the second capture pad by an insulator; and a second plurality of electrically active vias connecting the second capture pad to the third capture pad. Each via of the first plurality of active vias is non-aligned with each via of the second plurality of active vias. The structure provides reduction of strain on the vias when a shear force is applied to a ball grid array used therewith while minimizing the degradation of the electrical signals.

Abstract: A semiconductor device in which the resistance of a copper wiring to electromigration is increased. The copper wiring is formed so that copper grains will be comparatively large in a central portion of the copper wiring and so that copper grains will be comparatively small in an upper portion and a lower portion of the metal wiring. The copper wiring having this structure is formed by a damascene method. This structure can be formed by controlling electric current density at electroplating time. With the copper wiring having this structure, it is easier for an electric current to run through the central portion than to run through the upper portion. As a result, the diffusion of copper atoms in the upper portion is suppressed and therefore the diffusion of copper atoms from an interface between the copper wiring and a cap film is suppressed.

Abstract: The present invention relates to a semiconductor device comprising first and second active device regions that are located in a semiconductor substrate and are isolated from each other by an isolation region therebetween, while the semiconductor device comprises a first conductive interconnect structure that is embedded in the isolation region and connects the first active device region with the second active device region. The semiconductor device preferably contains at least one static random access memory (SRAM) cell located in the semiconductor substrate, and the first conductive interconnect structure cross-connects a pull-down transistor of the SRAM cell with a pull-up transistor thereof. The conductive interconnect preferably comprises doped polysilicon and can be formed by processing steps including photolithographic patterning, etching, and polysilicon deposition.

Abstract: An integrated circuit structure includes a chip including a substrate and a power distribution network. The power distribution network includes a plurality of power through-silicon vias (TSVs) penetrating the substrate, wherein the plurality of power TSVs forms a grid; and a plurality of metal lines in a bottom metallization layer (M1), wherein the plurality of metal lines couples the plurality of power TSVs to integrated circuit devices on the substrate.

Abstract: An integrated circuit package system comprising: providing a first conductive line adjacent to a second conductive line; forming a first connection stack over the first conductive line with the first connection stack overhanging the second conductive line; connecting an integrated circuit device and the first connection stack; and encapsulating the integrated circuit device and the first connection stack.

Abstract: A display unit includes, on an insulating substrate, a plurality of wirings formed to extend in different directions, a thin-film transistor, and a display element. At least one of the plurality of wirings is a divided wiring having a crossing portion formed at an intersection with the other of the plurality of wirings, and a main portion which is formed in a layer same as the other of the plurality of wirings with an insulating film in between and which is electrically connected to the crossing portion via an conductive connection provided in the insulating film. At least one of the main portion and the crossing portion includes a first layer and a second layer stacked in order from the insulating substrate side, the second layer being in direct contact with the first layer and made of a material of a higher melting point than the first layer.

Abstract: A semiconductor device includes first and second wirings formed in a first wiring layer and extending parallel to an X direction, third and fourth wirings formed in a third wiring layer and extending parallel to a Y direction; fifth and sixth wirings formed in a second wiring layer positioned between the first and second wiring layers, a first contact conductor that connects the first wiring to the third wiring; and a second contact conductor that connects the second wiring to the fourth wiring. The first and second contact conductors are arranged in the X direction. According to the present invention, because the first and second contact conductors that connect wiring layers that are two or more layers apart are arranged in one direction, a prohibited area that is formed in the second wiring layer can be made narrower. Therefore, the flexibility of the layout of the second wiring layer is enhanced and the restriction on the wiring density can be relaxed.

Abstract: A sensor package has a substrate. A sensor die having an inactive surface is bonded to the substrate. An active surface of the sensor die is exposed. A portion of the active surface of the sensor die has an active imaging area. A metal bezel is formed on the active surface of the sensor die and separate from the imaging area.

Abstract: A package structure includes a substrate, a first die and at least one second die. The substrate includes a first pair of parallel edges and a second pair of parallel edges. The first die is mounted over the substrate. The first die includes a third pair of parallel edges and a fourth pair of parallel edges, wherein the third pair of parallel edges and the fourth pair of parallel edges are not parallel to the first pair of parallel edges and the second pair of parallel edges, respectively. The at least one second die is mounted over the first die.

Abstract: A semiconductor device includes a first pad row and a second pad row, a first ground potential supply electrode which is connected to a first interconnect provided near the first pad row, and a second ground potential supply electrode which is connected to a second interconnect provided near the second pad row. The first pad row includes a first pad connected to the first circuit within the chip and connected to the first interconnect via a first bonding wire, and includes a second pad connected to a second circuit within the chip and connected to the second interconnect via a second bonding wire crossing over the second pad row.

Abstract: A semiconductor device includes first underlying lines in an underlying wiring layer electrically connected to and shaped like a first semiconductor region, second underlying lines in the underlying wiring layer electrically connected to and shaped like a second semiconductor region, a first intermediate line in an intermediate wiring layer electrically connected to the first underlying lines, the first intermediate line including finger regions shaped like the first underlying lines, a coupling section to electrically interconnect the finger regions, a second intermediate line in the intermediate wiring layer electrically connected to the second underlying lines, the second intermediate line including finger regions shaped like the second underlying lines, and a coupling section to electrically connect the finger regions, a first overlying line in an overlying wiring layer electrically connected to the first intermediate line, and a second overlying line in the overlying wiring layer electrically connected t

Abstract: Integrated circuit packages that connect solder balls between solder ball pads of a die and substrate pads of a printed circuit board (PCB). The solder balls are electrically disconnected from any circuit of the die, i.e., “dummy” solder balls, and are used to temporarily hold the die in position with respect to the PCB until the circuit is wire bonded and an underfill material is cured between the die and the PCB to more permanently connect them together. The underfill material is selected to have a coefficient of thermal expansion (CTE) that is substantially equal to the CTE of the solder balls to prevent thermal mismatch problems. An overmolding compound is disposed about the die and the underfill material and about the wire bonds to complete the package. Various arrangements of the solder ball pads on the die include columnar and row, corner, diagonal, cross, and periphery arrangements.

Abstract: An interconnect of the group III-V semiconductor device and the fabrication method for making the same are described. The interconnect includes a first adhesion layer, a diffusion barrier layer for preventing the copper from diffusing, a second adhesion layer and a copper wire line. Because a stacked-layer structure of the first adhesion layer/diffusion barrier layer/second adhesion layer is located between the copper wire line and the group III-V semiconductor device, the adhesion between the diffusion barrier layer and other materials is improved. Therefore, the yield of the device is increased.

Abstract: A wire bond pad and method of fabricating the wire bond pad. The method including: providing a substrate; forming an electrically conductive layer on a top surface of the substrate; patterning the conductive layer into a plurality of wire bond pads spaced apart; and forming a protective dielectric layer on the top surface of the substrate in spaces between adjacent wire bond pads, top surfaces of the dielectric layer in the spaces coplanar with coplanar top surfaces of the wire bond pads.

Abstract: Particular embodiments of the present invention provide a leadframe suitable for use in packaging IC dice that enables stress reduction in and around the die, die attach material, die attach pad and mold interfaces. More particularly, various leadframes are described that include recesses in selected regions of the top surface of the die attach pad.

Abstract: A photoelectric conversion apparatus includes: a first interlayer insulation film disposed on a semiconductor substrate; a first plug disposed in a first hole in the first interlayer insulation film, and serving to electrically connect between a plurality of active regions disposed in the semiconductor substrate, between gate electrodes of a plurality of MOS transistors, or between the active region and the gate electrode of the MOS transistor, not through the wiring of the wiring layer; and a second plug disposed in a second hole in the first interlayer insulation film, the second plug being electrically connected to the active region, wherein a wiring arranged over the second plug and closest to the second plug is electrically connected to the second plug, and the wiring electrically connected to the second plug forms a portion of dual damascene structure. By such a structure, incidence efficiency of light onto a photoelectric conversion element can be improved.

Abstract: An active-matrix device includes a device substrate including a plurality of pixels formed thereon, each pixel having a separate control electrode, a plurality of chiplets having at least first and second corresponding chiplets disposed at different locations over the device substrate, a plurality of wires formed over the device substrate, each wire being connected to a connection pad and to a different pixel control electrode, and wherein the shape of at least one of the wires connecting a connection pad for the first chiplet is different from the shape of at least one of the wires connecting a corresponding connection pad for the second chiplet.

Abstract: A method of manufacture of an integrated circuit communication system including providing a semiconductor wafer; and fabricating a cross-over current mirror driver on the semiconductor wafer for generating a crossing point at a reference voltage.

Abstract: An integrated circuit and method for fabrication includes first and second structures, each including a set of sub-lithographic lines, and contact landing segments connected to at least one of the sub-lithographic lines at an end portion. The first and second structures are nested such that the sub-lithographic lines are disposed in a parallel manner within a width, and the contact landing segments of the first structure are disposed on an opposite side of a length of the sub-lithographic lines relative to the contact landing segments of the second structure. The contact landing segments for the first and second structures are included within the width dimension, wherein the width includes a dimension four times a minimum feature size achievable by lithography.

Abstract: A programmable semiconductor device has a switch element in an interconnection layer, wherein in at least one of the inside of a via, interconnecting a wire of a first interconnection layer and a wire of a second interconnection layer, a contact part of the via with the wire of the first interconnection layer and a contact part of the via with the wire of the second interconnection layer, there is provided a variable electrical conductivity member, such as a member of an electrolyte material. The via is used as a variable electrical conductivity type switch element or as a variable resistance device having a contact part with the wire of the first interconnection layer as a first terminal and having a contact part with the wire of the second interconnection layer as a second terminal.

Abstract: One aspect of the present invention is a semiconductor device including: a semiconductor substrate; a first wiring that is formed on the semiconductor substrate; a second wiring that is formed to cross over the first wiring with a space interposed therebetween at a cross portion in which the first wiring and the second wiring cross each other; a protective film that is formed on the semiconductor substrate to cover at least a part of the first wiring, the part being located under the second wiring in the cross portion; and an insulator film that is formed in an island shape on the protective film under the second wiring in the cross portion to be located between edges of the protective film and to cover the first wiring in the cross portion.

Abstract: A memory device has a sidewall insulating member with a sidewall insulating member length according to a first spacer layer thickness. A first electrode formed from a second spacer layer having a first electrode length according to a thickness of a second spacer layer and a second electrode formed from the second spacer layer having a second electrode length according to the thickness of the second spacer layer are formed on sidewalls of the sidewall insulating member. A bridge of memory material having a bridge width extends from a top surface of the first electrode to a top surface of the second electrode across a top surface of the sidewall insulating member, wherein the bridge comprises memory material.

Abstract: A power semiconductor device has a semiconductor chip stack and lines within a housing. The lines electrically connect large-area contact regions of power semiconductor device components within the housing to one another. In this case, at least one of the lines has a large-area planar conductive layer. This planar conductive area electrically connects the large-area contact regions to one another.

Abstract: One or more embodiments are related to a semiconductor structure, comprising: a semiconductor chip; a conductive layer comprising at least a first conductive pathway and a second conductive pathway spacedly disposed from the first conductive pathway, the first conductive pathway electrically coupled to the chip, at least a portion of the first conductive pathway disposed outside the lateral boundary of the chip, at least a portion of the second conductive pathway disposed outside the lateral boundary of the chip; and a conductive interconnect disposed outside the lateral boundary of the chip, the conductive interconnect electrically coupling the first conductive pathway to the second conductive pathway.

Abstract: A semiconductor device includes a first wiring layer, a second wiring layer and a third wiring layer. The first wiring layer is formed on a semiconductor substrate. The second and the third wiring layer wiring layers are arranged in a direction intersecting with the first wiring layer on respective sides of the wiring layer. An air bridge wiring intersects the second and third wiring layers sandwiching an air layer above the first wiring layer therewith. The overall shape of the air bridge wiring has an upward convex curvature in an arch shape and the transverse sectional shape of the air bridge wiring is in the form of a downward concave curvature.

Abstract: Provided is a semiconductor memory module allowing a filling member formed between a module substrate and memory chips mounted on the module substrate to completely fill the space between the module substrate and the memory chips. According to embodiments of the present invention, the semiconductor memory module includes a module substrate having at least one memory chip mounted on the substrate such that its edges are oblique to major and minor axes bisecting the module substrate. The oblique orientation allows for an improved opening between memory chips formed on the substrate so that the filling member may be properly formed between the module substrate and the memory chips to prevent voids where the filling member is not formed.

Abstract: A semiconductor device having redistribution interconnects in the WPP technology and improved reliability, wherein the redistribution interconnects have first patterns and second patterns which are electrically separated from each other within the plane of the semiconductor substrate, the first patterns electrically coupled to the multi-layer interconnects and the floating second patterns are coexistent within the plane of the semiconductor substrate, and the occupation ratio of the total of the first patterns and the second patterns within the plane of the semiconductor substrate, that is, the occupation ratio of the redistribution interconnects is 35 to 60%.

Abstract: A semiconductor device with improved bondability between a wire and a bump and cutting property of the wire to improve the bonding quality. In the semiconductor device, a wire is stacked on a pad as a second bonding point to form a bump having a sloped wedge and a first bent wire convex portion, and a wire is looped from a lead as a first bonding point to the bump and is pressed to the sloped wedge of the bump with a face portion of a tip end of a capillary to bond the wire to the bump. At the same time, the wire is pressed to the first bent wire convex portion using an inner chamfer of a bonding wire hole in the capillary to form a wire bent portion having a bow-shaped cross section. The wire is pulled up and cut at the wire bent portion.

Abstract: A nonvolatile memory device, includes: a lower side electrode aligned in a first direction; an upper side electrode positioned above the lower side electrode and aligned in a second direction intersecting the first direction; and a memory unit provided between the lower side electrode and the upper side electrode. At least one selected from the lower side electrode and the upper side electrode includes a first electrode and a second electrode, the first electrode having a forward-tapered side wall, the second electrode having a reverse-tapered side wall and being adjacent to the first electrode via an insulating layer in substantially identical plane.

Abstract: Semiconductor structures are disclosed including a substrate comprising a semiconductor material and having opposed first and second surfaces, and at least one conductive via extending from the first surface to the second surface. The conductive vias can extend at angles relative to the first surface, such as acute angles or 90°. The conductive vias can include segments that extend at different angles. Methods of forming conductive vias in semiconductor structures are provided. In the methods, a thermal gradient is applied in combination with an electric field to form conductive vias.

Abstract: A method for forming a semiconductor die and a flip-chip integrated circuit device are disclosed that include a power and ground mesh that is oriented diagonally. A layout of a semiconductor die is formed by generating a first integrated circuit design and copying and rotating the design so as to form three additional integrated circuit design blocks. The power and ground mesh layer includes four overlying sets of power and ground strips that are oriented diagonally and symmetric. Because the power and ground strips of the present invention are angled and correspond to the underlying integrated circuit design, they allow for powering both rotated and non-rotated logic while maintaining identical interconnection points and capacitive loading across all the repeated blocks. In addition, the angled power and ground strips allow for easily coupling power and ground to structures around the periphery of the power and ground strips.

Abstract: A wiring board includes a film base, a plurality of conductive wirings aligned on the film base, and protrusion electrodes formed of a plated metal in the vicinity of end portions of the conductive wirings, respectively. An outer surface at both side portions of the protrusion electrodes in cross section in a width direction of the conductive wirings defines a curve, and the protrusion electrodes in cross section in a longitudinal direction of the conductive wirings define a rectangular shape. The conductive wirings include a first conductive wiring having a wiring width of W1 and a second conductive wiring having a wiring width of W2 larger than W1, and the protrusion electrode on the first conductive wiring and the protrusion electrode on the second conductive wiring have a substantially same height.

Abstract: A mountable integrated circuit package system includes: forming a base integrated circuit package system includes: providing a first substrate, and forming a package encapsulation having a cavity over the first substrate with the first substrate partially exposed within the cavity; and mounting an interposer including a central aperture over the package encapsulation and the first substrate with the central aperture over the cavity.

Abstract: An electrical circuit includes at least two unit cells configured on a planar substrate which extends in one plane. The unit cells respectively have at least two contact points with a different function and include at least one dielectric layer disposed on the substrate and/or on the unit cells and at least two contact surfaces which are disposed parallel to the plane above the contact points and/or the substrate. The contact points with the same function are connected electrically to at least one common contact surface for at least a part of the contact points of the same function via at least one through-contacting through the dielectric layer and able to be contacted in common from outside via the corresponding contact surfaces.

Abstract: A semiconductor device includes a first metal region, a plurality of vias, a plurality of second metal regions, a plurality of openings and a third metal region. The first metal region conducts source/drain current. The second metal regions are electrically connected to the first metal region through the vias for conducting the source/drain current, in which each of the second metal regions is disposed in a distance from the adjacent second metal regions. The third metal region is electrically connected to the second metal regions through the openings, in which the resistance of the third metal region is smaller than the resistances of the first metal region and the second metal regions.

Abstract: A wiring substrate having variously sized ball pads, a semiconductor package including the wiring substrate, and a stack package using the semiconductor package, to improve board level reliability (BLR) of a semiconductor package or stack package mounted on a mother board are shown. Outer ball pads are formed to have relatively greater surface areas at the corners of the semiconductor package as compared to those at other areas and are formed to have the greatest surface area within a designable range. Additionally, occurrence of cracks may be inhibited at junctions of other solder balls by forming dummy solder pads at the outermost corners among the outer ball pads formed proximate to the corners of the wiring substrate. Stress arising during a board level reliability test is absorbed without product failure at junctions between the dummy solder pads and dummy solder balls.

Abstract: A power semiconductor arrangement is provided that includes a power semiconductor chip being electrically connected to a set of plug-like elements with at least two plug-like elements and further including a sheet metal strip line including a set of openings receiving the first set of plug-like elements, where the set of openings in the sheet metal strip line and the set of plug-like elements establish a press fit connection.

Abstract: Embodiments of the invention include a semiconductor integrated circuit package that includes a substrate having an integrated circuit die attached thereto. The substrate further includes at least one signal layer having a plurality of electrical signal traces formed thereon. The package includes a discrete non-active electrical component mounted on the package so that the integrated circuit die is electrically connected with an electrical signal trace of the package through the discrete non-active electrical component. And in one particular implementation, the discrete non-active electrical component comprises a capacitive element arranged in series between the electrical signal traces and the die so that the capacitor operates as a package mounted AC coupling capacitor.

Abstract: A semiconductor device is provided with a first insulating film, a first wiring layer formed in the first insulating film, a second insulating film formed above the first wiring layer and the first insulating film, the second insulating film including a low dielectric constant film, a second wiring layer formed in the second insulating film and coupled to the first wiring layer through a first connection section, and a third insulating film formed above the second wiring layer and the second insulating film and serving as one of an interlayer insulating film and a passivation film, and at least one of the first and third insulating films being one of a film formed mainly of SiON, a film formed mainly of SiN, and a laminated film being the films formed mainly of SiON or SiN respectively.