Abstract: An adhesive film includes an amine curing agent and a phenolic curing agent, and has a ratio of a storage modulus at 170° C. after 80% or more curing to a storage modulus at 40° C. before curing in the range of about 1.5 to about 3.0.

Abstract: A method for producing a rollable web with successive antennas, where an electronic chip is attached to an antenna in a predetermined position. The position of an electronic chip changes with respect to the antenna when compared to at least some of the chips within individual and successive antennas. A rollable web includes successive antennas, where electronic chips are attached to antennas in a predetermined position. In the rollable web, the position of a chip changes with respect to the antenna compared to at least some of the chips within individual and successive antennas.

Abstract: A chip package includes a substrate, a pad positioned on the substrate, a base board, at least one adhesive layer and at least one chip. The base board is positioned on the pad. At least one mounting hole is defined through the base board. The at least one adhesive layer is received in the at least one mounting hole. The at least one chip is received in the at least one mounting hole and adhere to the pad via the at least one adhesive layer.

Abstract: A substrate for a semiconductor package is provided having first and second core layers defining a cavity having an adhesive member and sized and shaped to receive a semiconductor chip. The semiconductor package further having a connection member formed on a bond finger and connected to a via pattern formed through the first and second core layers. A stack package is also provided having multiple substrates.

Abstract: An electrooptical device substrate, contains: a first insulating film provided on a substrate; two or more pixels; a first concave portion provided in the first insulating film over the two or more pixels; a second concave portion provided on the bottom surface of the first concave portion; a thin film transistor containing an organic semiconductor layer provided in the second concave portion, a gate insulating film provided on the organic semiconductor layer, and a gate electrode provided on the gate insulating film and being matched to one pixel among the two or more pixels; a scanning line which is provided at an upper side with respect to the gate insulating film and provided in the first concave portion over the two or more pixels; and a data line electrically connected to the thin film transistor.

Abstract: A semiconductor apparatus includes a semiconductor chip in which a plurality of electrode pads are provided on a main surface, and a plurality of bump electrodes are provided on the electrode pads of the semiconductor chip. The semiconductor apparatus also includes a wired board which is allocated in a side of the main surface of the semiconductor chip, and is positioned in a central area of the main surface of the semiconductor chip so as to be separated from an edge part of the semiconductor chip by at least 50 ?m or more. The semiconductor apparatus also includes a plurality of external terminals which are provided on the wired board, and which are electrically connected to a plurality of bump electrodes through wirings of the wired board, and sealing part which is provided between the semiconductor chip and the wired board, is made of underfill material that covers a connection part between the bump electrode and the wiring.

Abstract: It is an object to provide a semiconductor device integrating various elements without using a semiconductor substrate, and a method of manufacturing the same. According to the present invention, a layer to be separated including an inductor, a capacitor, a resistor element, a TFT element, an embedded wiring and the like, is formed over a substrate, separated from the substrate, and transferred onto a circuit board 100. An electrical conduction with a wiring pattern 114 provided in the circuit board 100 is made by a wire 112 or a solder 107, thereby forming a high frequency module or the like.

Abstract: A semiconductor device bonded by an anisotropic conductive adhesive composition, the anisotropic conductive adhesive composition having a solid content ratio between a polymer binder system and a curing system of about 40:60 to about 60:40, and a coefficient of thermal expansion of about 150 ppm/° C. or less at about 100° C. or less.

Abstract: Provided is a method of manufacturing a semiconductor device capable of adhering semiconductor elements and a support member for mounting semiconductor elements, such as lead frames, organic substrates or the like, even in a relatively low temperature range without damaging adhesion property and workability and of suppressing the occurrence of voids.

Abstract: A method and structure for uncovering captive devices in a bonded wafer assembly comprising a top wafer and a bottom wafer. One embodiment method includes forming a plurality of cuts in the top wafer and removing a segment of the top wafer defined by the plurality of cuts. The bottom wafer remains unsingulated after the removal of the segment.

Abstract: A chip-to-chip multi-signaling communication system with common conductive layer, which comprises a first chip, a second chip, and a common conductive layer, is disclosed. The first chip has at least a first metal pad and a second metal pad. The second chip has at least a first metal pad and a second metal pad. The common conductive layer is to a conductive material and glued directly to the first chip and the second chip. Wherein, the first metal pad of the second chip is aligned with the first metal pad of the first chip for receiving the signal from the first metal pad of the first chip through the common conductive layer. The interference generated by other pads of the first and the second chips is suppressed by the design of the pads and the common conductive layer.

Abstract: A semiconductor device may include: first and second wiring boards separated from each other via a gap; a semiconductor chip; first and second groups of electrode pads; and first and second groups of connection pads. The semiconductor chip is fixed to upper surfaces of the first and second wiring boards, and has a first portion adjacent to the gap. The first and second groups of electrode pads are disposed on the first portion. The first and second groups of electrode pads are aligned adjacent to side surfaces of the first and second wiring boards, respectively. The side surfaces of the first and second wiring boards face each other. The first and second groups of connection pads are disposed on lower surfaces of the first and second wiring boards, respectively. The first and second groups of connection pads are aligned adjacent to the side surfaces of the first and second wiring boards, respectively.

Abstract: A semiconductor device includes a semiconductor element, a support member bonded to a first surface of the semiconductor element with a first bonding material and a lead electrode bonded to a second surface of the semiconductor element supported on the support member with a second bonding material, and further including a method of producing the semiconductor device. Respective connecting parts of the support member and the lead electrode are Ni-plated and each of the first and the second bonding material is a Sn solder having a Cu6Sn5 content greater than a eutectic content.

Abstract: A method for manufacturing an integrated circuit package in package system includes: providing a substrate having a first wire-bonded die with an active side mounted above; connecting the active side of the first wire-bonded die to the substrate with a bond-wire; mounting a wire-in-film adhesive having an isolation barrier over the first wire-bonded die; and encapsulating the first wire-bonded die, the bond-wires, and the wire-in-film adhesive with an encapsulation.

Abstract: A semiconductor device includes a semiconductor element having a plurality of element electrodes formed thereon, a circuit board having board electrodes respectively corresponding to the element electrodes formed thereon and having the semiconductor element mounted thereon, and bumps each of which is provided on at least one of the element electrode and the board electrode, and connects together the element electrode and the board electrode corresponding to each other when the semiconductor element is mounted on the circuit board. Furthermore, at least one of a dielectric layer and a resistive layer is provided between at least one of the bumps and the element or board electrode on which the at least one of the bumps is provided, so that the element or board electrode, the dielectric layer or the resistive layer, and the bump form a parallel-plate capacitor or electrical resistance.

Abstract: A semiconductor device (1,21) includes a solid state device (2,22), a semiconductor chip (3) that has a functional surface (3a) on which a functional element (4) is formed and that is bonded on a surface of the solid state device with the functional surface thereof facing the surface of the solid state device and while maintaining a predetermined distance between the functional surface thereof and the surface of the solid state device, an insulating film (6) that is provided on the surface (2a, 22a) of the solid state device facing the semiconductor chip and that has an opening (6a) greater in size than the semiconductor chip when the surface of the solid state device facing the semiconductor chip is vertically viewed down in plane, and a sealing layer (7) that seals a space between the solid state device and the semiconductor chip.

Abstract: In one embodiment, a method includes attaching a film to cover a first portion of a first semiconductor die. The first semiconductor die is attached, using the tape, to a lead frame using a first bonding method. The first bonding method places the film between the lead frame and the semiconductor die. A second semiconductor die is attached to the lead frame using a second bonding method. The second bonding method bonds the lead frame and the semiconductor die. The first semiconductor device and the second semiconductor device are encapsulated into a semiconductor package.

Abstract: A semiconductor device has a flipchip or PoP semiconductor die mounted to a die attach area interior to a substrate. The substrate has a contact pad area around the die attach area and flow control area between the die attach area and contact pad area. A first channel is formed in a surface of the substrate within the flow control area. The first channel extends around a periphery of the die attach area. A first dam material is formed adjacent to the first channel within the flow control area. An underfill material is deposited between the die and substrate. The first channel and first dam material control outward flow of the underfill material to prevent excess underfill material from covering the contact pad area. A second channel can be formed adjacent to the first dam material. A second dam material can be formed adjacent to the first channel.

Abstract: A photosensitive adhesive composition comprising: (A) a polyimide having a carboxyl group as a side chain, whereof the acid value is 80 to 180 mg/KOH; (B) a photo-polymerizable compound; and (C) a photopolymerization initiator.

Abstract: A method of attaching a die to a carrier using a temporary attach material is disclosed. The method comprises attaching the temporary attach material between a surface of the die and a surface of the carrier. The temporary attach material attaches the die to the carrier. The method comprises bonding at least one connector to the die and the carrier. The connector includes a first end bonded to the carrier and a second end bonded to the die. The method further comprises encapsulating at least a portion of the die and at least a portion of the at least one connector by an encapsulation material.

Abstract: A chip package includes a substrate, a pad, a double-sided adhesive tape, a chip, and a sealing member. The pad is arranged on the substrate and has a top surface facing away from the substrate. The double-sided adhesive tape includes a first paste surface and an opposing second paste surface. The first paste surface is attached to the top surface. The chip is attached onto the second paste surface and includes a light emitting surface or a light receiving surface facing away from the second paste surface. The sealing member is formed on the pad and tightly surrounds the chip and the double-sided adhesive.

Abstract: A method of assembling an electronic device and electronic packages therefrom. A die attach adhesive precursor is placed between a top surface of a workpiece and an IC die. The die attach adhesive precursor includes metal particles, a first plurality of first microcapsules having a polymerizable material inside, and a second plurality of second microcapsules having a polymerization agent inside to form a first polymer upon rupture of first and second microcapsules. A force sufficient to rupture at least a portion of the first plurality of first microcapsules and at least a portion of the second plurality of second microcapsules is applied to form a self-healing die attach adhesive wherein the first polymer binds the plurality of metal particles and the remaining microcapsules and secures the IC die to the top surface of the workpiece. The self-healing die attach adhesive generally includes at least 90 vol. % metal.

Abstract: A patterned adhesive layer including holes is employed to attach a coreless substrate layer to a stiffner. The patterned adhesive layer is confined to kerf regions, which are subsequently removed during singulation. Each hole in the patterned adhesive layer has an area that is greater than the area of a bottomside interconnect footprint of the coreless substrate. The patterned adhesive layer may include a permanent adhesive that is thermally curable or ultraviolet-curable. The composition of the stiffner can be tailored so that the thermal coefficient of expansion of the stiffner provides tensile stress to the coreless substrate layer at room temperature and at the bonding temperature. The tensile stress applied to the coreless substrate layer prevents or reduces warpage of the coreless substrate layer during bonding. Upon dicing, bonded stacks of a semiconductor chip and a coreless substrate can be provided without adhesive thereupon.

Abstract: Disclosed herein is a semiconductor package substrate including a base substrate, a mounting member mounted on an upper portion of the base substrate, and an adhesive layer formed between the base substrate and the mounting member, wherein the adhesive layer includes a thermally conductive adhesive and a ductile adhesive formed at the outer circumference of the thermally conductive adhesive.

Abstract: The adhesive composition of the invention comprises (A) a thermoplastic resin with a Tg of no higher than 100° C. and (B) a thermosetting component, wherein the (B) thermosetting component includes (B1) a compound with an allyl group and (B2) a compound with a maleimide group.

Abstract: A chip module and a fabricating method thereof are provided. Firstly, a substrate is provided. Next, a chip is assembled on the substrate and electrically connected with the substrate. Afterward, a plurality of passive units is assembled on the substrate in the style of encircling the chip. Then, a first glue structure is filled between the passive units so that an encircled area is defined by the first glue structure and the passive units. Then, a second glue structure is filled in the encircled area so that the chip is covered by the second glue structure.

Abstract: An adhesive flexible barrier film comprises a substrate and a barrier layer disposed on the substrate. The barrier layer is formed from a barrier composition comprising an organosilicon compound. The adhesive flexible barrier film also comprises an adhesive layer disposed on the barrier layer and formed from an adhesive composition. A method of forming the adhesive flexible barrier film comprises the steps of disposing the barrier composition on the substrate to form the barrier layer, disposing the adhesive composition on the barrier layer to form the adhesive layer, and curing the barrier layer and the adhesive layer. The adhesive flexible barrier film may be utilized in organic electronic devices.

Abstract: A semiconductor device comprises a wiring substrate including a wiring pattern; a semiconductor chip installed on the wiring substrate, including a plurality of pads formed on a surface of the semiconductor chip, which opposes the wiring substrate; a first resin layer covering over a part of the wiring pattern within a region of overlapping the semiconductor chip; and a second resin layer installed between the semiconductor chip and the first resin layer. The pads are oppose to and coupled with a part of the wiring pattern exposed over the first resin layer; and the linear expansion coefficient of the wiring substrate is larger than that of the semiconductor chip, the elastic modulus of the wiring substrate is lower than that of the semiconductor chip and the linear expansion coefficient of the first resin layer is larger than that of the second resin layer. The elastic modulus of the first resin layer is lower than that of the second resin layer.

Abstract: A semiconductor device is provided in which a semiconductor chip is bonded to a substrate with a sufficiently increased bonding strength and cracking is assuredly prevented which may otherwise occur due to heat shock, heat cycle and the like. The semiconductor device includes a semiconductor chip and a substrate having a bonding area to which the semiconductor chip is bonded via a metal layer. The metal layer includes an Au—Sn—Ni alloy layer and a solder layer provided on the Au—Sn—Ni alloy layer. Undulations are formed in an interface between the Au—Sn—Ni alloy layer and the solder layer.

Abstract: Electronic devices and methods for fabricating electronic devices are described. One method includes providing a substrate with a die attach area, and forming a layer on the substrate outside of the die attach area. The layer may be formed from a fluoropolymer material. The method also includes coupling a die to the substrate in the die attach area, wherein a gap remains between the die and the die attach area. The method also includes placing an underfill material in the gap and adjacent to the layer on the substrate. Examples of fluoropolymer materials which may be used include polytetrafluoroethylene (PTFE) and perfluoroalkoxy polymer resin (PFA). Other embodiments are described and claimed.

Abstract: An electronic component, in which the outer perimeter portion of a component (2) is surrounded with a first sealing resin (4), a second sealing resin (3) is filled within the periphery of the first sealing resin (4), the component (2) and a board (1) are electrically connected by a wire (5), the edge, in the vicinity of which the wire (5) passes, of the outer perimeter edge portions of the component (2) is formed to be a chamfered oblique surface (31), and the wire (5) is provided to extend to the board (1) along the oblique surface (31). By this means, the overall height of the electronic component can be kept low.

Abstract: A semiconductor device has a base substrate having a plurality of metal traces. A conductive polymer cover is provided having an opening. The conductive polymer cover forms a cavity when attached to the base substrate. At least one die is attached to an interior surface of the conductive polymer cover and positioned over the opening. The conductive polymer cover and the at least one die are electrically coupled to metal traces on the first surface of the base substrate.

Abstract: Conductive compositions which are useful as thermally conductive compositions and may also be useful as electrically conductive compositions are provided. The compositions include a conductive particle constituent in combination with a sintering aid which can, for example be a compound of the same metal in the nanometal, an organo-metallic, a metalorganic salt, mercaptan and/or resinate. In some embodiments the conductive particles include a small amount of nanoscale (<200 nm) particles. The compositions exhibit increased thermal conductivity.

Abstract: Apparatus and methods for providing a molded chip interposer structure and assembly. A molded chip structure having at least two integrated circuit dies disposed within a mold compound is provided having the die bond pads on the bottom surface; and solder bumps are formed in the openings of a dielectric layer on the bottom surface, the solder bumps forming connections to the bond pads. An interposer having a die side surface and a board side surface is provided having bump lands receiving the solder bumps of the molded chip structure on the die side of the interposer. An underfill layer is formed between the die side of the interposer and the bottom surface of the molded chip structure surrounding the solder bumps. Methods for forming the molded chip interposer structure are disclosed.

Abstract: A thermally enhanced electronic package comprises a chip, a substrate, an adhesive, and an encapsulation. The adhesive or the encapsulation is mixed with carbon nanocapsules. The substrate includes an insulation layer and a wiring layer formed on the substrate. The adhesive covers the chip and the substrate. The chip is electrically connected to the wiring layer. The encapsulation covers the chip and the substrate.

Abstract: A semiconductor device for use in a printed circuit board is provided. In the semiconductor device, metal pillars are disposed perpendicular to bond pads of a semiconductor die. This configuration eliminates the need to form via holes for the connection of interconnection layers and the bond pads of the semiconductor die, thus simplifying the fabrication procedure of the semiconductor device. In addition, the semiconductor die is embedded in the semiconductor device. Based on this configuration, the use of the semiconductor device in a printed circuit board facilitates the stacking of a plurality of semiconductor dies and can reduce the thickness required for the stack, which make the semiconductor device light in weight and small in thickness and size.

Abstract: A fabrication method of a chip scale package includes: disposing a chip on a carrier board and embedding the chip into a composite board having a hard layer and a soft layer; and removing the carrier board so as to perform a redistribution layer (RDL) process, thereby solving the conventional problems caused by directly attaching the chip on an adhesive film, such as film-softening caused by heat, encapsulant overflow, chip deviation and contamination, etc., all of which may result in poor electrical connection between the wiring layer and the chip electrode pads in the subsequent RDL process and even waste products as a result.

Abstract: A microelectronic package and method of making same are provided. The package includes a substrate having first and second opposed surfaces, an edge surface extending therebetween, a plurality of terminals, and a plurality of conductive elements electrically connected with the terminals. The edge surface can be disposed at a periphery of the substrate or can be the edge surface of an aperture within the substrate. A microelectronic element has a front face and contacts thereon, with at least some of the contacts being adjacent to the edge surface of the substrate. A dielectric material overlies the edge surface of the substrate and defines a sloping surface between the front face of the microelectronic element and the substrate. A conductive matrix material defines a plurality of conductive interconnects extending along the sloping surface. The conductive interconnects electrically interconnect respective ones of the contacts with the conductive elements.

Abstract: In one embodiment, a method for forming a multi-component power structure for use in electrically propelled vehicles may include constraining a parent material system between a power component and a thermal device. The parent material system may include a low temperature material having a relatively low melting point and a high temperature material having a relatively high melting point. The relatively low melting point may be less than the relatively high melting point. The parent material system can be heated to a melting temperature greater than the relatively low melting point and lower than the relatively high melting point to diffuse the low temperature material into the high temperature material. The parent material system can be solidified to form a transient liquid phase bond that is electrically and thermally conductive.

Abstract: A mounting structure formed by bonding the electrodes of a substantially planar electronic component to the electrodes provided on the mounting surface of a circuit board includes a sealing body 5 formed between one main surface of the electronic component and the circuit board and/or on the other main surface of the electronic component. The sealing body 5 is composed of a plurality of layers having different adhesive strengths and thermal conductivities, wherein a layer having a relatively high adhesion strength is arranged in a region being in contact with either one of the electronic component and the circuit board, and a layer having a relatively high thermal conductivity is arranged in a region being in contact with none of the electronic component and the circuit board.

Abstract: Methods of forming a microelectronic packaging structure and associated structures formed thereby are described. Those methods may include forming a cavity in a carrier material, attaching a die in the cavity, wherein a backside of the die comprises a metal filled DBF, forming a dielectric material adjacent the die and on a bottom side of the carrier material, forming a coreless substrate by building up layers on the dielectric material, and removing the carrier material from the coreless substrate.

Abstract: A connection structure comprising an adhesive composition is provided. The adhesive composition is capable of providing good adhesion strength to the polyimide surface of a flexible circuit board that is exposed on the metal wiring surface and between the traces even when the polyimide surface is relatively smooth. The adhesive composition contains a thermoplastic resin, a polyfunctional acrylate, and a radical polymerization initiator and further contains a monofunctional urethane acrylate having a urethane residue at its terminal end. The monofunctional urethane acrylate is represented by the formula (1): CH2?CR0—COO—R1—NHCOO—R2??(1) wherein R0 is a hydrogen atom or a methyl group, R1 is a divalent hydrocarbon group, and R2 is an optionally substituted lower alkyl group.

Abstract: A method of attaching members is provided. In one aspect, the method includes placing a bonding material comprising at least one of silver micro particles)and silver nano particles on a surface of a first member; placing the first member with the surface of the first member having the bonding material thereon on a surface of a second member; heating the bonding material to a selected temperature while applying a selected pressure on at least one of the first member and second member for a selected time period to sinter the bonding material to attach the first member to the second member.

Abstract: This description relates to a semiconductor device including a wafer having a first surface and a second surface opposite to the first surface and a carrier attached to the first surface of the wafer by an adhesive layer, a portion of the adhesive layer adjacent to an edge of the wafer is exposed. The semiconductor device further includes a protection layer to cover the exposed portion of the adhesive layer. The semiconductor device further includes a plurality of dies attached to the second surface and a molding compound encapsulating the plurality of dies.

Abstract: There is provided a method of removing trap levels and defects, which are caused by stress, from a single crystal silicon thin film formed by an SOI technique. First, a single crystal silicon film is formed by using a typical bonding SOI technique such as Smart-Cut or ELTRAN. Next, the single crystal silicon thin film is patterned to form an island-like silicon layer, and then, a thermal oxidation treatment is carried out in an oxidizing atmosphere containing a halogen element, so that an island-like silicon layer in which the trap levels and the defects are removed is obtained.

Abstract: A multifunction tape for a semiconductor package and configured to bond to a device-formed side of a semiconductor substrate having a plurality of devices thereon while performing a process of grinding a side of the semiconductor substrate opposite to the device-formed side and a process of dicing the semiconductor substrate into individual chips with a dicing tape having a UV-curable adhesive layer bonded to the ground side of the semiconductor substrate, the multifunction tape being bonded to the individual chips while the individual chips, separated from each other by the dicing process, are picked up and die-attached and a method of manufacturing a semiconductor device using the same, the multifunction tape including a base film; a UV-curable adhesive layer on one side of the base film; and first and second bonding layers on the adhesive layer.

Abstract: In a pressure-sensitive adhesive composition or a pressure-sensitive adhesive sheet containing an energy ray-curable polymer, problems associated with the volatilization of a low molecular weight compound contained in the composition are overcome. An energy ray-curable polymer characterized by comprising a radical generating group, which is capable of initiating a polymerization reaction upon excitation with an energy ray, and an energy ray-polymerizable group bonded together in the main or side chain.

Abstract: The adhesive composition of the invention comprises a radical generator, a thermoplastic resin and a urethane (meth)acrylate having two or more radical-polymerizing groups in the molecule and a weight-average molecular weight of 3000-30,000.

Abstract: A microelectronic assembly can include first, second and third stacked substantially planar elements, e.g., of dielectric or semiconductor material, and which may have a CTE of less than 10 ppm/° C. The assembly may be a microelectronic package and may incorporate active semiconductor devices in one, two or more of the first, second or third elements to function cooperatively as a system-in-a-package. In one example, an electrically conductive element having a minimum thickness less than 10 microns, may be formed by plating, and may electrically connect two or more of the first, second or third elements. The conductive element may entirely underlie a surface of another one of the substantially planar elements.

Abstract: In accordance with the present invention, there is provided a semiconductor package (e.g., a QFP package) including a uniquely configured leadframe sized and configured to maximize the available number of exposed leads in the semiconductor package. More particularly, the semiconductor package of the present invention includes a generally planar die pad or die paddle defining multiple peripheral edge segments. In addition, the semiconductor package includes a plurality of leads. Some of these leads include exposed bottom surface portions which are provided in at least one row or ring which at least partially circumvents the die pad, with other leads including portions which protrude from respective side surfaces of a package body of the semiconductor package. Connected to the top surface of the die pad is at least one semiconductor die which is electrically connected to at least some of the leads.