With Specified Encapsulant Patents (Class 257/788)
  • Publication number: 20100201003
    Abstract: Packaging systems and methods of manufacture are provided. In this regard, a representative system comprises a first layer of liquid crystal polymer (LCP), a first electronic component supported by the first layer, and a second layer of LCP. The first layer and the second layer encase the first electronic component.
    Type: Application
    Filed: November 23, 2005
    Publication date: August 12, 2010
    Inventors: Dane Thompson, Guoan Wang, Nickolas D. Kingsley, Ioannis Papapolymerou, Emmanouil M. Tentzeris
  • Publication number: 20100201004
    Abstract: A carbon/epoxy resin composition and a method of producing a carbon-epoxy dielectric using the same. The carbon/epoxy resin composition includes about 45 volume percent (volume %) to about 50 volume % of an epoxy composition, the epoxy composition including a bisphenol-based epoxy compound and an alicyclic epoxy compound, based on a total volume of the carbon/epoxy resin composition, about 2.0 volume % to about 3.1 volume % of carbon black, based on a total volume of the carbon/epoxy resin composition, about 80 parts by volume to about 104 parts by volume of an acid anhydride-based curing agent, based on 100 parts by volume of the epoxy composition, and about 1 part by volume to about 3 parts by volume of a tertiary alkylamine-based curing catalyst, based on 100 parts by volume of the epoxy composition.
    Type: Application
    Filed: July 27, 2009
    Publication date: August 12, 2010
    Applicant: SAMSUNG ELECTRONICS CO., LTD
    Inventors: Yoo-Seong YANG, Eun-Sung LEE, Sang-Soo JEE, Soon-Jae KWON
  • Publication number: 20100193971
    Abstract: A positive photosensitive resin composition for spray coating of the present invention is used for forming a coating film onto a substrate such as a semiconductor element mounting substrate, a ceramics substrate or an aluminium substrate by spray coating. The positive photosensitive resin composition is characterized by containing (A) an alkali soluble resin, (B) a compound which generates an acid by the action of light and (C) a solvent, and having a viscosity of 2 to 200 cP.
    Type: Application
    Filed: July 22, 2008
    Publication date: August 5, 2010
    Inventors: Toshio Banba, Hideki Orihara
  • Patent number: 7768140
    Abstract: A semiconductor device has a semiconductor chip bonded to external connection pads or external connection terminals by flip-chip bonding and an underfill resin, and provides a semiconductor device which enables to lessen the warpage attributable to the underfill without involvement of an increase in the size of the semiconductor device. A low elastic resin member is disposed opposite to a surface of a semiconductor chip on which a plurality of electrode pads are formed, and an underfill resin is filled between the semiconductor chip and the low elastic resin member and between electrode pads and external connection pads.
    Type: Grant
    Filed: September 25, 2007
    Date of Patent: August 3, 2010
    Assignee: Shinko Electric Industries Co., Ltd.
    Inventor: Kiyoshi Oi
  • Publication number: 20100187659
    Abstract: An inventive semiconductor device includes a semiconductor chip having a passivation film, and a sealing resin layer provided over the passivation film for sealing a front side of the semiconductor chip. The sealing resin layer extends to a side surface of the passivation film to cover the side surface.
    Type: Application
    Filed: March 26, 2010
    Publication date: July 29, 2010
    Applicant: ROHM CO., LTD.
    Inventors: Osamu Miyata, Masaki Kasai, Shingo Higuchi
  • Publication number: 20100181680
    Abstract: A semiconductor device includes: a mounted body in which a wiring pattern is formed on a first main surface; a semiconductor chip mounted on the surface of the mounted body on which the wiring pattern is formed; an underfill material which is filled between the mounted body and the semiconductor chip and forms a fillet on an outer peripheral part of the semiconductor chip; and an injection section which is disposed on the mounted body and on an outside of a side section, on which the fillet is formed to be longest, of four side sections defining a chip mount area on which the semiconductor chip is mounted, and guides the underfill material to between the mounted body and the semiconductor chip.
    Type: Application
    Filed: January 15, 2010
    Publication date: July 22, 2010
    Applicant: SONY CORPORATION
    Inventors: Yoshimichi Harada, Makoto Murai, Takayuki Tanaka, Takuya Nakamura
  • Publication number: 20100176517
    Abstract: Differences in contraction forces of a sealing resin can be alleviated and strain on a package can be reduced even when electronic components are unevenly positioned on a substrate. An electronic device (100) includes a substrate 102, electronic components (104, 108) mounted on one face of the substrate 102, and a sealing resin 118 formed on the one face of the substrate 102 and which seals the electronic components. The sealing resin 118 includes a first resin region 120 made up of a first resin composition and a second resin region 122 made up of a second resin composition, and is formed so as to have, as seen in planar view, a region in which only the first resin region 120 exists and a region in which only the second resin region 122 exists.
    Type: Application
    Filed: January 6, 2010
    Publication date: July 15, 2010
    Applicant: NEC ELECTRONICS CORPORATION
    Inventors: Yuichi Miyagawa, Jun Tsukano, Kenji Furuya, Takamitsu Noda, Hiroyasu Miyamoto
  • Patent number: 7750483
    Abstract: A semiconductor chip assembly includes a semiconductor chip that includes a conductive pad, a conductive trace that includes a routing line, a metal pillar and an enlarged plated contact terminal, a connection joint that electrically connects the routing line and the pad, and an encapsulant. The chip and the metal pillar are embedded in the encapsulant, the routing line extends laterally beyond the metal pillar towards the chip, the metal pillar is welded to the routing line and includes a ball bond and a stem, and the plated contact terminal is plated on the stem.
    Type: Grant
    Filed: October 26, 2006
    Date of Patent: July 6, 2010
    Assignee: Bridge Semiconductor Corporation
    Inventors: Charles W. C. Lin, Cheng-Chung Chen
  • Patent number: 7750451
    Abstract: A multi-chip package system is provided including providing a first carrier having a first integrated circuit die thereover, providing a second carrier, placing the first carrier coplanar with the second carrier, and molding a package encapsulation around and exposing the first carrier.
    Type: Grant
    Filed: February 7, 2007
    Date of Patent: July 6, 2010
    Assignee: Stats Chippac Ltd.
    Inventors: Zigmund Ramirez Camacho, Henry Descalzo Bathan, Lionel Chien Hui Tay, Arnel Trasporto
  • Publication number: 20100164126
    Abstract: The present invention provides a resin composition. The resin composition is used for a resin spacer provided in a semiconductor device. The semiconductor device comprises of a substrate, a semiconductor element mounted on an interposer so as to face the substrate, and the resin spacer provided between the substrate and the interposer or the semiconductor element for bonding them together in a state that a space is formed between the substrate and the semiconductor element. The resin composition comprises an alkali solubility resin, a photopolimerization resin, and a particulate filler. An average particle size of the particulate filler is in the range of 0.05 to 0.35 ?m. An amount of the particulate filler contained in the resin composition is in the range of 1 to 40 wt %. Further, the present invention also provides a resin spacer film. The resin spacer film is constituted of the resin composition described above.
    Type: Application
    Filed: May 23, 2008
    Publication date: July 1, 2010
    Applicant: Sumitomo Bakelite Company Limited
    Inventors: Toyosei Takahashi, Rie Takayama
  • Patent number: 7732936
    Abstract: Embodiments of buffer coatings for semiconductor and integrated circuit manufacturing are presented herein, wherein the buffer coating is provided by mechanically blending a first polymer with at least a second polymer. The mechanically blended polymers producing a buffer coating that provides a barrier that is has an increased toughness and decreased shrinkage.
    Type: Grant
    Filed: September 6, 2006
    Date of Patent: June 8, 2010
    Assignee: Intel Corporation
    Inventors: Michael D. Goodner, Kevin J. Lee
  • Patent number: 7728440
    Abstract: A semiconductor device includes: a semiconductor chip mounted on a mounting substrate; a first resin filling a gap between the chip and the substrate; a frame-shaped stiffener surrounding the chip; a first adhesive for bonding the stiffener to the substrate; a lid for covering the stiffener and an area surrounded by the stiffener; and a second resin filling a space between the stiffener and the chip. A thermal expansion coefficient of the second resin is smaller than that of the first resin. The first resin includes an underfill part filling a gap between the chip and the substrate and a fillet part extended from the chip region.
    Type: Grant
    Filed: January 23, 2004
    Date of Patent: June 1, 2010
    Assignee: NEC Electronics Corporation
    Inventor: Hirokazu Honda
  • Patent number: 7723744
    Abstract: Light-emitting devices are provided that incorporate one or more underlying LED chips or other light sources and a layer having one or more populations of nanoparticles disposed over the light source. The nanoparticles may absorb some light emitted by the underlying source, and re-emit light at a different level. By varying the type and relative concentration of nanoparticles, different emission spectra may be achieved. White light and specialty-color emission may be achieved. Devices also may include multiple LED chips, with nanoparticles disposed over one or more underlying chips in an array.
    Type: Grant
    Filed: December 7, 2007
    Date of Patent: May 25, 2010
    Assignee: Evident Technologies, Inc.
    Inventors: Jennifer Gillies, David Socha, Kwang-Ohk Cheon, Michael LoCasio
  • Patent number: 7723856
    Abstract: An epoxy resin composition for encapsulating semiconductors containing an epoxy resin, a phenol resin, an inorganic filler, a curing accelerator, a glycerol tri-fatty acid ester produced by dehydration condensation reaction of glycerol and a saturated fatty acid with a carbon atom content of 24-36, and a hydrotalcite compound as essential components is provided. The resin composition exhibits excellent mold releasability and produces only a slight amount of stains on the surfaces of the mold and semiconductor packages. A semiconductor device exhibiting excellent solder resistance is also provided.
    Type: Grant
    Filed: March 10, 2005
    Date of Patent: May 25, 2010
    Assignee: Sumitomo Bakelite Co., Ltd.
    Inventor: Daisuke Hirokane
  • Patent number: 7723852
    Abstract: In accordance with the present invention, there is provided multiple embodiments of a semiconductor package including two or more semiconductor dies which are electrically connected to an underlying substrate through the use of conductive wires, some of which may be fully or partially encapsulated by an adhesive or insulating layer of the package. In a basic embodiment of the present invention, the semiconductor package comprises a substrate having a conductive pattern disposed thereon. Electrically connected to the conductive pattern of the substrate are first and second semiconductor dies. The first semiconductor die and a portion of the substrate are covered by an adhesive layer. The second semiconductor die, the adhesive layer and a portion of the substrate are in turn covered by a package body of the semiconductor package.
    Type: Grant
    Filed: January 21, 2008
    Date of Patent: May 25, 2010
    Assignee: Amkor Technology, Inc.
    Inventors: Yoon Joo Kim, In Tae Kim, Ji Young Chung, Bong Chan Kim, Do Hyung Kim, Sung Chul Ha, Sung Min Lee, Jae Kyu Song
  • Publication number: 20100123142
    Abstract: Provided is a flat panel display apparatus including a sealant which has a small effective width and is able to effectively attach a substrate and an encapsulation substrate. The flat panel display apparatus includes the substrate, a display unit disposed on the substrate, the encapsulation substrate disposed facing the substrate so that the display unit is disposed on inner side of the encapsulation substrate, and the sealant attaching the substrate and the encapsulation substrate, wherein an end surface of the sealant facing the substrate contacts a silicon oxide layer disposed on the substrate.
    Type: Application
    Filed: July 30, 2009
    Publication date: May 20, 2010
    Applicant: Samsung Mobile Display Co., Ltd.
    Inventors: Ji-Hun Ryu, Sun-Young Jung, Seung-Yong Song, Young-Seo Choi, Oh-June Kwon, Kwan-Hee Lee
  • Patent number: 7709857
    Abstract: Provided is a light emitting diode package in accordance with the present invention including a lead frame composed of at least a pair of lead terminals; a mold receiving a part of the lead frame therein and equipped with an irradiation window opened to radiate light, and further including one or more holes formed to expose a part of a bottom surface of the lead frame received in the inside of the mold; an LED chip mounted on the lead frame positioned in the mold; an electrode connection unit for electrically connecting the LED chip and the lead frame; and a molding agent composed of any one selected from transparent epoxy, silicon, and phosphor blends charged in the mold and protecting the LED chip.
    Type: Grant
    Filed: April 24, 2008
    Date of Patent: May 4, 2010
    Assignee: Samsung Electro-Mechanics Co., Ltd.
    Inventors: Kyung Tae Kim, Bong Girl Min
  • Patent number: 7701073
    Abstract: The invention discloses integrated circuits (ICs), molded IC packages, and to leadframe arrays, package arrays and methods for their manufacture. Leadframe arrays and package arrays used for the manufacture of IC packages by transfer molding processes include a locking feature adapted for encapsulation. The locking feature is situated in a strap of the leadframe array overlying a gate between mold cavities. The strap lock formed by curing encapsulant in the locking feature of the strap strengthens the resulting package array and provides improved mold extraction and handling characteristics.
    Type: Grant
    Filed: September 18, 2007
    Date of Patent: April 20, 2010
    Assignee: Texas Instruments Incorporated
    Inventor: James R. Huckabee
  • Publication number: 20100084665
    Abstract: An electronically active sheet includes a bottom substrate having a bottom electrically conductive surface. A top substrate having a top electrically conductive surface is disposed facing the bottom electrically conductive surface. An electrical insulator separates the bottom electrically conductive surface from the top electrically conductive surface. At least one bare die electronic element is provided having a top conductive side and a bottom conductive side. Each bare die electronic element is disposed so that the top conductive side is in electrical communication with the top electrically conductive surface and so that the bottom conductive side is in electrical communication with the bottom electrically conductive surface.
    Type: Application
    Filed: May 26, 2009
    Publication date: April 8, 2010
    Inventors: John James Daniels, Gregory Victor Nelson
  • Patent number: 7692318
    Abstract: Better semiconductor encapsulation is achieved with a liquid epoxy resin composition comprising (A) a liquid epoxy resin, (B) a curing agent containing at least 5 wt % of an aromatic amine compound, (C) a microencapsulated catalyst containing a phenolic hydroxy-bearing benzoic acid derivative, and optionally, (D) an inorganic filler.
    Type: Grant
    Filed: March 23, 2006
    Date of Patent: April 6, 2010
    Assignee: Shin-Etsu Chemical Co., Ltd.
    Inventor: Hiroyuki Takenaka
  • Patent number: 7687320
    Abstract: A semiconductor device in which moisture penetration into the package interior is suppressed, comprising a rewiring layer formed by plating, with improved reliability of electrical characteristics. On the main surface of a semiconductor chip comprising circuit elements and formed on a wafer, a passivation film opposing the circuit elements is formed, so as to expose a first region of the main surface along the edges of the main surface. An insulating film, which extends over the main surface and along the side faces of this passivation film and onto the main surface of the semiconductor chip, is formed such that there remains a second region within the first region, along the edges of the main surface. A sealing layer covering the insulating film is then formed on the second region.
    Type: Grant
    Filed: August 29, 2006
    Date of Patent: March 30, 2010
    Assignee: Oki Semiconductor Co., Ltd.
    Inventor: Kenji Nagasaki
  • Patent number: 7687810
    Abstract: An etching step is performed on an LED/substrate wafer to etch through the LED epitaxial layers entirely around each LED on the substrate wafer to form a gap between each LED on the wafer. The substrate is not etched. When the LEDs/substrates are singulated, edges of each substrate extend beyond edges of the LED die. The LEDs are flip-chips and are mounted on a submount with the LED die between the submount and the substrate. An insulating underfill material is injected under the LED die and also covers the sides of the LED die and “enlarged” substrate. The substrate is then removed by laser lift-off. The raised walls of the underfill that were along the edges of the enlarged substrate are laterally spaced from the edges of the LED die so that a phosphor plate can be easily positioned on top to the LED die with a relaxed positioning tolerance.
    Type: Grant
    Filed: October 22, 2007
    Date of Patent: March 30, 2010
    Assignees: Philips Lumileds Lighting Company, LLC, Koninklijke Philip Electronics N.V.
    Inventors: Qingwei Mo, Arnold Daguio
  • Patent number: 7683482
    Abstract: A chip is bonded on a circuit board by aligning in position bumps with board electrodes with interposition of an anisotropic conductive layer between the chip and the circuit board. The anisotropic conductive layer is a mixture of an insulating resin, conductive particles and an inorganic filler. The chip is pressed against the board with a pressure force of not smaller than 20 gf per bump by virtue of a tool, while warp of the chip and the board is connected, the bumps are compressed, and the insulating resin is hardened.
    Type: Grant
    Filed: September 27, 2006
    Date of Patent: March 23, 2010
    Assignee: Panasonic Corporation
    Inventors: Kazuto Nishida, Hidenobu Nishikawa, Yoshinori Wada, Hiroyuki Otani
  • Patent number: 7683470
    Abstract: A Chip on Board (COB) package which can reduce the manufacturing costs by using a general PCB as a substrate, increase a heat radiation effect from a light source, thereby realizing a high quality light source at low costs, and a manufacturing method thereof. The COB package includes a board-like substrate with a circuit printed on a surface thereof, the substrate having a through hole. The package also includes a light source positioned in the through hole and including a submount and a dome structure made of resin, covering and fixing the light source to the substrate. The invention allows a good heat radiation effect by using the general PCB as the substrate, enabling manufacture of a high quality COB package at low costs. This in turn improves emission efficiency of the light source, ultimately realizing a high quality light source.
    Type: Grant
    Filed: February 22, 2007
    Date of Patent: March 23, 2010
    Assignee: Samsung Electro-Mechanics Co., Ltd.
    Inventors: Seon Goo Lee, Hun Joo Hahm, Dae Yeon Kim
  • Patent number: 7682879
    Abstract: A microelectronic device includes a die having an active surface and a non-active surface. To assemble the microelectronic device, the active surface of the die is placed on a substrate. A first material is dispensed between the active surface of the die and the substrate. A second material is dispensed on at least a portion of the non-active surface of the die. The second material is different than the first material and the first material and the second material are simultaneously cured.
    Type: Grant
    Filed: July 27, 2006
    Date of Patent: March 23, 2010
    Assignee: Seagate Technology LLC
    Inventors: Robert Michael Echols, Michael Richard Fabry
  • Patent number: 7683478
    Abstract: A sealed microelectronic structure which provides mechanical stress endurance and includes at least two chips being electrically connected to a semiconductor structure at a plurality of locations. Each chip includes a continuous bonding material along it's perimeter and at least one support column connected to each of the chips positioned within the perimeter of each chip. Each support column extends outwardly such that when the at least two chips are positioned over one another the support columns are in mating relation to each other. A seal between the at least two chips results from the overlapping relation of the chip to one another such that the bonding material and support columns are in mating relation to each other. Thus, the seal is formed when the at least two chips are mated together, and results in a bonded chip structure.
    Type: Grant
    Filed: February 6, 2008
    Date of Patent: March 23, 2010
    Assignee: International Business Machines Corporation
    Inventors: Kuan-Neng Chen, Bruce K. Furman, Edmund J. Sprogis, Anna W. Topol, Cornelia K. Tsang, Matthew R. Wordeman, Albert M. Young
  • Patent number: 7675185
    Abstract: An epoxy resin molding material for sealing which comprises an epoxy resin, an epoxy resin curing agent, and a pitch, as well as an electronic component comprising an element that is sealed with the molding material. This molding material exhibits favorable coloring properties, and even when used in packages with narrow distances between pads or wires, shorting defects caused by conductive materials can be prevented, as the molding material contains no conductive carbon black.
    Type: Grant
    Filed: December 6, 2004
    Date of Patent: March 9, 2010
    Assignee: Hitachi Chemical Co., Ltd.
    Inventors: Kazuyoshi Tendou, Mitsuo Katayose
  • Patent number: 7675182
    Abstract: A semiconductor package comprises a substrate; a semiconductor die that comprises a set of one or more interconnects on one side to couple to the substrate; and a shape memory alloy layer provided on another side of the semiconductor die to compensate warpage of the semiconductor die. The shape memory alloy layer deforms with warpage of the semiconductor die and changes from the deformed shape to an original shape to flatten the semiconductor die in response to rise of a temperature during coupling of the die to the substrate.
    Type: Grant
    Filed: September 27, 2007
    Date of Patent: March 9, 2010
    Assignee: Intel Corporation
    Inventors: Hai Xiao Sun, Daoqiang Lu
  • Publication number: 20100052133
    Abstract: A semiconductor device includes a plurality of semiconductor packages each with a semiconductor element and a flexible board. The flexible board is wider than the semiconductor element and is electrically connected to the semiconductor element. The plurality of semiconductor packages are stacked on one surface of a mother board. The semiconductor element is positioned between the flexible boards of the semiconductor packages in adjacent layers. The flexible boards in the adjacent layers are joined together at junction portions positioned at a part of the flexible boards which sticks out from an area in which the semiconductor elements and the flexible boards overlap. A reinforcing resin is provided in at least a part of the area between the flexible boards in the adjacent layers and between the junction portion of the flexible boards and the corresponding semiconductor element. The reinforcing resin contacts at least a part of the adjacent flexible board.
    Type: Application
    Filed: July 1, 2009
    Publication date: March 4, 2010
    Applicant: Elpida Memory, Inc.
    Inventors: Hisashi TANIE, Hiroshi Moriya, Masahiro Yamaguchi, Emi Sawayama
  • Publication number: 20100044888
    Abstract: A bis(aminophenol) derivative having substituents at positions adjacent to two amino groups is provided. The bis(aminophenol) derivative is used as a raw material of a polyamide resin for a positive-tone photosensitive resin composition. A polyamide resin comprising bis(aminophenol) and a structure derived from a carboxylic acid is also provided, the bis(aminophenol) having substituents at positions adjacent to the two amino groups. A positive-tone photosensitive resin composition comprising a polybenzooxazole precursor resin, exhibiting high sensitivity and a high cyclization rate even when cured at a low temperature is provided. Also provided is a positive-tone photosensitive resin composition comprising a polyamide resin having an imide structure, an imide precursor structure, or an amide acid ester structure. The composition exhibits high sensitivity and produces a cured product having low water absorption even when cured at a low temperature.
    Type: Application
    Filed: October 23, 2007
    Publication date: February 25, 2010
    Applicant: SUMITOMO BAKELITE COMPANY LIMITED
    Inventor: Koji Terakawa
  • Patent number: 7667339
    Abstract: An epoxy resin composition for semiconductor encapsulation includes at least one epoxy resin, at least one curing agent, at least one filler, and at least one first curing accelerator, the first curing accelerator having a tetracyanoethylene, a 7,7,8,8-tetracyanoquinodimethane, a compound having the chemical structure of Formula 1, or a mixture thereof, wherein each of R1 through R7, independently, represents a hydrogen atom or a C1-C12 hydrocarbon group, provided that when R1 through R7 are C1-C12 hydrocarbon groups, R1 and R2, R2 and R3, R3 and R4, R4 and R5, R5 and R6, and R6 and R7 can be joined to each other to form a cyclic structure.
    Type: Grant
    Filed: December 29, 2006
    Date of Patent: February 23, 2010
    Assignee: Cheil Industries, Inc.
    Inventors: Eun Jung Lee, Yoon Kok Park, Young Kyun Lee, Whan Gun Kim, Suk Ku Chang
  • Patent number: 7663155
    Abstract: A luminescent diode chip for flip-chip mounting on a carrier, having a conductive substrate (12), a semiconductor body (14) that contains a photon-emitting active zone and that is joined by an underside to the substrate (12), and a contact (18), disposed on a top side of the semiconductor body (14), for making an electrically conductive connection with the carrier (30) upon the flip-chip mounting of the chip, whereby either the carrier is solder covered or a layer of solder is applied to the contact. An insulating means (40, 42, 44, 46, 48) is provided on the chip, for electrically insulating free faces of the semiconductor body (14) and free surfaces of the substrate (12) from the solder.
    Type: Grant
    Filed: July 18, 2005
    Date of Patent: February 16, 2010
    Assignee: Osram Opto Semiconductors GmbH
    Inventors: Volker Harle, Dominik Eisert
  • Patent number: 7659475
    Abstract: The present invention provides a method for dielectric passivating the surface of a solar cell by accumulation of negative fixed charges of a first type at the interface between semiconductor material and a passivating material. According to the invention the passivating material comprises an oxide system, for example a binary oxide system, comprising Al2O3 and at least one metal oxide or metalloid oxide which enhances the tetrahedral structure of Al2O3, for example, an (Al2O3)x(TiO2)1-x alloy. In this way it is possible to combine the desirable properties from at least two different oxides, while eliminating the undesirable properties of each individual material. The oxide system can be deposited onto the semiconductor surface by means of a sol-gel method, comprising the steps of formation of the metal oxide and/or metalloid oxide sol and the aluminum solution and then carefully mixing these together under stirring and ultrasonic treatment.
    Type: Grant
    Filed: June 17, 2004
    Date of Patent: February 9, 2010
    Assignee: IMEC
    Inventors: Guido Agostinelli, Jozef Szlufcik, Petko Vitanov, Antoaneta Harizanova
  • Patent number: 7652385
    Abstract: Aiming at providing a semiconductor device advanced in performance of transistors, and improved in reliability, a semiconductor device of the present invention has a semiconductor element, a frame component provided over the semiconductor element, while forming a cavity therein, and a molding resin layer covering around the frame component, wherein the frame component is composed of a plurality of resin films (a first resin film and a second resin film) containing the same resin, and the cavity allows the active region of the semiconductor element to expose therein.
    Type: Grant
    Filed: July 28, 2008
    Date of Patent: January 26, 2010
    Assignee: NEC Electronics Corporation
    Inventor: Kazunori Kuramoto
  • Patent number: 7652214
    Abstract: In an electronic component package in which an electronic component mounted on a mounting substrate via external electrodes placed on the mounting substrate is covered by a mold resin, the electronic component has a component cover which covers elements placed on the lower face of a component substrate, and which forms cavities, and a protective member which is lower in elastic modulus than the mold resin is disposed in a portion which excludes portions joined with the external electrodes in a lower face of the component cover, and which is opposed to the cavities.
    Type: Grant
    Filed: October 30, 2006
    Date of Patent: January 26, 2010
    Assignee: Panasonic Corporation
    Inventors: Atsushi Takano, Mitsuhiro Furukawa, Ryouichi Takayama
  • Publication number: 20100007007
    Abstract: A semiconductor package includes: a semiconductor chip having a first surface, and a second surface that is opposite to the first surface and allows a semiconductor device to be formed thereon; bonding pads disposed on the second surface of the semiconductor chip; and a metal ion barrier layer disposed on the first surface of the semiconductor chip, and preventing metal ions from penetrating into the semiconductor chip through the first surface of the semiconductor chip. Accordingly, the semiconductor package can obtain a superior semiconductor device by minimizing moisture absorption and effectively blocking the penetration of metal ions.
    Type: Application
    Filed: July 2, 2009
    Publication date: January 14, 2010
    Applicant: Samsung Electronics Co., Ltd
    Inventors: Sung-hwan YOON, Jai-kyeong Shin, Yong-nam Koh, Hyoung-suk Kim, In-ku Kang, Ho-jin Lee, Sang-wook Park, Joong-kyo Kook, Min-young Son, Soong-yong Hur
  • Publication number: 20100001415
    Abstract: A liquid epoxy resin composition comprising (A) a liquid epoxy resin; (B) an amine curing agent; (C) a nitrogen compound selected from the group consisting of organic acids salts of tertiary amines, amino acids, imino acids, and monoamine compounds having an alcoholic hydroxyl group in an amount of from 0.1 to 20 parts by weight per total 100 parts by weight of the components (A) and (B); and (D) an inorganic filler in an amount of from 50 to 900 parts by weight per 100 parts by weight of the component (A).
    Type: Application
    Filed: July 31, 2009
    Publication date: January 7, 2010
    Inventors: Masatoshi Asano, Kaoru Katoh, Kazuaki Sumita
  • Patent number: 7642661
    Abstract: A liquid epoxy resin composition comprising: (A) a liquid epoxy resin; (B) an amine type curing agent; (C) a sulfur-containing phenol compound in an amount of from 1 to 20 parts by weight per total 100 parts by weight of the components (A) and (B); and (D) an inorganic filler in an amount of from 50 to 900 parts by weight per 100 parts by weight of the component (A).
    Type: Grant
    Filed: November 20, 2006
    Date of Patent: January 5, 2010
    Assignee: Shin-Etsu Chemical Co., Ltd.
    Inventors: Masatoshi Asano, Kaoru Katoh, Kazuaki Sumita
  • Publication number: 20090283922
    Abstract: In some embodiments an etchstop layer is deposited over a transistor that has been encapsulated by a high-K film, a silicon nitride is deposited over the deposited etchstop layer, the silicon nitride is removed, and the etchstop layer is removed. Other embodiments are described and claimed.
    Type: Application
    Filed: December 27, 2007
    Publication date: November 19, 2009
    Inventors: Willy Rachmady, Justin S. Sandford, Oleg Golonzka
  • Patent number: 7612458
    Abstract: There is provided an epoxy resin composition for semiconductor encapsulating use comprising: an epoxy resin (A); a phenol resin (B); a curing accelerator (C); and an inorganic filler (D), wherein the inorganic filler (D) contains a spherical fused silica (d1) which contains: metal or semimetal other than silicon; and/or an inorganic compound comprising the metal or semimetal other than silicon.
    Type: Grant
    Filed: January 12, 2006
    Date of Patent: November 3, 2009
    Assignee: Sumitomo Bakelite Company Limited
    Inventor: Atsushi Nakamura
  • Publication number: 20090230539
    Abstract: In recent years, as electronic equipment becomes thinner, an area for mounting a semiconductor device used in the electronic equipment is required to be smaller, and a thickness of an encapsulating resin for encapsulating a semiconductor substrate having a circuit formed thereon and the like also becomes smaller. The encapsulating resin is marked with a product number, a manufacturer name, or the like. There arises a problem in that, in the marking, an infrared laser beam applied to the encapsulating resin passes through the encapsulating resin, generates heat in the semiconductor substrate, and destructs the formed circuit. By providing a thin film for refracting the infrared laser beam on a rear surface of the semiconductor substrate, the optical path of the infrared laser beam is made longer to reduce heat generated in the semiconductor substrate.
    Type: Application
    Filed: February 12, 2009
    Publication date: September 17, 2009
    Applicant: NEC ELECTRONICS CORPORATION
    Inventor: TOMOHIRO KAMIMURA
  • Patent number: 7579698
    Abstract: A semiconductor photodetector which can achieve spectral sensitivity characteristics close to relative luminous characteristics at low cost while using a light receiving element of a semiconductor made from such as silicon, has a semiconductor light receiving element having high spectral sensitivity in a wavelength range between approximately 400 nm to 1100 nm and an optical transmitting resin for sealing at least a light receiving surface of the semiconductor light receiving element. The optical transmitting resin is formed by dispersing metal boride micro particles whose particle diameter is not more than approximately 100 nm in a transparent resin and blocks light in wavelengths approximately 700 nm or above.
    Type: Grant
    Filed: January 17, 2006
    Date of Patent: August 25, 2009
    Assignee: New Japan Radio Co., Ltd.
    Inventors: Fumio Takamura, Seiji Koike
  • Patent number: 7560820
    Abstract: A technique for controlling an atmosphere within an enclosure involves providing a getter within the atmosphere of the enclosure. An LED manufactured according to the technique may include a getter within an enclosed volume of the LED device.
    Type: Grant
    Filed: April 12, 2005
    Date of Patent: July 14, 2009
    Assignee: SAES Getters S.p.A.
    Inventors: Marco Amiotti, Ronald O. Petersen
  • Patent number: 7560821
    Abstract: An area mount type semiconductor device having high reliability when a semiconductor element is mounted on a surface with the use of a lead-free solder, and a die bonding resin composition and encapsulating resin composition used for the area mount type semiconductor device attainable by an area mount type semiconductor device mounting a semiconductor element or a stacked element comprising a substrate, and a semiconductor element mounted on a surface of the substrate via a die bonding resin composition, and substantially having only the surface of the substrate mounting the semiconductor element encapsulated with the use of an encapsulating resin composition, wherein an elastic modulus of a cured product of the die bonding resin composition at 260° C. is 1 MPa to 120 MPa, an elastic modulus of a cured product of the encapsulating resin composition at 260° C. is 400 MPa to 1,200 MPa, and a thermal expansion coefficient of the cured product of the encapsulating resin composition at 260° C. is 20 ppm to 50 ppm.
    Type: Grant
    Filed: March 22, 2006
    Date of Patent: July 14, 2009
    Assignee: Sumitomo Bakelite Company, Ltd
    Inventors: Hironori Osuga, Takashi Yagisawa, Hiroyuki Yasuda
  • Patent number: 7550859
    Abstract: A method for hermetically sealing a package includes applying a light or energy active resist to a fill port to act as a temporary hermetic seal, patterning the resist, and applying a solder to the fill port, wherein the solder is configured to serve as a hermetic seal.
    Type: Grant
    Filed: August 21, 2007
    Date of Patent: June 23, 2009
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: Don Michael, Mari J. Rossman
  • Patent number: 7547978
    Abstract: Polymerized materials for forming the underfill and encapsulation structures for semiconductor package are disclosed. A filler constituent, such as boron nitride, silicates, elemental metals, or alloys, may be added to a liquid photopolymer resin to tailor the physical properties thereof upon curing. The filler constituents may be employed to alter the coefficient of thermal expansion, thermal conductivity, or electrical conductivity of the polymerized material. A number of different embodiments are disclosed that employ the above materials in selected regions of the underfill and encapsulation structures of the semiconductor package. The polymerized materials may also be used to form support structures and covers for optically interactive semiconductor devices. Methods for forming the above structures using stereolithography are also disclosed.
    Type: Grant
    Filed: June 14, 2004
    Date of Patent: June 16, 2009
    Assignee: Micron Technology, Inc.
    Inventors: David R. Hembree, Warren M. Farnworth
  • Patent number: 7530164
    Abstract: A method for connecting electronic components, such as, an integrated circuit die and a package substrate, is described. According to one aspect of the invention, a contact pad protective material is applied on one or more of the contact pads on an integrated circuit die. The underfill material is applied to the surface of the die not covered by the contact pad protective material and the underfill material is partially cured in a curing oven. The contact pad material is removed leaving openings over the respective surface of the contact pad. A one or more contacts on a package substrate is inserted into the openings, electronically connecting the contacts to the contact pads.
    Type: Grant
    Filed: January 27, 2006
    Date of Patent: May 12, 2009
    Assignee: Intel Corporation
    Inventors: Paul Koning, Terry Sterrett
  • Patent number: 7528415
    Abstract: A semiconductor laser improved in heat sinkability of portions in the vicinity of a light-emitting end face of a main body in order to prevent occurrence of COD is provided. A main body 150 having a light-emitting end face 150a for emitting laser light is formed on a semiconductor substrate, n-type GaAs substrate. Thickness of a front end portion 112a in the vicinity of the light-emitting end face 150a of a plated metal layer 112 formed on the main body 150 is larger than thickness of a central portion 112b of the plated metal layer 112 in a direction along a cavity.
    Type: Grant
    Filed: April 20, 2006
    Date of Patent: May 5, 2009
    Assignee: Sharp Kabushiki Kaisha
    Inventor: Fumie Kunimasa
  • Patent number: 7517726
    Abstract: In one embodiment the present invention includes a method of manufacturing a chip scale package. Embodiments of the present invention include sawing kerfs between semiconductor device boundaries on opposite sides of the wafer and filling the kerfs with mold compound. The devices may then be sawed into individual packaged devices encapsulated in mold compound. In one embodiment, kerfs on opposite sides of the wafer have different widths to create a step in the wafer boundary with the mold compound, which improves the integrity of the package. In one embodiment, a device and one or more neighboring devices are bonded together using bond wires to form a group of device that are encapsulated in mold compound.
    Type: Grant
    Filed: April 25, 2008
    Date of Patent: April 14, 2009
    Assignee: Shanghai KaiHong Technology Co., Ltd
    Inventors: Xiaochun Tan, Jun Guo
  • Patent number: 7514769
    Abstract: A micro surface mount die package is described that includes a die attach pad having a plurality of integrally formed risers. A bumped die is mounted on the die attach pad such that the risers are located to the side of the die and the contact bumps face away from the die attach pad. An encapsulant covers the active and side surfaces of the die while leaving the contact bumps exposed on the packaged semiconductor device. Methods for forming such packages and panels suitable for use in forming such packages are also described.
    Type: Grant
    Filed: August 13, 2005
    Date of Patent: April 7, 2009
    Assignee: National Semiconductor Corporation
    Inventor: Shahram Mostafazadeh