With Specified Filler Material Patents (Class 257/789)
  • Patent number: 6020648
    Abstract: A process for packaging a die uses compressible microspheres to form a stress buffer layer between the die and an epoxy encapsulant to absorb stresses on the die caused by the different thermal expansion rates of the epoxy and die during temperature changes. By using a compressible layer of microspheres or other material, the need for a nitride passivation or other insulating layer to protect the die from thermally-induced stress is eliminated. In addition, the number and size of the microspheres and the amount of epoxy used to seal the package can be adjusted so that the epoxy is approximately co-planar with the top of the package to allow the package to be handled and used with standard equipment and processes.
    Type: Grant
    Filed: December 15, 1998
    Date of Patent: February 1, 2000
    Assignee: Clear Logic, Inc.
    Inventor: John MacPherson
  • Patent number: 5998877
    Abstract: A semiconductor device packaged in a plastic package wherein the thickness of the plastic mold on the top surface of the semiconductor device chip is less than the height of the lead on the top surface of the semiconductor device chip and the top surface to the plastic mold filling the space between the leads is convex downward in an arc shape, and a metal mold employable for producing the semiconductor device packaged in a plastic package comprising a lower mold having a cavity in which a semiconductor device chip provided with a plurality of leads thereon, is placed during a molding process, and an upper mold having a lower surface having a plurality of longitudinal projections and recesses arranged in parallel to one anther, the cross section of the longitudinal projections and recesses produced along the lower surface of the upper mold being effective to cause longitudinal linear contact along the longitudinal projections and recesses, between the lower surface and the edges of the leads, during a molding
    Type: Grant
    Filed: August 22, 1997
    Date of Patent: December 7, 1999
    Assignee: Oki Electric Industry Co., Ltd.
    Inventor: Shinji Ohuchi
  • Patent number: 5998867
    Abstract: A shielding apparatus for an electronic component includes a first insulative encapsulant surrounding at least a portion of the component and a second encapsulant surrounding said first encapsulant and having conductive particles dispersed therein for absorbing ionizing radiation.
    Type: Grant
    Filed: February 23, 1996
    Date of Patent: December 7, 1999
    Assignee: Honeywell Inc.
    Inventors: Ronald J. Jensen, Richard K. Spielberger, Toan Dinh Nguyen, William F. Jacobsen
  • Patent number: 5994785
    Abstract: In an epoxy resin composition comprising an epoxy resin, a curing agent, and at least 70% by weight of an inorganic filler, at least one of the epoxy resin and the curing agent has such a molecular weight distribution as to provide an average dispersity Mw/Mn of less than 1.6, a two-nucleus compound content of less than 8% by weight and a seven- and more-nucleus compound content of less than 32% by weight. When the composition is cured at 180.degree. C. for 90 seconds into a primary product having Tg1 and the primary product postcured at 180.degree. C. for 5 hours into a secondary product having Tg2, the relationship: (Tg2-Tg1)/Tg2<0.1 is satisfied. The composition is fast-curing and effectively moldable and cures into a reliable product without a need for postcure.
    Type: Grant
    Filed: May 6, 1999
    Date of Patent: November 30, 1999
    Assignees: Mitsubishi Denki Kabushiki Kaisha, Shin-Etsu Chemical Co., Ltd.
    Inventors: Noriaki Higuchi, Koji Futatsumori, Chiat Hooi Keow, Hui Teng Teoh, Toshio Shiobara
  • Patent number: 5982631
    Abstract: A method and encapsulation material for encapsulating the solder joints of an IC device mounted on the substrate of an electronic circuit assembly. The encapsulation material is formulated to be sufficiently opaque to x-radiation to enable the use of x-radiation imaging techniques to detect air pockets and voids in the encapsulation material that might degrade the fatigue life properties of the solder joints encapsulated by the encapsulation material. For the purpose of enhancing the fatigue life properties of the solder joints, the encapsulation material contains a filler material dispersed in a polymeric material, such as an epoxy, such that the encapsulation material is characterized by a coefficient of thermal expansion approximately equal to that of the solder joints. The filler material contains a sufficient amount of an element to render the encapsulation material opaque to x-radiation.
    Type: Grant
    Filed: January 25, 1999
    Date of Patent: November 9, 1999
    Assignee: Delco Electronics Corp.
    Inventors: Philip Harbaugh Bowles, Michael Livingston Shipman
  • Patent number: 5981313
    Abstract: The packaging structure for a semiconductor device according to this invention is formed by mounting a semiconductor chip 1 on a wiring board 4 to connect it to the electrodes 5 of the wiring board 4, and filling a sealing resin 7, obtained by mixing a filler material 8 for lowering the coefficient of thermal expansion in a base resin, in the gap formed between the semiconductor device and the wiring board. The sealing resin 7 is separated to a first part 9 with small amount of the filler material and is composed mostly of the base resin, and a second part 10 with an amount of the filler material more than in the first part. With this constitution, the second part is consists of a material with smaller coefficient of thermal expansion than that of the first part. The first part and the second part are separated after completion of the filling of the sealing resin 7.
    Type: Grant
    Filed: October 2, 1997
    Date of Patent: November 9, 1999
    Assignee: NEC Corporation
    Inventor: Kei Tanaka
  • Patent number: 5969414
    Abstract: There is provided a leadframe assembly for encapsulation in a polymer resin which prevents post-assembly fracture or swelling of the resin. The leadframe is coated with an adhesion enhancing layer that increases the shear stress required for delamination to in excess of about 3.4 MPa. In combination with this adhesion enhancing layer is a compliant die attach adhesive bonding an integrated circuit device to a central die attach paddle. This compliant die attach adhesive has a compliancy factor, E.multidot.a of less than 1.5 MPa/.degree.C. and a thickness of from about 0.01 mm to about 0.08 mm.
    Type: Grant
    Filed: May 25, 1994
    Date of Patent: October 19, 1999
    Assignee: Advanced Technology Interconnect Incorporated
    Inventors: Arvind Parthasarathi, Deepak Mahulikar
  • Patent number: 5965947
    Abstract: In a semiconductor package which includes a plurality of semiconductor chips of different kinds, some of the chips are bonded to die bonding pad by means of a conductive adhesive, while the other chips are bonded by means of a non-conductive adhesive that contains highly insulating beads. Encapsulation of the package is by a molding compound. A nitride film or an organic insulating film is disposed on a back side of the chips bonded by the non-conductive adhesive to improve the withstand voltage between these chips and the die pad.
    Type: Grant
    Filed: August 19, 1997
    Date of Patent: October 12, 1999
    Assignee: SamSung Electronics Co., Ltd.
    Inventors: Shi-baek Nam, Seung-kon Mok, Dae-hoon Kwon
  • Patent number: 5959316
    Abstract: A semiconductor device has a light-emitting diode covered by a transparent spacer which separates the LED from a uniformly thick fluorescent material containing layer such that there is a more uniform lighting of the fluorescent material containing layer to provide a uniform white light.
    Type: Grant
    Filed: September 1, 1998
    Date of Patent: September 28, 1999
    Assignee: Hewlett-Packard Company
    Inventor: Christopher Haydn Lowery
  • Patent number: 5949142
    Abstract: A chip size package is constituted by a chip on which an integrated circuit is formed, and plated bumps are formed at terminal portions of the integrated circuit, a flexible two-layered printed-circuit board having interlevel conductive bumps for electrically connecting metal patterns formed on the two surfaces of the flexible board, and an anisotropic conductive film for electrically connecting the plated bumps arranged on the chip to the flexible two-layered printed-circuit board, and fixing the chip onto the flexible two-layered printed-circuit board. With these features, the chip size package is excellent in mass production without any sealing by potting and any setting/removing on/from a convey jig and the like for every product.
    Type: Grant
    Filed: March 26, 1998
    Date of Patent: September 7, 1999
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Masashi Otsuka
  • Patent number: 5945722
    Abstract: A color active pixel sensor cell is formed by utilizing four photodiodes which are each covered with a layer of oxide. The thicknesses of the layers of oxide are set so that a first layer of oxide prohibits red light from entering the first photodiode, a second layer of oxide prohibits green light from entering the second photodiode, a third layer of oxide prohibits blue light from entering the third photodiode, and a fourth layer of oxide allows visible light to enter the fourth photodiode. The amount of red light received by the cell is then determined by subtracting the light energy collected by the first photodiode from the light energy collected by the fourth photodiode. Similarly, the amount of green and blue light received by the cell is determined by subtracting the light energy collected by the second and third photodiodes, respectively, from the amount of light energy collected by the fourth photodiode.
    Type: Grant
    Filed: May 2, 1997
    Date of Patent: August 31, 1999
    Assignee: National Semiconductor Corporation
    Inventors: Gu-Fung David Tsuei, Min-Hwa Chi
  • Patent number: 5939792
    Abstract: A resin-mold type semiconductor device includes a semiconductor chip, a die pad for supporting and fixing the semiconductor chip, a plurality of inner leads whose distal ends face the semiconductor chip, a plurality of outer leads integrally connected to the corresponding inner leads, bonding wires for electrically connecting distal end portions of the inner leads to terminal electrodes of the semiconductor chip, a resin-mold package for molding the die pad, the semiconductor chip, the inner leads and the bonding wires, and a highly water-absorbent insulating film made of highly water-absorbent polymer formed at least one portion of the surface of the resin-mold package.
    Type: Grant
    Filed: October 8, 1997
    Date of Patent: August 17, 1999
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Toshimitsu Ishikawa
  • Patent number: 5929522
    Abstract: A semiconductor device package includes a carrier substrate molded of a non-laminate material. A plurality of conductive metal balls are molded within the non-laminate carrier substrate to provide an electrical connection between opposite sides of the substrate. The conductive metal balls provide conductive columns through the substrate for electrically connecting a chip mounted on one side of the substrate to solder balls on an opposite side of the substrate for mounting the package on a printed circuit board. The conductive columns eliminate the need for via holes which are used in known packages. The package with conductive columns provides a more compact, more precise, and lower cost package which is less susceptible to moisture damage than the known packages employing via holes.
    Type: Grant
    Filed: April 17, 1998
    Date of Patent: July 27, 1999
    Assignee: Hestia Technologies, Inc.
    Inventor: Patrick O. Weber
  • Patent number: 5907189
    Abstract: One aspect of the invention relates to a method for providing a semiconductor package with a thermally conductive coating, the semiconductor package including a package substrate having a plurality of electrically conductive traces formed thereon, an upper surface and a lower surface, the lower surface having a plurality of contacts for providing electrical connection between the conductive traces formed on the package substrate and a plurality of conductive traces formed on a printed circuit board, and a semiconductor die mounted to the upper surface to the package substrate, the semiconductor die having a plurality of bond pads formed thereon which are electrically connected to the conductive traces formed on the package substrate. In one embodiment, the method includes the steps of depositing a coating on the upper surface of the package substrate and the coating includes a diamond film or diamond particles.
    Type: Grant
    Filed: May 29, 1997
    Date of Patent: May 25, 1999
    Assignee: LSI Logic Corporation
    Inventor: Atila Mertol
  • Patent number: 5907190
    Abstract: A semiconductor device in which the surface of the semiconductor element is coated with a cured silicone in which there is dispersed filler having an average particle diameter of 0.01 to 500 micrometers and a specific gravity of 0.01 to 0.95 characterized in that the concentration of said filler is higher in the layer of said cured material remote from the element than in the layer of said cured material adjoining the element. The method for fabricating such a device comprises coating the surface of a semiconductor element with a curable silicone composition in which there is dispersed a filler having an average particle diameter of 0.01 to 500 micrometers and a specific gravity of 0.01 to 0.95 and thereafter curing said composition after the elapse of sufficient time for the filler in the layer of the composition adjoining the element to migrate into the layer of said composition remote from the element.
    Type: Grant
    Filed: November 21, 1995
    Date of Patent: May 25, 1999
    Assignee: Dow Corning Toray Silicone Co., Ltd.
    Inventors: Takae Ishikawa, Katsutoshi Mine, Hiroyosi Naito, Kimio Yamakawa
  • Patent number: 5886415
    Abstract: An anisotropic conductive sheet material includes a resin and conductive fillers, such as metallic particles, added in the resin. A conductive layer is formed on one of the surfaces of the anisotropic conductive sheet material. A circuit board includes a substrate having first and second surfaces and a circuit pattern being formed on the first surface of the substrate, an anisotropic conductive sheet having first and second surfaces, a circuit pattern being formed on the first surface thereof. The second surface of the anisotropic conductive sheet is adhered to the first surface of the substrate in such a manner that the circuit patterns are electrically connected to each other by means of the anisotropic conductive sheet. An electrically insulative layer formed on the first surface of the anisotropic conductive sheet to cover the circuit pattern thereof, except that external connecting portions thereof are exposed.
    Type: Grant
    Filed: January 17, 1997
    Date of Patent: March 23, 1999
    Assignee: Shinko Electric Industries, Co., Ltd.
    Inventor: Masatoshi Akagawa
  • Patent number: 5883419
    Abstract: A transistor in accordance with the invention comprises an ultra-thin Mo--C film functioning as a channel for an electron flow with two ends of the thin metal film functioning as source and drain terminals of the transistor, respectively; a piezoelectric film formed on the Mo--C film, for producing a force in accordance with an applied electric field provided by a gate voltage; and an electrode film formed on the piezoelectric film functioning as a gate of the transistor to which the gate voltage is applied to produce the applied electric field; and wherein a resistance of the Mo--C film between the source and drain terminals changes in accordance with the force produced in response to the applied gate voltage. This transistor can be used as an element of the three dimensional integrated circuit with a laminated structure.
    Type: Grant
    Filed: May 1, 1997
    Date of Patent: March 16, 1999
    Assignee: Electronics and Telecommunications Research Institute
    Inventors: Seong-Jae Lee, Kyoung-Wan Park, Min-Cheol Shin
  • Patent number: 5880530
    Abstract: An apparatus and method for forming solder interconnection structures that reduce thermo-mechanical stresses at the solder joints of a semiconductor device and its supporting substrate. In one embodiment, the solder interconnection structure of the present invention comprises a semiconductor device and a substrate having a plurality of solder connections extending from the substrate to electrodes or bond pads on the semiconductor device. A multilayer structure is disposed between the semiconductor device and substrate filling the gap formed by the solder connections. The multilayer structure includes a first layer and a second layer, each having a different coefficient of thermal expansion. Thus, in accordance with the present invention, the stress concentration points are moved away from the solder joints of the semiconductor device and substrate to a point located between the first and second layers of the filler structure.
    Type: Grant
    Filed: March 29, 1996
    Date of Patent: March 9, 1999
    Assignee: Intel Corporation
    Inventors: Yohko Mashimoto, Shuji Inoue, Jiro Kubota, Mashahiro Kuroda
  • Patent number: 5874784
    Abstract: A semiconductor device includes an interconnection plate, a semiconductor chip having electrodes formed on one surface thereof and bonded to the interconnection plate with the other surface thereof, wires respectively connecting the electrodes of the semiconductor chip and the internal connection regions of the interconnection plate, and a resin sealer sealing therein the semiconductor chip and the wires on the interconnection plate, wherein the internal connection regions are provided in a peripheral area of the interconnection plate surrounding the semiconductor chip, and major portions of the interconnection patterns and the external connection terminals are provided in an area inward from the internal connection regions under the semiconductor chip.
    Type: Grant
    Filed: June 17, 1996
    Date of Patent: February 23, 1999
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Kazumasa Aoki, Yoshiki Sota
  • Patent number: 5866953
    Abstract: An apparatus and a method for providing a heat sink on an upper surface of a semiconductor chip by placing a heat-dissipating material thereon which forms a portion of a glob top. The apparatus comprises a semiconductor chip attached to and in electrical communication with a substrate. A barrier glob top material is applied to the edges of the semiconductor chip on the surface ("opposing surface") opposite the surface attached to the substrate to form a wall around a periphery of an opposing surface of the semiconductor chip wherein the barrier glob top material also extends to contact and adhere to the substrate. The wall around the periphery of the opposing surface of the semiconductor chip forms a recess. A heat-dissipating glob top material is disposed within the recess to contact the opposing surface for the semiconductor chip.
    Type: Grant
    Filed: May 24, 1996
    Date of Patent: February 2, 1999
    Assignee: Micron Technology, Inc.
    Inventors: Salman Akram, James M. Wark
  • Patent number: 5847467
    Abstract: A device or die is presented which uses laser deposited leads, with a filler to bridge the gap between the die and the lead frame. The filler may be oxide, poly amide, a combination of oxide layers and poly amide layers, plastic or a plastic which has plastic coated beads of metal. The die and lead frame are placed on a heat spreader. Leads are formed over the filler material from bond pads on the lead frame to bond pads on the die. Various protective materials are placed over the die to protect it from the package. Over the protective material is another heat spreader or other device that is required to make the die function better. Typical devices are batteries, capacitors, or other die. Finally, the structure is encapsulated in a package of non-conductive material. This structure is more stable than presently available structures because the active element, the die, is not in direct contact with the plastic package.
    Type: Grant
    Filed: July 27, 1993
    Date of Patent: December 8, 1998
    Assignee: Texas Instruments Incorporated
    Inventors: Kendall Scott Wills, Paul Anthony Rodriguez
  • Patent number: 5844309
    Abstract: An adhesive composition including: a main component comprising a resin material, a solvent for dissolving said main component, and a filler added to said main component, wherein said filler has a particle size so as to make a concavo-convex depth of a surface of said adhesive composition equal to or less than 15 .mu.m after said adhesive composition is applied to an adherend and dried in order to evaporate said solvent before a thermocompression process. The present invention also discloses a semiconductor device using the adhesive composition, an adhering method using the adhesive composition and a method for producing a semiconductor device using the adhesive composition.
    Type: Grant
    Filed: December 3, 1996
    Date of Patent: December 1, 1998
    Assignee: Fujitsu Limited
    Inventors: Yukio Takigawa, Shigeaki Yagi, Toshimi Kawahara, Mitsunada Osawa, Hiroyuki Ishiguro, Shinya Nakaseko, Takashi Hozumi, Masaaki Seki
  • Patent number: 5834850
    Abstract: A metal foil material for covering a semiconductor device, a semiconductor device covered with the metal foil material, and a process for producing the metal foil-covered semiconductor device are disclosed. The metal foil material is one which is, in molding a resin for encapsulating a semiconductor element using a mold, temporarily fixed on a surface of a cavity of the mold, and is adhered on a surface of a semiconductor device by injecting the encapsulating resin into the mold and molding the resin, wherein a contact angle of the face of the metal foil material which is in contact with the encapsulating resin during molding, to water is 110.degree. or less.
    Type: Grant
    Filed: August 26, 1996
    Date of Patent: November 10, 1998
    Assignee: Nitto Denko Corporation
    Inventors: Yuji Hotta, Hitomi Shigyo, Shinichi Ohizumi, Seiji Kondoh
  • Patent number: 5789813
    Abstract: An integrated circuit package having a die supported on a ball grid array substrate and wire bonds electrically connecting the die to the substrate. Supported on the substrate is a lock ring having a threaded opening encircling the die. Encapsulant covers the die and the wire bonds and adheres the lock ring to the substrate. A heat sink having a threaded portion can be threaded into the lock ring into an operative cooling position relative to the die and subsequently to an unthreaded removed position. When in the latter position, a repair station can be positioned over the package and the solder balls are accessible for hot gas melting thereof for removal (or replacement) of the package from the underlying motherboard.
    Type: Grant
    Filed: September 30, 1996
    Date of Patent: August 4, 1998
    Assignee: LSI Logic Corporation
    Inventors: Janet Kirkland, Mark R. Schneider
  • Patent number: 5770867
    Abstract: A photocoupler device includes a light-emitting chip, a light-receiving chip, a light-emitting side lead frame for individually holding the light emitting chip and a light-receiving side lead frame for individually holding the light-receiving chip. The light-emitting and light-receiving chips are opposed to each other so as to be optically coupled and covered with a light-transmissive resin as a first molding layer, in the whole part except in the outside connecting terminal portions of the two lead frames. The first molding layer is further covered with an opaque resin as a second molding layer. In such a photocoupler device, the light-transmissive resin is made to contain fillers in an amount of 80% by weight or more and directly cover the light-emitting chip, without needing silicone-resin coating for protecting the light-emitting chip.
    Type: Grant
    Filed: January 16, 1996
    Date of Patent: June 23, 1998
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Naoki Sata, Kazuo Kusuda
  • Patent number: 5709960
    Abstract: An electronic component has a body (11) that is formed from a mold compound that includes a thermoplastic material (31), a first filler (32) comprised of an electrically insulative material wherein the first filler (32) is more thermally conductive than the thermoplastic material (31), and a second filler (33) comprised of an electrically conductive material wherein the second filler (33) is more thermally conductive than the thermoplastic material (31).
    Type: Grant
    Filed: June 21, 1996
    Date of Patent: January 20, 1998
    Assignee: Motorola, Inc.
    Inventors: Lonne L. Mays, Mark D. Mosher, Alexandra Hubenko
  • Patent number: 5698904
    Abstract: A packaging material for electronic components is provided which inhibits the cracking of a passivation film on an encapsulated chip and inhibits the breaking of an interconnecting metallization pattern in a chip of an electronic component and meets the miniaturization trend for electronic components. The packaging material includes: a resin, and 80% to 93% by weight, relative to the total amount of the packaging material, of a filler made up of particles having an average particle size of 30 .mu.m or less, at least 90% by weight of which are spherically shaped or have rounded ends and/or edges.
    Type: Grant
    Filed: January 13, 1997
    Date of Patent: December 16, 1997
    Assignee: Rohm Co., Ltd.
    Inventor: Masahiro Tsuji
  • Patent number: 5688575
    Abstract: This invention relates to metal-containing inserts, such as transformers, that are encapsulated, via compression molding processes, with at least one wet lay thermoplastic sheet material and that do not experience significant visible cracking during heat cycling.
    Type: Grant
    Filed: October 21, 1996
    Date of Patent: November 18, 1997
    Assignee: E. I. du Pont de Nemours and Company
    Inventors: M. Lana Sheer, Lloyd Fox, John Carl Solenberger
  • Patent number: 5686162
    Abstract: Electronic devices protected by an organic polymeric encapsulant and placed in a corrosive environment can have added protection by dispersing in the encapsulant particles of a solid buffer which tend to neutralize the effect of the corrosive agent. This approach is quite effective when strong acids are the corrosive agents, and when solid acid-base buffers are dispersed in the polymeric material. The encapsulant may be elastomeric, and silicone elastomers containing solid acid-base buffers are quite effective in protecting the underlying electronic device from corrosion by strong acids.
    Type: Grant
    Filed: January 31, 1996
    Date of Patent: November 11, 1997
    Assignee: Motorola, Inc.
    Inventors: Anthony J. Polak, Theresa L. Baker
  • Patent number: 5682066
    Abstract: A microelectronic assembly (10) includes an integrated circuit die (12) mounted onto a substrate (14) and spaced apart by a gap (30). Solder bump interconnections (32) extend across the gap (30) and physically attach and electrically connect an electrical circuit on the substrate (14) to an electrical circuit on the integrated circuit die (12). The gap (30) is filled with a transparent encapsulant (16) to protect the solder bump interconnections (32). The transparent encapsulant (16) is composed of a polymeric matrix and filler particles dispersed in the matrix. The polymeric matrix and the filler particles have substantially similar indices of refraction, thereby making the encapsulant (16) transparent. The integrated circuit die (12) includes light emitting diodes (18) that transmit light toward the transparent substrate (14) to form a display.
    Type: Grant
    Filed: August 12, 1996
    Date of Patent: October 28, 1997
    Assignee: Motorola, Inc.
    Inventors: Daniel Roman Gamota, Alan G. Chen, Michael Hertsberg
  • Patent number: 5677511
    Abstract: An apparatus directed to portable peripheral cards is disclosed which provides protection against electro-static discharge and electro-magnetic interference. Furthermore, this apparatus provides a solid housing which affords a strong protective structure for the PC board and also protects the ICs housed inside the peripheral card from being easily accessed.
    Type: Grant
    Filed: March 20, 1995
    Date of Patent: October 14, 1997
    Assignee: National SEmiconductor Corporation
    Inventors: Carl James Taylor, Michael William Patterson
  • Patent number: 5656857
    Abstract: A semiconductor device which realize reduction of thickness with maintaining shielding effect has a shielding package having a substrate with a plurality of electrode pattern provided on a surface thereof and side walls upwardly formed in the peripheral end part of the surface thereof, a semiconductor chip having a plurality of electrodes directly connected to the electrode patterns of the shielding package, respectively, an insulating resin layer of a low dielectric constant formed on the substrate enclosed by the side walls so as to cover, and a conductive resin layer formed on an entire surface of the insulating resin layer.
    Type: Grant
    Filed: May 11, 1995
    Date of Patent: August 12, 1997
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Yoshihiro Kishita
  • Patent number: 5644168
    Abstract: A semiconductor package which comprises a lead frame, a semiconductor chip secured to the lead frame and a mold composition encasing the lead frame and the semiconductor chip has a filler of ceramic particles. Each of the ceramic particles, preferably silica or alumina, has macroscopic pores of sufficient size to receive a resin binder therein, the pores extending from the surface of the particle to the particle interior. A permanently hardenable composition adherable to the ceramic particles preferably an epoxy cresol novolac, extends around the ceramic particles and into the pores. The ceramic particles are formed by providing ceramic particles having a macroscopically smooth surface and subjecting the surfaces of the particles to a composition capable of removing portions of the particles, preferably hydrofluoric acid, while agitating the particles to form the pores.
    Type: Grant
    Filed: May 3, 1995
    Date of Patent: July 1, 1997
    Assignee: Texas Instruments Incorporated
    Inventors: Jeremias P. Libres, Abbas I. Attarwala, Mario A. Bolanos, Jimmy Liang, Indran B. Nair
  • Patent number: 5641997
    Abstract: A semiconductor chip is positioned between encapsulating sheets. The encapsulating sheets each have a surface that is highly adhesive and a surface that is less adhesive. The surface of the encapsulating sheet that is highly adhesive contacts the chip. The surface that is less adhesive contacts a mold. Subsequently, encapsulation is carried out by molding. A soldering resistance can be improved without reducing a mold releasing property.
    Type: Grant
    Filed: September 13, 1994
    Date of Patent: June 24, 1997
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Hideo Ohta, Tetsuo Okuyama, Shinetsu Fujieda, Sadao Kajiura, Akira Yoshizumi
  • Patent number: 5629566
    Abstract: A semiconductor device includes a semiconductor chip which is connected to a circuit substrate via solder bumps by flip-chip connection, a first encapsulant having a large Young's modulus and filling a space between the semiconductor chip and the circuit substrate in the central portion of the semiconductor chip, and a second encapsulant having a small Young's modulus and filling a space between the semiconductor chip and the circuit substrate in the peripheral portion of the semiconductor chip. A method for manufacturing the semiconductor device includes flowing the second encapsulant into position, but not the first encapsulant.
    Type: Grant
    Filed: August 7, 1995
    Date of Patent: May 13, 1997
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Kazuhide Doi, Masayuki Miura, Takashi Okada, Naohiko Hirano, Yoichi Hiruta
  • Patent number: 5617297
    Abstract: A portable peripheral card for an electrical device is disclosed that has an injected molded housing package. In one aspect of the invention, the peripheral card has a printed circuit board, a female electrical connector, and a solid one-piece injected molded package, whereas the molding compound includes organic polymer fibers. The printed circuit board has electrical components mounted thereon and the female electrical connector is attached to the printed circuit board to permit communications between the electrical components on the printed circuit board and the electrical device. The solid one-piece package encapsulates the printed circuit board and the electrical components yet exposes a portion of the electrical connector to facilitate electrical connections between the printed circuit board and the electrical device. In one preferred embodiment, the organic polymer fibers includes at least one selected from the group consisting of cotton, cellulose, polyester and nylon.
    Type: Grant
    Filed: September 25, 1995
    Date of Patent: April 1, 1997
    Assignee: National Semiconductor Corporation
    Inventors: Randy Lo, Hem P. Takiar
  • Patent number: 5597422
    Abstract: The object is to provide a light-transmissive resin sealed semiconductor that is excellent in weatherability, heat resistance and fire retardancy, limits the performance deterioration of a photovoltaic element for a long term due to moisture permeation to an minimum extent, has rubber elasticity necessary for protecting the semiconductor element, and has a surface covering material that is incombustible or fire retardant. This object is achieved by a construction wherein a covering material provided on the surface of the incident light side of photovoltaic element (101), comprises a transparent filler (102) that is cross-linked multi-component copolymer containing vinylidene fluoride and hexafluoropropylene as the major components.
    Type: Grant
    Filed: April 26, 1995
    Date of Patent: January 28, 1997
    Assignee: Canon Kabushiki Kaisha
    Inventors: Ichiro Kataoka, Takahiro Mori, Satoru Yamada, Hidenori Shiotsuka, Ayako Komori
  • Patent number: 5594204
    Abstract: An apparatus directed to portable peripheral cards is disclosed which provide protection against electro-static discharge and electro-magnetic interference. Furthermore, this apparatus provides a solid housing which affords a strong protective structure for the PC board and also protects the ICs housed inside the peripheral card from being easily accessed.
    Type: Grant
    Filed: July 25, 1995
    Date of Patent: January 14, 1997
    Assignee: National Semiconductor Corporation
    Inventors: Carl J. Taylor, Michael W. Patterson, Gordon Force
  • Patent number: 5589714
    Abstract: Semiconductor devices are encapsulated in a thermosetting resin filled with aluminum nitride particles. The aluminum nitride particles have an outer layer of Al--O--N, into which is incorporated amorphous Si--O, which renders them hydrolytically stable. The aluminum nitride particles impart very high thermal conductivity to the cured resin. In addition, the cured resin has a CTE similar to that of the encapsulated semiconductor device, and has excellent dielectric properties.
    Type: Grant
    Filed: March 24, 1995
    Date of Patent: December 31, 1996
    Assignee: The Dow Chemical Company
    Inventor: Kevin E. Howard
  • Patent number: 5585600
    Abstract: The present invention provides a method for forming an improved lead-on chip semiconductor module and an improved module of this type. In a lead-on chip semiconductor device, a semiconductor chip which has a major surface having input and output bonding pads thereon, is secured to a lead frame having a plurality of leads adjacent the bonding pads by means of bonding wires connecting a respective one of the leads to a pad on the chip. A coating of dielectric material having a Young's modulus in the range of about 10 psi to about 500 psi is disposed around the entire length of each of the wires and over the pads and over the portion of the respective leads to which the wires are connected to act as a stress buffer. This material preferably has a T.sub.g of at least as low as -40.degree. C. Also preferably this package is encapsulated with conventional encapsulant.
    Type: Grant
    Filed: September 2, 1993
    Date of Patent: December 17, 1996
    Assignee: International Business Machines Corporation
    Inventors: Francis E. Froebel, David L. Gardell, Gary H. Irish, Mohammed S. Shaikh
  • Patent number: 5578141
    Abstract: A solar cell module in which at least the light receiving surface side of a photovoltaic element is coated with a filler, characterized in that the filler is made of a composition containing vinylidene fluoride copolymer and acrylic resin. The solar cell module is excellent in weather resistance, heat resistance, adhesion to a photovoltaic element (solar cell), and scratch resistance. Moreover, it is capable of minimizing the deterioration of the performance of the solar cell due to moisture permeability, thereby achieving a desirable photoelectric conversion efficiency over a long period of time.
    Type: Grant
    Filed: April 7, 1995
    Date of Patent: November 26, 1996
    Assignee: Canon Kabushiki Kaisha
    Inventors: Takahiro Mori, Ichiro Kataoka, Satoru Yamada, Shigenori Itoyama
  • Patent number: 5561329
    Abstract: Curable silicone compositions comprise either (a) microparticles of a fluororesin which exhibits low adhesion to the cured composition, or (b) microparticles of an organic or inorganic material whose surfaces have been coated with this type of fluororesin. The compositions are useful coatings for semiconductor devices requiring high levels of moisture and heat resistance.
    Type: Grant
    Filed: May 30, 1995
    Date of Patent: October 1, 1996
    Assignee: Dow Corning Toray Silicone Co., Ltd.
    Inventors: Katsutoshi Mine, Hiroyoshi Naito, Kimio Yamakawa
  • Patent number: 5539218
    Abstract: There is disclosed a semiconductor device wherein electrode terminals (2), elements (6) and wires (7) are disposed on a base plate (5) of a case (4) filled with only epoxy resin (1). The epoxy resin (1) contains impurities such as halogen and alkaline metallic salts in an amount of not more than 5 ppm and has a linear expansion coefficient of 5.times.10.sup.-6 to 25.times.10.sup.-6 when hardened. The semiconductor device provides for direct sealing of the components, whereby its size and cost are reduced.
    Type: Grant
    Filed: March 17, 1995
    Date of Patent: July 23, 1996
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Shinobu Takahama, Akinobu Tamaki, Satoshi Hirakawa, Hitoshi Yamano, Teruki Hyougatani
  • Patent number: 5500555
    Abstract: Improved thermal characteristics are obtained in a multi-layer substrate for mounting a semiconductor device. A prepeg layer disposed in close proximity to or immediately adjacent to a semiconductor device is formed incorporating an integral, thermally-conductive mesh or screen. The prepeg layer is preferably a sandwich structure of two BT-resin layers (films), between which is disposed a copper screen. In this manner, heat is conducted away from an operating device by an integral part of the substrate, without the need for additional slugs or heat sink structures. Utility for multichip modules is also disclosed.
    Type: Grant
    Filed: April 11, 1994
    Date of Patent: March 19, 1996
    Assignee: LSI Logic Corporation
    Inventor: Tom Ley
  • Patent number: 5479049
    Abstract: A first transparent protection layer is formed on color filters, and micro lenses are further formed on the first transparent protection layer. Then unevenness due to the micro lenses is flattened by a first transparent resin layer which has water repellency and oil repellency (low surface energy), a high transmittance in visible light range, a high flattening capability in a coating process, and a refractive index lower than the refractive index of the micro lenses. With the above-mentioned arrangement, dust or the like can be difficult to contaminate the surface of the solid state image sensor without loosing the light converging effect of the micro lenses. Even when dust or the like attaches to the surface, it can be easily removed with a cotton swab or the like.
    Type: Grant
    Filed: September 15, 1993
    Date of Patent: December 26, 1995
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Tetsuro Aoki, Shun-ichi Naka
  • Patent number: 5474828
    Abstract: Disclosed herein are electronic device sealing resin compositions containing (A) 40-25 parts by weight of a thermoplastic resin composed of 100-10 wt. % of a poly(arylene thioether-ketone) and 0-90 wt. % of a poly(arylene sulfide), (B) 60-75 parts by weight of an inorganic filler, and per 100 parts by weight of the sum of the thermoplastic resin (A) and inorganic filler (B), (C) 1.5-5 parts by weight of a silicone oil, (D) 10-15 parts by weight of a silicone rubber or (C) 0.5-3 parts by weight of a silicone oil and (D) 5-13 parts by weight of a silicone rubber. Electronic devices sealed using such resin compositions are also disclosed.
    Type: Grant
    Filed: June 30, 1994
    Date of Patent: December 12, 1995
    Assignee: Kureha Kagaku Kogyo K.K.
    Inventors: Toshitaka Kouyama, Keiichiro Suzuki, Toshio Enoki, Yasuo Sakaguchi
  • Patent number: 5471096
    Abstract: Compositions containing bisphenol M dicyanate, prepolymer thereof, or mixtures thereof, and 4,4'-ethylidene bisphenol dicyanate, prepolymer thereof or mixtures thereof; and filler having maximum particle size of 20 microns and being substantially free of alpha particle emissions. The compositions are useful in forming interconnection structures for forming an integrated semiconductor device to a carrier substrate.
    Type: Grant
    Filed: November 4, 1993
    Date of Patent: November 28, 1995
    Assignee: International Business Machines Corporation
    Inventors: Kostas I. Papathomas, Frederick R. Christie, David W. Wang
  • Patent number: 5447576
    Abstract: A composition and method for encapsulating a solar cell which minimizes thermal discoloration, or browning, of the encapsulant. The composition includes an EVA encapsulant, a curing agent and one of two particularly well-suited hindered amine light stabilizers, either O,O-t-Amyl-O-(1,2,2,6,6-Pentamethyl-4-piperidinyl) mono-peroxycarbonate or Poly[(4-hydroxy-2,2,6,6-tetramethyl-1-piperidine-ethanol)-co-dimethyl succinate]. Alternatively, if the selected hindered amine light stabilizer is O,O-t-Amyl-O-(1,2,2,6,6-Pentamethyl-4-piperidinyl) mono-peroxycarbonate, the curing agent need not be included. The composition is applied to a solar cell then cured. The cured product withstands thermal exposure and resists thermal discoloration.
    Type: Grant
    Filed: August 3, 1992
    Date of Patent: September 5, 1995
    Assignee: Siemens Solar Industries International, Inc.
    Inventor: Paul B. Willis
  • Patent number: 5442237
    Abstract: A semicondutor device having electronic circuitry formed in a semiconductor substrate (11) and separated from an overlying metal interconnect layer (18, 18') using a fluorinated polymer dielectric (14,14'). The fluorinated polymer layer (14,14') may be formed directly on metallic surfaces, or formed on a semiconductor or non-metallic surface using an adhesion promoter (13,13'). Once formed, the fluorinated polymer layer (14,14') can be patterned to provide vias, and covered with a patterned metal interconnect layer (18, 18').
    Type: Grant
    Filed: February 4, 1994
    Date of Patent: August 15, 1995
    Assignee: Motorola Inc.
    Inventors: Henry G. Hughes, Ping-Chang Lue, Frederick J. Robinson
  • Patent number: 5430330
    Abstract: A semiconductor device where electrode terminals (2), elements (6) and wires (7) are disposed on a base plate (5) of a case (4) filled with only epoxy resin (1). The epoxy resin (1) contains impurities such as halogen and alkaline metallic salts in an amount of not more than 5 ppm and has a linear expansion coefficient of 5.times.10.sup.-6 to 25.times.10.sup.-6 when hardened. The semiconductor device provides for direct sealing of the components, its size and cost are therefore reduced.
    Type: Grant
    Filed: June 18, 1993
    Date of Patent: July 4, 1995
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Shinobu Takahama, Akinobu Tamaki, Satoshi Hirakawa, Hitoshi Yamano, Teruki Hyougatani