Abstract: There is provided a resin composition having high flame retardancy, which improves high temperature storage of an epoxy resin composition comprising an epoxy resin having biphenyl structure without a halogenated flame retardant and an antimony compound as a conventional flame retardant. High temperature storage was improved, a glass transition temperature (Tg) became not less than 150° C. and V-0 class in flame retardance standard (UL94) was accomplished by employing (1) an epoxy resin having biphenyl structure mainly as an epoxy resin, (2) a phenolic aralkyl resin mainly as a curing agent, (3) 0.5 to 30 parts by weight of a polyimide resin as an additive based on total 100 parts by weight of the epoxy resin and the curing agent, (4) a polysiloxane compound modified with polyether containing an amino group as a flame retardant, (5) not less than 87% by weight of a fused silica as an inorganic filler based on the total composition.

Abstract: A microelectronic substrate assembly and method for manufacture. In one embodiment, bond members (such as solder balls) project away from a surface of the microelectronic substrate to define a fill region or cavity between the surface of the microelectronic substrate and the bond members. A fill material is disposed in the fill region, for example, by dipping the microelectronic substrate in reservoir of fill material so that a portion of the fill material remains attached to the microelectronic substrate. An exposed surface of the fill material is engaged with a support member, such as a printed circuit board, and the bond members are attached to corresponding bond pads on the support member. The microelectronic substrate and the fill material can then be encapsulated with an encapsulating material to form a device package.

Abstract: An epoxy resin composition to seal semiconductors constructed of a semiconductor element, a base to support said semiconductor element, and an epoxy resin composition covering only one side opposite to the base, said epoxy resin composition comprising (A) epoxy resin, (B) hardener, and (C) inorganic filler, and giving a cured product which has (a) a flexural modulus of elasticity of 10 to 30 GPa at 23° C. and (b) a coefficient of linear expansion of 4×10−6/K to 10×10−6/K in the temperature range from 23° C. to the glass transition point, with the product of (a) and (b) being smaller than 2×10−4 GPa/K.

Abstract: An electronic package and/or package lid includes at least one connection slot for receiving a line, such as an optical fiber. The package and/or package lid also includes at least one sealant slot proximate the connection slot. Optical fibers are connected to a component, such as an opto-electronic component, through the connection slot. A sealant provided via the sealant slot hermetically seals the optical fibers within the connection slot.

Abstract: A new interconnection scheme is disclosed for a tape automated bonding (TAB) package, a flip chip package and an active matrix liquid crystal display (AMLCD) panel, where an electrically conducting adhesive is used to form an electrical interconnection between an active electronic device and its components. The electrically conducting adhesive can be a mixture comprising a polymer resin, a no-clean solder flux, a plurality of electrically conducting particles with an electrically conducting fusible coating which provides a metallurgical bond between the conducting particles as well as to the substrates. The advantages of using the electrically conducting adhesives include reduction in bonding pressure and/or bonding temperature, control of interfacial reactions, promotion of stable metallurgical bonds, enhanced reliability of the joints, and others.

Abstract: A semiconductor device comprising: a semiconductor element having a plurality of electrodes; a passivation film formed on the semiconductor element in a region avoiding at least a part of each of the electrodes; a conductive foil provided at a given spacing from the surface on which the passivation film is formed; an external electrodes formed on the conductive foil; intermediate layer formed between the passivation film and the conductive foil to support the conductive foil; and wires electrically connecting the electrodes to the conductive foil; wherein a depression tapered in a direction from the conductive foil to the passivation film if formed under a part of the conductive foil that includes the connection with the external electrodes.

Abstract: The present invention provides a process for the production of a semiconductor device comprising a semiconductor element provided on a printed circuit board with a plurality of connecting electrode portions provided interposed therebetween, the gap between said printed circuit board and said semiconductor element being sealed with an underfill resin layer.

Abstract: A fuse link 16 is formed of a portion of a top level of patterned metal conductor in a multilevel conductor integrated circuit 10. A deposited layer of oxide material 26 covers the fuse link. Radiant energy from such as a laser 36 is directed through the oxide material 26 to heat and open the fuse link 16. Layers of deposited protective oxide 28 and PIX 30 then cover the fuse link and layer of oxide material. One photoprocessing step is avoided by locating the fuse link 16 and bond pad 22, both made from the top layer of conductive material, at different levels. The blanket etch then exposes the bond pad 22 while leaving the fuse link 16 covered. The fuse link can be formed down in a step 38 or the bond pad 22 can be formed above such as a group of memory cells 80. The bond pad 22 and fuse link 16 also can be formed at the same level with other process procedures.

Abstract: A connection component is provided. The connection component includes (1) a first interposer having a first surface to which a microelectronic may be mounted and a second surface opposite from the first surface, (2) a second interposer that is more flexible than the first interposer and that is disposed under the second surface of the rigid interposer, and (3) a plurality of conductive parts that may be positioned in the first and second interposers and that may be exposed at the first surface of the first interposer, a bottom surface of the second interposer, or both the first and bottom surfaces. The electrically conductive parts may include leads. A socket assembly or a microelectronic element such as semiconductor chip may be mounted onto the first surface of the rigid interposer. The connection component may be mounted onto a support substrate.

Abstract: In a semiconductor-sealing liquid epoxy resin composition comprising (A) a liquid epoxy resin, (B) a curing agent, and (C) an inorganic filler, the inorganic filler has such a controlled particle size distribution that the composition provides improved interstitial infiltration and has a low modulus of elasticity in the cured state.

Abstract: An integrated circuit chip package according to the present invention includes an integrated circuit chip that is mounted on a substrate by a reflow process and by a plurality of solder bumps. At least one standoff is located between the circuit chip and the substrate to maintain a distance between the circuit chip and the substrate during the reflow process. A mold compound is used for underfilling air gaps between the chip and the substrate. The integrated circuit chip package is formed by placing the chip and substrate within a mold cavity and pressing a transfer mold compound into the mold cavity. Air spaces between the integrated circuit chip and the substrate are underfilled by the mold compound as it is pressed in between the integrated circuit chip, the standoffs and the substrate. Air is allowed to escape from between the chip and the substrate during the underfilling through a vent which extends through the substrate.

Abstract: In order to provide a resin sealed electronic device which is capable of securing high reliability by packaging with a transfer molding resin without using any under filler material, a resin sealed electronic device mounts a flip chip type monolithic IC on a hybrid circuit board through bumps and is packaged with a thermosetting resin through transfer molding. The transfer molding resin has a linear expansion coefficient of 3×10−6 to 17×10−6 and contains a filler having a particle size smaller than a height of the bump by more than 10 &mgr;m. The resin sealed electronic device is integrated in a unit including the hybrid circuit board mounting the flip chip type monolithic IC through transfer molding with the transfer molding resin, and the bump is restrained from moving by the transfer molding resin flowing around at transfer-molding.

Abstract: A device that reduces the interfacial stress caused by differential thermal expansion in an IC/PC board assembly can be created by attaching an annular part, that has a higher coefficient of thermal expansion, to the IC at an elevated temperature. When the assembly cools the annular part contracts and compresses the IC, increasing the change in size of the IC and reducing the stress in the IC/PC joint.

Abstract: The present invention relates to a semiconductor encapsulating resin composition which is safe and superior in moisture resistance, flame retardance and moldability, and to a highly reliable semiconductor device which is fabricated by encapsulating a semiconductor element with such a semiconductor encapsulating resin composition. The resin composition according to the present invention comprises a thermosetting resin, a hardening agent and a compound metal hydroxide of polyhedral crystal form represented by the following general formula (1): m(MaOb).n(QdOe).cH2O  (1) [wherein M and Q are different metal elements; Q is a metal element which belongs to a group selected from IVa, Va, VIa, VIIa, VIII, Ib and IIb groups in the periodic table; m, n, a, b, c, d and e, which may be the same or different, each represents a positive number].

Abstract: An electronic assembly includes a flexible multilayer substrate having integral electrically-conductive traces that also includes, as a lowermost layer, a metal foil. A plurality of uppermost layers, likewise including a metal foil, form a thin barrier member that is sealingly attached to the substrate's other layers. In this manner, a plurality of electronic components, mounted on the substrate's other layers so as to be electrically interconnected with the traces before sealingly attaching the barrier member, are encapsulated within metal foil to provide an environmentally-sealed assembly featuring improved resistance to moisture diffusion and penetration/permeation of other substances characteristic of the assembly's service environment into the assembly. A filler material, also encapsulated within the metal foil, is operative to neutralize a predetermined amount of a penetrant, further improving the operability and service life of the assembly.

Abstract: A sealing material comprising (A) a liquid epoxy resin, (B) a curing agent, (C) spherical silica, (D) a soft x-ray non-transmissive spherical inorganic filler, and (E) a curing accelerator is suited as an underfill material for flip-chip type semiconductor devices. The sealing material has improved thin-film infiltration and storage stability. The filled state or seal defects can be readily inspected using soft x-rays.

Abstract: A solar cell module is constructed in such an arrangement that a photovoltaic element is covered by at least a sealant resin and a surface protecting film, wherein the oxygen permeability of the surface protecting film is not less than 1 cc/m2·24 hr·atm and not more than 50 cc/m2·24 hr·atm at 25° C./90% RH, thereby providing the solar cell module with high reliability, free of deterioration of the sealant resin, particularly free of yellowing, in long-term outdoor exposure use.

Abstract: A thermal conductive sheet including at least 70-95 weight parts of inorganic filler and 5-30 weight parts of thermosetting resin composition and having flexibility in an uncured state is prepared. Through-holes are formed in the thermal conductive sheet and a conductive resin composition is filled in the through-holes. The thermal conductive sheet and a semiconductor chip are overlapped to match positions of the through-holes formed in the thermal conductive sheet with those of the electrodes formed on the semiconductor chip. The thermal conductive sheet and the semiconductor chip are compressed while being heated and the thermal conductive sheet is cured and integrated with the semiconductor chip. An external lead electrode is formed on the thermal conductive sheet at a side opposite to the surface where the semiconductor chip is overlapped, and that is connected with the conductive resin composition.

Abstract: A simplified process for flip-chip attachment of a chip to a substrate is provided by pre-coating the chip with an encapsulant underfill material having separate discrete solder columns therein to eliminate the conventional capillary flow underfill process. There is also provided a flip-chip configuration having a flexible tape lamination for underfill encapsulation. With this configuration, the complaint solder/flexible encapsulant understructure absorbs the strain caused by the difference in the thermal coefficients of expansion between the chip and the substrate and provides enhanced ruggedness.

Abstract: The present invention is directed to a resin ceramic composition that includes a ceramic filler in an amount effective for providing a single composition with a magnetic field of at least one gauss.

Abstract: A semiconductor light emitting device includes a semiconductor light emitting element (1), a resin stem (10) having a recess (7), and a projection (9) made of a light-transmissive thermosetting resin on the resin stem so as to cover the entire upper surface and continuous upper part of side surfaces of the resin stem to a predetermined depth. The recess is filled with a light-transmissive resin encapsulating element (5) to embed the semiconductor light emitting element, one end of an externally extended first lead (21) and one end of an externally extended second lead (22) electrically connected to first and second electrodes of the semiconductor light emitting element, and a bonding wires (4) connecting the second lead to the second electrode. The projection functions as a lens and is made by hardening a fluid-state resin in an encapsulating case mold.

Abstract: The present invention is a method of providing a protective covering on an electronic package including a first circuitized substrate, a semiconductor chip positioned on and electrically coupled to the first substrate, and a plurality of conductors also on the substrate for electrically connecting the substrate to an external circuitized substrate. In one version, the method comprises covering substantially all of the external surfaces of the substrate, the semiconductor chip and a portion of the plurality of conductors with a protective covering from immersion in a dielectric solution (e.g., TEFLON AF). The coatings can also be applied by brushing, spraying, or chemical vapor deposition. In an alternative embodiment, all of the external surfaces, including all of the conductors, are coated with the protective covering (e.g., to facilitate package shipment or other handling). The resulting electronic packages are also described herein.

Abstract: An element such as a semiconductor wafer or other body is provided with flexible leads, the tip ends of which project over the front surface of the element. The tips of the flexible leads are spaced apart from the front surface and are independently moveable with respect to the element. The flexible leads may be curved in a plane parallel to the front surface of the element, or may be curved so that the tip end of each flexible lead is disposed further from the front surface of the element than the main body of the flexible lead.

Abstract: A resin sealed semiconductor device is provided with an organic resin wiring substrate, an LSI chip having a semiconductor integrated circuit and mounted in a bare chip package form to the organic resin wiring substrate through a plurality of electrical bonding members, and a resin charged into a gap portion between the organic resin wiring substrate and the LSI chip. In this resin sealed semiconductor device, a modulus of longitudinal elasticity of the resin to be charged, its coefficient of linear thermal expansion and its fillet shape are optimized. The resin charged is also preferably colored in black to minimize adverse effects of visible rags on the LSI chip.

Abstract: A chip scale package mainly comprises a semiconductor chip disposed on an upper surface of a substrate and sealed by a package body. The package body comprises a resin base material divided into a first region and a second region. The resin base material contains a plurality of filler particles having the percentage by weight of the filler particles in the first and second regions being different. Thus, in accordance with the present invention, the package provides better buffering effect for stresses due to CTE mismatch between the substrate and the chip, and significantly reduces the moisture from surrounding diffusing into the package thereby reducing the problems of delamination or die-cracking.

Abstract: Filled, curable siloxane encapsulant compositions containing a curable siloxane base resin with functional groups reactive with functional groups of a hardener compound to form a polysiloxane, and filler particles with surface functional groups reactive with the hardener compound functional groups, wherein the filler particles have at least a bi-modal particle packing distribution of first filler particles having a first diameter and second filler particles having a second diameter smaller than the first diameter, and the first and second filler particles are present in amounts effective to provide a particle packing distribution with a relative bulk volume of at least about 90 percent.

Abstract: A composition for sealing a semiconductor device contains polyphenylene sulfide wherein a line expansion coefficient at 150° C. to 200° C. is 4.75×10−5 [1/°C.] or less, a line thermal expansion coefficient at 80 to 130° C. is 6.0×10−5 [1/°C.] or less, and a line expansion coefficient ratio between the flow direction and a normal direction of the flow direction is 0.55 or more.

Abstract: A flip chip having solder bumps and an integrated flux and underfill, as well as methods for making such a device, is described. The resulting device is well suited for a simple one-step application to a printed circuit board, thereby simplifying flip chip manufacturing processes which heretofore have required separate fluxing and underfilling steps.

Abstract: A process for forming a thermally enhanced Chip On Board semiconductor device with a heat sink is described. In one aspect, a thermally conducting filled gel elastomer material or a silicon elastomeric material or elastomeric material, if the material is to be removed, is applied to the die surface to which the heat sink is to be bonded. During the subsequent glob top application and curing steps, difficult-to-remove glob top material which otherwise may be misapplied to the die surface adheres to the upper surface of the elastomer material. The elastomer material is removed by peeling prior to adhesion bonding of the heat sink to the die. In another aspect, the thermally conducting filled gel elastomer material is applied between a die surface and the inside attachment surface of a cap-style heat sink to eliminate overpressure on the die/substrate interface.

Abstract: A flexible printed board according to this invention relates to a flexible printed board on which a semiconductor element flip-chip-bonded. The flexible printed board has an element formation surface of the semiconductor element is shielded from light by a light-shielding member.

Abstract: A curable silicon composition, comprising (A) 100 parts by weight of an organopolysiloxane containing silicon-bonded aryl groups and at least two alkenyl groups per molecule, and having a viscosity of from 0.01 to 1,000 Pa.s at 25° C., wherein the aryl groups comprise from 1 to 40 mole % of the total silicon-bonded organic groups in the organopolysiloxane; (B) an organopolysiloxane having a viscosity of from 0.001 to 10 Pa.s at 25° C. and containing at least 2 silicon-bonded hydrogen atoms per molecule, in a quantity sufficient to cure the composition; (C) a platinum catalyst in a quantity sufficient to cure the composition; and (D) 0.00001 to 100 parts by weight of an organopolysiloxane having a viscosity of from 0.01 to 10,000 Pa.s at 25° C.

Abstract: A flip-chip type semiconductor device has a semiconductor chip mounted on a substrate via a plurality of bumps. The gap between the substrate and the chip is filled with an underfill material and sealed along sides thereof with a fillet material. The underfill material is a cured epoxy resin composition comprising a liquid epoxy resin and an inorganic filler, having a coefficient of expansion of 20-40 ppm/° C. below its Tg. The fillet material is a similar cured epoxy resin composition having a coefficient of expansion of less than 20 ppm/° C. below its Tg. The device is highly reliable.

Abstract: A circuit assembly includes a substrate layer, a first conductive layer mounted to the substrate layer and a second conductive layer. The first and second conductive layers are adhered by an adhesive layer having non-electrically conductive particles for separating the first and second conductive layers.

Abstract: A semiconductor device comprising a film substrate and a semiconductor chip bonded to an upper surface of the film substrate is provided. The semiconductor chip has a main surface formed with a plurality of terminal pads. The film substrate has a lower surface formed with a plurality of external terminal portions in a matrix pattern, and an upper surface formed with a plurality of wiring patterns for respectively connecting with the external terminal portions. The wiring patterns formed in the upper surface of the film substrate are respectively connected to the terminal pads formed on the main surface of the semiconductor chip.

Abstract: A flip chip having solder bumps and an integrated flux and underfill, as well as methods for making such a device, is described. The resulting device is well suited for a simple one-step application to a printed circuit board, thereby simplifying flip chip manufacturing processes which heretofore have required separate fluxing and underfilling steps.

Abstract: A semiconductor device includes a main chip and a sub-chip. The both chips are in a mount-structure, and molded by a resin package. The main chip has electrode pads formed at an periphery in a connecting surface thereof, while the sub-chip has a plurality of connecting bumps formed at a periphery in a connecting surface at positions corresponding to the plurality of electrode pads. A plurality of dummy bumps are formed at a central area of the connecting surface of the sub-chip. Connections are made respectively between the connecting bumps and the connecting electrodes. The main chip and the sub-chip have the connecting bumps and dummy bumps interposed therebetween to thereby prevent the main chip and/or the sub-chip from warping.

Abstract: A semiconductor chip package structure for providing a reliable interface between a semiconductor chip and a PWB to accommodate for the thermal coefficient of expansion mismatch therebetween. The interface between a chip and a PWB is comprised of a package substrate having a plurality of compliant pads defining channels therebetween. The package substrate is typically comprised of a flexible dielectric sheet that has leads and terminals on at least one surface thereof. The pads have a first coefficient of thermal expansion (“CTE”) and are comprised of a material having a fairly low modulus of elasticity. An encapsulant having a second CTE lower than the CTE of the compliant pads is disposed within the channels to form a uniform encapsulation layer. The pads are in rough alignment with the conductive terminals on the package substrate thereby allowing independent movement of the terminals during thermal cycling of the chip.

Abstract: A semiconductor device is disclosed wherein a pair of radiating terminals and a plurality of lead terminals are formed from a single lead frame. A hole or holes in each radiating terminal are formed with an equal width and in an equal pitch to those of gaps between the lead terminals, and the opposite sides of each hole of the radiating terminal are connected to each other by a support element. The support elements of the radiating terminals and support elements which interconnect the lead terminals are formed with an equal length and in an equal pitch to allow the support elements to be cut away by a plurality of punches which are arranged in an equal pitch and have an equal width.

Abstract: An integrated circuit chip package according to the present invention includes an integrated circuit chip mounted on a substrate by a plurality of solder bumps. A mold compound is used for underfilling air gaps between the chip and the substrate. The integrated circuit chip package is formed by placing the chip and substrate within a mold cavity and pressing a transfer mold compound into the mold cavity. Air spaces between the integrated circuit chip and the substrate are underfilled by the mold compound as it is pressed in between the integrated circuit chip and the substrate. Air is allowed to escape from between the chip and the substrate during the underfilling through a vent which extends through the substrate. The underfilling material may also be used to encapsulate the chip at the same time that underfilling is performed.

Abstract: A stable low-connecting resistance connection arrangement having a high yield rate without using any special material or process for a substrate. A flip-chip connecting structure in which the semiconductor integrated circuit (IC) chip is mounted directly on an organic circuit substrate. To achieve reliable connection and low-connecting resistance, the present invention absorbs variation of the heights of projecting electrodes formed on a semiconductor IC chip and substrate electrodes of an organic circuit substrate for example, by deforming the substrate electrodes and/or substrate layer of the organic circuit substrate. Resin of a conductive paste disposed between the projecting electrodes and substrate electrodes is squeezed out leaving a high density conductive particle layer to lower a contact resistance between such electrodes.

Abstract: The instant invention pertains to a multi-layer tamper proof electronic coating wherein the first layer is a protecting layer produced from a preceramic silicon containing material and at least one filler. The second layer is a resin sealer coat produced from a sealer resin selected from the group consisting of colloidal inorganic-based siloxane resins, benzocyclobutene based resins, polyimide polymers, siloxane polyimides and parylenes. An optional third layer is a cap coating layer selected from SiO.sub.2 coating, SiO.sub.2 /ceramic oxide coating, silicon containing coatings, silicon carbon containing coatings, silicon nitrogen containing coatings, silicon oxygen nitrogen coatings, silicon nitrogen carbon containing coatings and/or diamond like coatings.

Abstract: A solid state pickup device to which the present invention is applicable comprises a base member (1a) and a solid state pickup chip (3) having a bottom surface, a receiving surface for receiving light signal, and a side surface. The solid state pickup chip is glued on the base member by using a first adhesive (7). The solid state pickup device further comprises a solid package (6) formed around the base member and the solid state pickup chip having transparency. Herein, the first adhesive has flexibility. The solid state pickup device still further comprises a covering member (5) formed around the receiving and the side surfaces of the solid state pickup chip having transparency and flexibility.

Abstract: A method and an apparatus for providing a planar and compliant interface between a semiconductor chip and its supporting substrate to accommodate for the thermal coefficient of expansion mismatch therebetween. The complaint interface is comprised of a plurality of compliant pads defining channels between adjacent pads. The pads are typically compressed between a flexible film chip carrier and the chip. A compliant filler is further disposed within the channels to form a uniform encapsulation layer having a controlled thickness.

Abstract: A sealing label for sealing semiconductor element comprises a metal foil substrate or a heat-resisting organic film substrate having formed thereon a sealing material component layer for sealing a semiconductor element, wherein the sealing material component layer is convexly formed such that the layer has a thick flat portion at the central portion of the substrate as compared with the peripheral portion of the substrate. The use of the sealing label in molding a semiconductor device can provide a semiconductor device having a high quality without substantially having voids in the sealing resin.

Abstract: A resin encapsulated semiconductor element is encapsulated with resin composition containing an organic compound selected from the group consisting of organobromine compounds, organophosphorus compounds and organonitrogen compounds, an inorganic filler, and a metal borate. The obtained resin encapsulated semiconductor element has the same flame resistance as a conventional semiconductor element which is encapsulated with a resin composition containing a halogen and antimony compound, and furthermore, has remarkably improved reliabilities regarding moisture resistance and storing at a high temperature by effects of the contained metal borate for suppressing generation of or trapping released gas components, such as halogen or phosphorus, and others.

Abstract: A composition and method for encapsulating a photovoltaic device which minimizes discoloration of the encapsulant. The composition includes an ethylene-vinyl acetate encapsulant, a curing agent, an optional ultraviolet light stabilizer, and/or an optional antioxidant. The curing agent is preferably 1,1-di-(t-butylperoxy)-3,3,5-trimethylcyclohexane; the ultraviolet light stabilizer is bis-(N-octyloxy-tetramethyl) piperidinyl sebacate and the antioxidant is selected from the group consisting of tris (2,4-di-tert-butylphenyl) phosphite, tetrakis methylene (3,5-di-tert-butyl-4-hydroxyhydrocinnamate) methane, octadecyl 3,5-di-tert-butyl-4-hydroxyhydrocinnamate, and 2,2'-ethylidene bis(4,6-di-t-butylphenyl) fluorophosponite. The composition is applied to a solar cell then cured. The cured product contains a minimal concentration of curing-generated chromophores and resists UV-induced degradation.

Abstract: A chip component mounting board includes a chip mounting portion and a first groove. A chip component is mounted on the chip mounting portion. The chip mounting portion has a connection pad electrically connected to the chip component. The first groove is formed in the chip mounting portion to extend from a center of the chip mounting portion to one side of the chip mounting portion while gradually increasing its width. A method of manufacturing a chip component mounting board is also disclosed.

Abstract: Method for implementing a multi-phase plastic package for electronic components, and packaged electronic components produced according to the method. The present invention contemplates the use of molding compounds having two or more discrete phases in a transfer molding process wherein a temperature differential is induced between the electronic component to be packaged and the mold of the molding apparatus prior to molding. Each of the molding compound phases, when used in a current transfer molding apparatus, generates a separate layer in the resultant package, and each of the resultant layers possesses certain unique properties. In its simplest implementation, the present invention provides a two-phase molding compound pellet which provides an outer layer containing mold release compounds to facilitate release of the completed packaged device from the mold, and an inner layer without mold release agents. Other implementations include multiple layers.

Abstract: An integrated circuit chip package according to the present invention includes an integrated circuit chip mounted on a substrate by a plurality of solder bumps. A mold compound is used for underfilling air gaps between the chip and the substrate. The integrated circuit chip package is formed by placing the chip and substrate within a mold cavity and pressing a transfer mold compound into the mold cavity. Air spaces between the integrated circuit chip and the substrate are underfilled by the mold compound as it is pressed in between the integrated circuit chip and the substrate. Air is allowed to escape from between the chip and the substrate during the underfilling through a vent which extends through the substrate. The underfilling material may also be used to encapsulate the chip at the same time that underfilling is performed.

Abstract: Electronic devices protected by an organic polymeric encapsulant and placed in a corrosive environment can have added protection by dispersing in the encapsulant particles of a solid buffer which tend to neutralize the effect of the corrosive agent. This approach is quite effective when strong acids are the corrosive agents, and when solid acid-base buffers are dispersed in the polymeric material. The encapsulant may be elastomeric, and silicone elastomers containing solid acid-base buffers are quite effective in protecting the underlying electronic device from corrosion by strong acids.