With Specified Filler Material Patents (Class 257/789)
  • Patent number: 6774493
    Abstract: A simplified process for flip-chip attachment of a chip to a substrate is provided by precoating the chip with an encapsulant underfill material having separate discrete solder columns therein to eliminate the conventional capillary flow underfill process. Such a structure permits incorporation of remeltable layers for rework, test, or repair. It also allows incorporation of electrical redistribution layers. In one aspect, the chip and pre-coated encapsulant are placed at an angle to the substrate and brought into contact with the pre-coated substrate, then the chip and pre-coated encapsulant are pivoted about the first point of contact, expelling any gas therebetween until the solder bumps on the chip are fully in contact with the substrate. There is also provided a flip-chip configuration having a complaint solder/flexible encapsulant understructure that deforms generally laterally with the substrate as the substrate undergoes expansion or contraction.
    Type: Grant
    Filed: March 19, 2003
    Date of Patent: August 10, 2004
    Assignee: M. A. Capote
    Inventors: Miguel A. Capote, Zhiming Zhou, Xiaoqi Zhu, Ligui Zhou
  • Patent number: 6774501
    Abstract: A resin-sealed semiconductor device which comprises a lead frame having a die bond pad and an inner lead, a semiconductor chip installed on the die bond pad via a die bonding material and a sealing material for sealing the semiconductor chip and the lead frame, wherein properties of the die bonding material and the sealing material after curing satisfies the following formulae: &sgr;e≦0.2×&sgr;b formula (1) Ui≧2.0×10−6×&sgr;ei formula (2) Ud≧4.
    Type: Grant
    Filed: March 21, 2003
    Date of Patent: August 10, 2004
    Assignee: Hitachi Chemical Co., Ltd.
    Inventors: Kazuhiko Kurafuchi, Naoya Suzuki, Masaaki Yasuda, Tatsuo Kawata, Hiroyuki Sakai, Masao Kawasumi
  • Patent number: 6762509
    Abstract: A flip-chip packaging method for a semiconductor device treats a portion of an interconnect substrate so that a fill material when liquid beads on the treated portion of the interconnect substrate. When the fill material is dispensed on the interconnect substrate to fill a gap under the semiconductor device, the beading of the fill material prevents formation of fillets that might otherwise create a variation in the thermal coefficient of expansion of fill material and/or warp the interconnect substrate. The treated portion of the interconnect substrate can be roughened or coated with a material that differs from other portions of the interconnect substrate and thereby causes beading.
    Type: Grant
    Filed: December 11, 2001
    Date of Patent: July 13, 2004
    Assignees: Celerity Research Pte. Ltd., ASE Electronics (M) Sdn. Bhd.
    Inventors: Robert M. Hilton, Sabran B. Samsuri
  • Patent number: 6762511
    Abstract: A device allows for continuous regulation of the composition of a fluid mixture that includes at least two components of different polarities. The device is designed, for example, to be inserted in a separation system that the device supplies with a carrier fluid of stabilized composition. The device includes a storage tank (3) receiving a mixture coming from the separation system and at least one auxiliary vessel (6) containing one of the components of the mixture. To control the transfer of this component from auxiliary vessel (6) to storage tank (3), the device further includes at least one tubular capacitive sonde (CS) totally immersed in the fluid mixture, a sonde (TS) for measuring the temperature of the mixture, and a sondc (LS) for measuring the mixture level in storage tank (3).
    Type: Grant
    Filed: March 19, 2001
    Date of Patent: July 13, 2004
    Assignee: Hitachi, Ltd.
    Inventors: Yuichi Satsu, Harukazu Nakai, Akio Takahashi, Masao Suzuki, Katsuo Sugawara
  • Patent number: 6756685
    Abstract: In a semiconductor device which is formed by connecting electrodes of a package substrate composed of a resin and electrodes of a semiconductor chip formed of a silicon semiconductor, an underfill resin having the Young's modulus of less than 100 kgf/mm2 is filled in the gap of the junction between the semiconductor chip and the package substrate.
    Type: Grant
    Filed: August 1, 2002
    Date of Patent: June 29, 2004
    Assignee: NEC Electronics Corporation
    Inventor: Tetsuya Tao
  • Patent number: 6750550
    Abstract: An adhesive composition for bonding semiconductor chips to their chip mounting components comprising a curable polymer composition comprising from 1 to 900 weight-ppm spherical filler having an average particle size of from 10 to 100 &mgr;m and a major axis-to-minor axis ratio of from 1 to 1.5. Also, semiconductor devices in which a semiconductor chip therein is bonded to its chip mounting component by the aforesaid adhesive composition.
    Type: Grant
    Filed: June 20, 2000
    Date of Patent: June 15, 2004
    Assignee: Dow Corning Toray Silicone Co., Ltd.
    Inventors: Kimio Yamakawa, Minoru Isshiki, Katsutoshi Mine
  • Patent number: 6747203
    Abstract: A photovoltaic module including: a light-transmissive substrate; a first sealing polymer layer stacked on the substrate; a photovoltaic cell stacked on the first sealing polymer layer; a second sealing polymer layer stacked on the photovoltaic cell and a weatherproof film stacked on the second sealing polymer layer, wherein the weatherproof film includes a moisture-proof layer provided on the second sealing polymer layer and a gas-proof layer provided on the moisture-proof layer, the gas-proof layer being made of polyphenylene sulfide.
    Type: Grant
    Filed: July 10, 2002
    Date of Patent: June 8, 2004
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Yukio Fukuda, Akimasa Umemoto, Noriaki Shibuya
  • Publication number: 20040106232
    Abstract: A process of making an electrode-to-electrode bond structure includes a step of forming a resin coating on a first bonding object having a first electrode portion in a manner such that the resin coating covers the first electrode portion. Then, an opening is formed in the resin coating to expose the first electrode portion. Then, the opening is filled with a metal paste containing a metal and a resin component. Then, the first bonding object is placed on a second bonding object having a second electrode portion in a manner such that the metal paste filled in the opening faces the second electrode portion while the resin coating contacts the second bonding object. Finally, heat-treatment is performed to cause the first electrode portion and the second electrode portion to be electrically connected with each other via the metal while causing the resin coating to harden.
    Type: Application
    Filed: November 12, 2003
    Publication date: June 3, 2004
    Applicant: FUJITSU LIMITED
    Inventors: Seiki Sakuyama, Nobuhiro Imaizumi, Tomohisa Yagi
  • Patent number: 6744137
    Abstract: An apparatus for making a semiconductor assembly and, specifically, interconnecting a semiconductor die to a carrier substrate. The carrier substrate includes a first surface and a second surface with at least one opening therethrough. The die includes an active surface and a back surface, wherein the die is attached facedown to the first surface of the carrier substrate with conductive bumps therebetween. In addition, a plurality of bond wires is attached through the at least one opening in the carrier substrate between the active surface of the die and the second surface of the carrier substrate. With this arrangement, both the conductive bumps and the bond wires share in the electrical interconnection between the die and the carrier substrate, thereby allowing more space for bond pads to interconnect with bond wires and/or allowing for smaller die sizes.
    Type: Grant
    Filed: March 5, 2002
    Date of Patent: June 1, 2004
    Assignee: Micron Technology, Inc.
    Inventor: Larry D. Kinsman
  • Patent number: 6734571
    Abstract: An encapsulation mold for forming an encapsulation layer over a semiconductor assembly is disclosed. A semiconductor assembly with multiple semiconductor dies secured to a single semiconductor support structure is inserted into an encapsulation mold. The mold contains a first section and a second section, which form a cavity around the assembly. The mold contains an aperture for transferring encapsulating material into the mold cavity. One of the mold sections has a design feature, such as a raised rib or groove interconnecting at approximately the separation or saw-cut regions of the individual dies of the assembly. Encapsulation material is inserted into the mold cavity until the cavity is filled. The mold section design feature shapes the top surface of the encapsulation layer. The mold is removed leaving the exterior surface of the encapsulation layer patterned with the design feature.
    Type: Grant
    Filed: January 23, 2001
    Date of Patent: May 11, 2004
    Assignee: Micron Technology, Inc.
    Inventor: Todd O. Bolken
  • Patent number: 6727575
    Abstract: The semiconductor device comprises a lead frame including a die pad portion for mounting a semiconductor element thereon and a board mounting portion for mounting a circuit board thereon, and a sealing resin for sealing the semiconductor element, the circuit board, the die pad portion and the board mounting portion. The lead frame further includes an anchoring region having a higher anchoring effect for the resin than that of each of the die pad portion and the board mounting portion between at least the die pad portion and the board mounting portion. The anchoring region enhances the adhesion of a sealing resin to a lead frame, to prevent the crack of a semiconductor device to be mounted on the lead frame and the disconnection of a bonding wire.
    Type: Grant
    Filed: September 17, 2001
    Date of Patent: April 27, 2004
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventor: Katsumi Sakabe
  • Patent number: 6724079
    Abstract: A wire bond-less electronic component is for use with a circuit external to the wire bond-less electronic component. The wire bond-less electronic component includes a support substrate (110, 410), an electronic device (130) over the support substrate, and a cover (140, 440, 540) located over the electronic device and the support substrate. The cover includes an interconnect structure (141, 441, 541) electrically coupled to the electronic device and adapted to electrically couple together the electronic device and the circuit for providing impedance transformation of an electrical signal between the electronic device and the circuit.
    Type: Grant
    Filed: January 4, 2002
    Date of Patent: April 20, 2004
    Assignee: Motorola, Inc.
    Inventors: Lakshminarayan Viswanathan, Pierre-Marie Piel, Garry D. Funk, Robert Paul Davidson
  • Patent number: 6690086
    Abstract: A method for inhibiting damage caused to semiconductor die packages during a molding process, and the semiconductor die packages formed therefrom, is described. One or more openings are provided in a die carrier which are filled with a material which is more resistant to compressive forces than the carrier.
    Type: Grant
    Filed: December 13, 2002
    Date of Patent: February 10, 2004
    Assignee: Micron Technology, Inc.
    Inventors: Stephen L. James, Brad D. Rumsey
  • Publication number: 20040021209
    Abstract: In a semiconductor pressure sensor device comprising a housing (1) having a cavity (3), a semiconductor sensor chip (2) mounted within the cavity, leads (4) for conveying pressure detection signals, and bonding wires (6) electrically connecting the sensor chip and the leads, a sensitive portion (2a) of sensor chip (2), leads (4) and bonding wires (6) are covered with an electrically insulating fluorochemical gel material which has a penetration of 30-60 according to JIS K2220, a Tg of up to −45° C., and a degree of saturation swelling in gasoline at 23° C. of up to 7% by weight. The sensor device is improved in operation reliability and durability life.
    Type: Application
    Filed: July 9, 2003
    Publication date: February 5, 2004
    Inventors: Mikio Shiono, Kenichi Fukuda
  • Patent number: 6680436
    Abstract: A reflow encapsulant is used with substrate and an electronic device. The encapsulant is configured to cure when the assembly is heated so as to reflow solder bumps connecting the substrate and electronic device. The encapsulant includes inorganic filler in an amount of 8% to 20% by weight. The amount of filler provided is sufficiently high to lower the CTE of the encapsulant so as to enhance cured material properties and prevent undue expansion and solder joint damage, but low enough so that the solder joints are not affected by filler particles during reflow.
    Type: Grant
    Filed: March 29, 2001
    Date of Patent: January 20, 2004
    Assignee: Seagate Technology LLC
    Inventors: Antai Xu, Robert Michael Echols, Eng Siong David Yeh, Michael John Peterson
  • Patent number: 6674178
    Abstract: In a semiconductor device, a semiconductor pellet having bump electrodes and a interconnection board having pad electrodes are brought into mutual opposition with a resin containing a filler therebetween, so that the bump electrode and the pad electrodes are superposed. With the filler remaining at the superposed parts between the electrodes, the electrode superposed parts are hot-pressed, and the semiconductor pellet and interconnection board are adhered by the resin.
    Type: Grant
    Filed: June 14, 2000
    Date of Patent: January 6, 2004
    Assignee: NEC Electronics Corporation
    Inventor: Gorou Ikegami
  • Patent number: 6670719
    Abstract: A microelectronic device package and method for manufacture. In one embodiment, the device package can include a microelectronic substrate having first and second device features, a conductive link that includes a conductive material extending between the first and second device features, and an external cover or enclosure disposed around at least a portion of the substrate and the conductive link. The package can be filled with a liquid or a pressurized gas to transfer heat away from the conductive link. In one embodiment, the enclosure can have a composition substantially identical to the composition of the conductive links and the enclosure can be formed simultaneously with formation of the conductive link to reduce the number of process steps required to form the microelectronic device package. A sacrificial material can temporarily support the conductive link during manufacture and can subsequently be removed to suspend at least a portion of the conductive link between two points.
    Type: Grant
    Filed: June 27, 2001
    Date of Patent: December 30, 2003
    Assignee: Micron Technology, Inc.
    Inventors: Jerome M. Eldridge, Paul A. Farrar
  • Patent number: 6664648
    Abstract: A method and an apparatus are described for applying an integrated circuit to a carrier element. In which a curable compensating layer of initially paste-like consistency is coated substantially with full coverage onto a lower contact area of the integrated circuit. Whereupon the integrated circuit is joined together, by the compensating layer, with the carrier element after a relative alignment in order then to produce an electrical connection between the integrated circuit and conductor tracks of the carrier element via electrical lines surmounting the thickness of the compensating layer. Whereupon the compensating layer is cured resulting in an increased volume of the compensating layer.
    Type: Grant
    Filed: March 16, 2001
    Date of Patent: December 16, 2003
    Assignee: Infineon Technologies AG
    Inventors: Johann Winderl, Christian Hauser, Martin Reiss
  • Patent number: 6664637
    Abstract: An electrical structure, and associated method of fabrication, for reducing thermally induced strain in a conductive structure that couples a first substrate to a second substrate. The first substrate may include a chip or a module. The second substrate may include a chip carrier or a circuit card. Thus, the present invention encompasses such coupling as chip to chip carrier, chip to circuit card, and module to circuit card. The conductive structure includes a first conductive body and a second conductive body. The first conductive body is attached to the first substrate and the second conductive body is attached to the second substrate. The first conductive body may include a solder bump, while the second conductive body may include a eutectic alloy, such as a eutectic alloy lead and tin. Alternatively, the second conductive body may include a non-eutectic alloy whose melting point is below the melting point of the first conductive body.
    Type: Grant
    Filed: January 8, 2001
    Date of Patent: December 16, 2003
    Assignee: International Business Machines Corporation
    Inventors: Miguel Angel Jimarez, Cynthia Susan Milkovich, Mark Vincent Pierson
  • Patent number: 6663943
    Abstract: A surface acoustic wave device includes a SAW element that is mounted on a substrate. Grooves are provided in the substrate at the outer periphery of the SAW element, and a flexible resin layer is provided at the inner portion of the grooves so as to cover the SAW element. An outer resin layer that is harder than the flexible resin layer is provided at the exterior of the flexible resin layer. This configuration facilitates reduction in size and profile of the surface acoustic wave device, contributes to reduction in cost, and exhibits high environmental resistance.
    Type: Grant
    Filed: June 19, 2001
    Date of Patent: December 16, 2003
    Assignee: Murata Manufacturing Co., Ltd.
    Inventor: Michio Kadota
  • Patent number: 6660930
    Abstract: A laminated solar cell module comprises a front light transmitting support, a plurality of interconnected solar cells encapsulated by a light-transmitting encapsulant material, and an improved backskin formed of an ionomer/nylon alloy. The improved backskin has a toughness and melting point temperature sufficiently great to avoid any likelihood of it being pierced by any of the components that interconnect the solar cells.
    Type: Grant
    Filed: June 12, 2002
    Date of Patent: December 9, 2003
    Assignee: RWE Schott Solar, Inc.
    Inventor: Ronald C. Gonsiorawski
  • Patent number: 6661104
    Abstract: A microelectronic substrate assembly and method for manufacture. In one embodiment, bond members (such as solder balls) project away from a surface of the microelectronic substrate to define a fill region or cavity between the surface of the microelectronic substrate and the bond members. A fill material is disposed in the fill region, for example, by dipping the microelectronic substrate in reservoir of fill material so that a portion of the fill material remains attached to the microelectronic substrate. An exposed surface of the fill material is engaged with a support member, such as a printed circuit board, and the bond members are attached to corresponding bond pads on the support member. The microelectronic substrate and the fill material can then be encapsulated with an encapsulating material to form a device package.
    Type: Grant
    Filed: September 4, 2001
    Date of Patent: December 9, 2003
    Assignee: Micron Technology, Inc.
    Inventors: Tongbi Jiang, Jason L. Fuller, Alan G. Wood
  • Patent number: 6646355
    Abstract: A new interconnection scheme is disclosed for a tape automated bonding (TAB) package, a flip chip package and an active matrix liquid crystal display (AMLCD) panel, where an electrically conducting adhesive is used to form an electrical interconnection between an active electronic device and its components. The electrically conducting adhesive can be a mixture comprising a polymer resin, a no-clean solder flux, a plurality of electrically conducting particles with an electrically conducting fusible coating which provides a metallurgical bond between the conducting particles as well as to the substrates. The advantages of using the electrically conducting adhesives include reduction in bonding pressure and/or bonding temperature, control of interfacial reactions, promotion of stable metallurgical bonds, enhanced reliability of the joints, and others.
    Type: Grant
    Filed: January 7, 2002
    Date of Patent: November 11, 2003
    Assignee: International Business Machines Corporation
    Inventors: Sung Kwon Kang, Sampath Purushothaman
  • Patent number: 6638847
    Abstract: A method of forming solder bumps on a chip or wafer for flip-chip applications comprises the steps of providing a chip or wafer having a plurality of metal bonds pads which provide electrical connection to the chip or wafer, and applying a solder bump comprising pure tin or a tin alloy selected from tin-copper, tin-silver, tin-bismuth or tin-silver-copper by an electroplating technique, and melting the solder bumps by heating to a temperature above the bump melting point to effect reflow.
    Type: Grant
    Filed: April 19, 2000
    Date of Patent: October 28, 2003
    Assignee: Advanced Interconnect Technology Ltd.
    Inventors: Edwin Wai Ming Cheung, Zaheed Sadrudin Karim
  • Patent number: 6635971
    Abstract: An electronic device, in which terminals of a semiconductor integrated circuit chip and terminals of a circuit substrate are mounted with solder so as to face one another. The electronic device includes a first resin, which is disposed between the circuit substrate and a terminal formation face of the semiconductor integrated circuit chip and a second resin, which is disposed at the outer perimeter of the semiconductor integrated circuit chip or is disposed laterally thereon. The modulus of elasticity of the second resin is smaller than the modulus of elasticity of the first resin, the modulus of elasticity of the second resin is at least 0.5 GPa but not more than 28 GPa at room temperature.
    Type: Grant
    Filed: January 11, 2002
    Date of Patent: October 21, 2003
    Assignee: Hitachi, Ltd.
    Inventors: Toyoki Asada, Yuji Fujita, Hideo Sotokawa, Kazumi Kawamoto, Kunio Matsumoto, Shinya Hamagishi, Mari Matsuyoshi
  • Patent number: 6630727
    Abstract: A modularly expandable semiconductor component includes at least one carrier layer, at least one intermediate layer, at least one coverlayer, at least one semiconductor chip, external contacts and a conductor configuration. The intermediate layer is provided with at least one opening, into which the at least one semiconductor chip is inserted. The carrier layer, the intermediate layer and the coverlayer are connected one above another and form a submodule. If a plurality of submodules are installed above one another, a semiconductor component is provided in which the semiconductor chips are located in several mutually overlying planes. The semiconductor chips can be interconnected. A method for producing a semiconductor component is also provided.
    Type: Grant
    Filed: September 5, 2000
    Date of Patent: October 7, 2003
    Assignee: Infineon Technologies AG
    Inventors: Günter Tutsch, Thomas Münch
  • Publication number: 20030183953
    Abstract: A silicon device which includes a silicon substrate and a bond pad array on the silicon substrate which is configured to be conductively connected to bond wire. The bond pad array consists of a plurality of bond pads which are vertically staggered on the silicon substrate. The vertical staggering allows the bond pads to be packed closer together on the silicon substrate, thereby reducing the horizontal space which is consumed by the bond pads on the silicon substrate, and thereby resulting in a reduction in die size. Preferably, the bond pads are also horizontally staggered on the silicon substrate, thereby allowing the bond pads to be spaced even closer together.
    Type: Application
    Filed: April 2, 2002
    Publication date: October 2, 2003
    Inventor: Jeff Blackwood
  • Publication number: 20030184985
    Abstract: The present invention provides an electronic device manufacturing method and an electronic device which make it possible to reduce the waste of materials and the number of manufacturing steps required. Electronic devices are manufactured via a process including creating a collective substrate, in which a plurality of substrates corresponding to the electronic devices being manufactured are connected in the form of a matrix, mounting electronic parts on the upper surface of the collective substrate, forming a solidified resin layer using a vacuum printing method so that said resin layer covers the upper surface of the collective substrate on which the aforementioned parts have been mounted, or an intermediate layer consisting of an insulating elastic material, and so that said resin layer covers the electronic parts, and separating the collective substrate on which the above-mentioned resin layer has been formed into individual substrates.
    Type: Application
    Filed: June 6, 2003
    Publication date: October 2, 2003
    Applicant: Taiyo Yuden Co., Ltd.
    Inventors: Gosuke Oshima, Masashi Miki
  • Patent number: 6628526
    Abstract: The present invention provides an electronic device manufacturing method and an electronic device which make it possible to reduce the waste of materials and the number of manufacturing steps required. Electronic devices are manufactured via a process including creating a collective substrate, in which a plurality of substrates corresponding to the electronic devices being manufactured are connected in the form of a matrix, mounting electronic parts on the upper surface of the collective substrate, forming a solidified resin layer using a vacuum printing method so that said resin layer covers the upper surface of the collective substrate on which the aforementioned parts have been mounted, or an intermediate layer consisting of an insulating elastic material, and so that said resin layer covers the electronic parts, and separating the collective substrate on which the above-mentioned resin layer has been formed into individual substrates.
    Type: Grant
    Filed: July 12, 2000
    Date of Patent: September 30, 2003
    Assignee: Taiyo Yuden Co., Ltd.
    Inventors: Gosuke Oshima, Masashi Miki
  • Patent number: 6627328
    Abstract: An epoxy resin composition comprising (A) an epoxy resin, (B) a curing accelerator, and (C) an inorganic filler is light transmissive when it satisfies formulae (1) and (2): [{2(nA2+nC2)−(nA+nC)2}/2]½<3.0×10−3  (1) [{2(fA2+fC2)−(fA+fC)2}/2]½<1.0×10−5  (2) wherein nA is the refractive index at T1° C. of the cured unfilled composition, nC is the refractive index at T1° C. of the inorganic filler, fA is a temperature coefficient of the refractive index of the cured unfilled composition, and fC is a temperature coefficient of the refractive index of the inorganic filler. The cured composition has improved heat resistance, humidity resistance and low stress as well as high transparency over a wide temperature range. The composition is suited for the sealing of optical semiconductor devices.
    Type: Grant
    Filed: September 13, 2001
    Date of Patent: September 30, 2003
    Assignee: Shin-Etsu Chemical Co., Ltd.
    Inventors: Tatsuya Kanamaru, Tsuyoshi Honda, Eiichi Asano, Toshio Shiobara
  • Patent number: 6621154
    Abstract: A miniature semiconductor apparatus is outstanding in reflow resistance, temperature cycle property, and PCT resistance corresponding to high density packing, high densification, and speeding up of processing. The semiconductor apparatus has at least one stress cushioning layer on a semiconductor element with an electrode pad formed, having a conductor on the stress cushioning layer, having a conductor for conducting the electrode pad and conductor via a through hole passing through the stress cushioning layer between the electrode pad and the conductor, having an external electrode on the conductor, and having a stress cushioning layer in an area other than the area where the external electrode exists and a conductor protection layer on the conductor, wherein the stress cushioning layer includes crosslinking acrylonitrile-butadiene rubber having an epoxy resin which is solid at 25° C. and a carboxyl group.
    Type: Grant
    Filed: September 28, 2000
    Date of Patent: September 16, 2003
    Assignee: Hitachi, Ltd.
    Inventors: Toshiya Satoh, Masahiko Ogino, Tadanori Segawa, Takao Miwa, Akira Nagai, Akihiro Yaguchi, Ichiro Anjo, Asao Nishimura
  • Patent number: 6621173
    Abstract: A semiconductor device having a semiconductor chip; a semiconductor chip attachment element facing the semiconductor chip, at least one interconnect on the surface of the semiconductor chip attachment element; and at least one member consisting of a metal or metal alloy that electrically connects the semiconductor chip with the interconnects; wherein the semiconductor chip is bonded to the semiconductor chip attachment element by an adhesive and at least a portion of at least one member that electrically connects the semiconductor chip with at least one interconnect is sealed or imbedded with a sealant/filling agent, and the complex modulus of at least one of the adhesive and the sealant/filling agent is not greater than 1×108 Pa at −65° C. and a shear frequency of 10 Hz.
    Type: Grant
    Filed: January 14, 2000
    Date of Patent: September 16, 2003
    Assignee: Dow Corning Toray Silicone Co., Ltd.
    Inventors: Kimio Yamakawa, Minoru Isshiki, Yoshiko Otani, Katsutoshi Mine
  • Patent number: 6621157
    Abstract: For encapsulating an electronic component, in particular a semiconductor chip the component (3) at a distance is fastened onto a flat substrate (2). For this on the substrate there is deposited an elastomer layer (4, 9) which compensates the differing thermal expansion coefficients between the substrate and the component. A buffer material and/or an adhesive in liquid or pasty form is deposited from a dispenser and the component at room temperature is placed onto the buffer material and/or the adhesive. Before the final curing the buffer material and/or the adhesive is firstly subjected to a precuring. Subsequently the component by way of electrical leads is connected to contact locations on the substrate and lastly there is effected an encasing of all remaining hollow spaces including the electrical leads, with a protective mass.
    Type: Grant
    Filed: January 6, 2000
    Date of Patent: September 16, 2003
    Assignee: Alphasem AG
    Inventors: Gustav Wirz, Wolfgang Herbst, Heinz Ritzmann
  • Patent number: 6621153
    Abstract: A coin-shaped IC tag which can be endowed with a predetermined weight is described. The coin-shaped IC tag ensures a normal operation and affords a satisfactory feeling of weightiness as a value medium. The coin-shaped IC tag comprises an IC tag core. The IC tag core comprises an IC packaging base member including a base and an electronic circuit for communicating data and for recording data, the electronic circuit mounted on the base. The IC tag core also comprises a high specific gravity resin layer joined to the IC packaging base member.
    Type: Grant
    Filed: June 20, 2001
    Date of Patent: September 16, 2003
    Assignee: Omron Corporation
    Inventors: Wakahiro Kawai, Yoshiki Iwamae
  • Patent number: 6617698
    Abstract: Reworkable thermally conductive adhesive composition comprising a cured reaction product from a diepoxide wherein the epoxy groups are connected through an acyclic acetal moiety, a cyclic anhydride and a thermally conductive filler are provided and used to bond semiconductive devices to a chip carrier or heat spreader.
    Type: Grant
    Filed: March 9, 2001
    Date of Patent: September 9, 2003
    Assignee: International Business Machines Corporation
    Inventors: Stephen Buchwalter, Michael Anthony Gaynes, Nancy C. LaBianca, Stefano Sergio Oggioni, Son K. Tran
  • Patent number: 6617701
    Abstract: An epoxy resin composition to seal semiconductors constructed of a semiconductor element, a base to support said semiconductor element, and an epoxy resin composition covering only one side opposite to the base, said epoxy resin composition comprising (A) epoxy resin, (B) hardener, and (C) inorganic filler, and giving a cured product which has (a) a flexural modulus of elasticity of 10 to 30 GPa at 23° C. and (b) a coefficient of linear expansion of 4×10−6/K to 10×10−6/K in the temperature range from 23° C. to the glass transition point, with the product of (a) and (b) being smaller than 2×10−4 GPa/K.
    Type: Grant
    Filed: March 13, 2001
    Date of Patent: September 9, 2003
    Assignee: Toray Industries, Inc.
    Inventors: Masayuki Tanaka, Yumiko Tsurumi
  • Patent number: 6614108
    Abstract: An electronic package and a method for packaging an electronic component, particularly a shock-sensitive component such as a yaw rate sensor or an accelerometer mounted to a circuit board. The package includes a case having an opening through which the circuit board is placed within the case, so that a peripheral edge of the circuit board is adjacent but spaced apart from a wall of the case. A thixotropic gel is present in the space between the peripheral edge of the circuit board and the wall of the case, so as to separate and control the mechanical decoupling of the circuit board and case. An optional spacer can be used to space the circuit board from the shelf. Alternatively, the gel may be filled with a polymer particulate material. A potting material preferably fills an upper cavity within the case to encapsulate and secure the circuit board within the case.
    Type: Grant
    Filed: October 23, 2000
    Date of Patent: September 2, 2003
    Assignee: Delphi Technologies, Inc.
    Inventors: Henry M. Sanftleben, Derek S. Ferraro
  • Patent number: 6614111
    Abstract: A semiconductor device able to maintain a bonding state between a bump and an electrode and having high reliability even under thermal stress, wherein a sealing resin is interposed to bond the electrodes and bumps between a wiring board formed with a plurality of electrodes and an IC chip formed with a plurality of bumps, the bumps being formed under the condition that the following formula is satisfied. 100<((&PHgr;A×F)/H)<125 where &PHgr;A represents the top diameter of a bump bonded with an electrode, H the height of a bump projecting from the IC chip and bonded with an electrode, and F the linear thermal expansion coefficient of the sealing resin.
    Type: Grant
    Filed: April 27, 2001
    Date of Patent: September 2, 2003
    Assignee: Sony Corporation
    Inventors: Satoshi Iwatsu, Noriyuki Honda
  • Patent number: 6611065
    Abstract: The present invention is a connection material which enables a flexible circuit board to be connected to a bare IC chip without causing a shoulder touch effect. The connection material contains an insulating adhesive and a flaky or fibrous insulating filler dispersed therein is used for connecting a film-like flexible circuit board and a bare IC chip. The aspect ratio of the flaky or fibrous insulating filler is no less than 20.
    Type: Grant
    Filed: November 14, 2001
    Date of Patent: August 26, 2003
    Assignee: Sony Chemicals Corporation
    Inventors: Motohide Takeichi, Junji Shinozaki
  • Patent number: 6608384
    Abstract: A semiconductor device includes a bonding-structure for electrically and mechanically bonding a solder ball to the electrode pad. The bonding-structure includes flexible arms that are connected to a common supporting layer that allows a relative displacement of the solder ball in relation to the semiconductor chip. The arms extending in one direction are supported by one supporting layer and the arms extending in an opposite direction are supported by another supporting layer.
    Type: Grant
    Filed: August 3, 2001
    Date of Patent: August 19, 2003
    Assignee: Nec Corporation
    Inventor: Seiya Isozaki
  • Patent number: 6600234
    Abstract: A semiconductor device includes a semiconductor substrate having bump electrodes and a sealing film formed thereon, the sealing film having laminated layers. The sealing film interposed between adjacent bump electrodes is prepared by laminating a protective film and each layer of the sealing film on the lower surface of the base film, on the bump electrodes, followed by allowing the bump electrodes to project through the sealing film under pressure and heat. The thickness of the sealing film is smaller than the height of the bump electrode, and thus the bump electrode projects through the sealing film. Particles for lowering the thermal expansion coefficient are dispersed in the sealing film to allow the sealing layers to exhibit a thermal expansion coefficient differing in its thickness direction such that the thermal expansion coefficient in the layer which is close to the semiconductor substrate is close to that of the semiconductor substrate.
    Type: Grant
    Filed: January 31, 2000
    Date of Patent: July 29, 2003
    Assignee: Casio Computer Co., Ltd.
    Inventors: Osamu Kuwabara, Takeshi Wakabayashi, Ichiro Mihara
  • Patent number: 6600217
    Abstract: A mounting substrate and related mounting method for a semiconductor device. The mounting substrate includes a mounting area to which the semiconductor device is to be mounted and fixed by an adhesive, a peripheral channel formed in the mounting substrate so as to surround the mounting area, and radial channels extending radially from the center towards the periphery of the mounting area. An adhesive is applied at least to either the center of the mounting surface of the semiconductor device or the center of the mounting area of the mounting substrate. The semiconductor device is placed on the mounting area and the adhesive flows outwardly along the radial channels, with the adhesive then being cured. The peripheral channel provides control of the amount of adhesive which flows to the outside of the semiconductor device and the mounting area. The adhesive overflow can be adjusted such that adhesive climbs up the sides of the semiconductor device but not reach the upper surface of the device.
    Type: Grant
    Filed: December 8, 2000
    Date of Patent: July 29, 2003
    Assignee: Fujitsu Limited
    Inventors: Masanori Onodera, Shinsuke Nakajyo, Masamitsu Ikumo
  • Patent number: 6597575
    Abstract: An electronic package includes a heat-generating electronic component such as an integrated circuit chip, a thermally conductive member, which may be an integrated heat spreader, and a low modulus thermal interface material in heat conducting relation between the electronic component and the thermally conductive member. Increased thermal performance requirements at the electronic component level are met by the thermal interface material, which includes a polymer matrix and thermally conductive filler, which has a storage shear modulus (G′) at 125° C. of less than about 100 kPa, and which has a gel point, as indicated by a value of G′/G″ of ≧1, where G″ is the loss shear modulus of the thermal interface material. The values for G′ and G″ are measured by a strain-controlled rheometer.
    Type: Grant
    Filed: January 4, 2002
    Date of Patent: July 22, 2003
    Assignee: Intel Corporation
    Inventors: James C. Matayabas, Jr., Paul Koning, Jinlin Wang
  • Patent number: 6590157
    Abstract: A highly moisture-sensitive element and method of making such element includes an encapsulation enclosure encapsulating all of the highly moisture-sensitive electronic devices on a substrate and a sealing material positioned between the substrate and the encapsulation enclosure to form a partial seal (later to be filled) between the substrate and the encapsulation enclosure around each highly moisture-sensitive electronic device or around groups of highly moisture-sensitive electronic devices.
    Type: Grant
    Filed: September 21, 2001
    Date of Patent: July 8, 2003
    Assignee: Eastman Kodak Company
    Inventors: Michael L. Boroson, John Schmittendorf, Peter G. Bessey, Jeffrey P. Serbicki
  • Patent number: 6586831
    Abstract: A vacuum package for integrated circuit devices includes a sealing ring having multiple control spacers of uniform thickness distributed around the sealing ring. The sealing ring is in a designated area on a substrate, material and surrounds one or more integrated circuit devices. The vacuum package also includes a sealing layer on the sealing ring. A vacuum package lid is sealed to the sealing ring by the sealing layer on the sealing ring. The vacuum package lid provides a vacuum cell for the one or more integrated circuit devices.
    Type: Grant
    Filed: August 10, 2001
    Date of Patent: July 1, 2003
    Assignee: Raytheon Company
    Inventors: Roland W. Gooch, Thomas R. Schimert
  • Patent number: 6586827
    Abstract: A wiring board includes a substrate having an opening, and an electronic part placed in the opening, wherein a space left in the opening is filled with an embedding resin having a base color tone selected from black, blue, green, red, orange, yellow, and violet.
    Type: Grant
    Filed: December 27, 2001
    Date of Patent: July 1, 2003
    Assignee: NGK Spark Plug Co., Ltd.
    Inventors: Hiroki Takeuchi, Toshifumi Kojima, Kazushige Obayashi, Hisahito Kashima
  • Patent number: 6583516
    Abstract: A semiconductor device comprising: a semiconductor element having a plurality of electrodes; a passivation film formed on the semiconductor element in a region avoiding at least a part of each of the electrodes; a conductive foil provided at a given spacing from the surface on which the passivation film is formed; an external electrodes formed on the conductive foil; intermediate layer formed between the passivation film and the conductive foil to support the conductive foil; and wires electrically connecting the electrodes to the conductive foil; wherein a depression tapered in a direction from the conductive foil to the passivation film if formed under a part of the conductive foil that includes the connection with the external electrodes.
    Type: Grant
    Filed: November 1, 2001
    Date of Patent: June 24, 2003
    Assignee: Seiko Epson Corporation
    Inventor: Nobuaki Hashimoto
  • Patent number: 6576931
    Abstract: A semiconductor light emitting device ensuring a uniform color tone comprises a semiconductor light emitting element that emits light of a first wavelength upon injection of a current, a fluorescent material portion that contains a fluorescent material excited by light of the first wavelength to emit light of a second wavelength, and a diffuser mixed in an appropriate material around the semiconductor light emitting element.
    Type: Grant
    Filed: July 31, 2001
    Date of Patent: June 10, 2003
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Chisato Furukawa, Masayuki Morishita
  • Patent number: 6573609
    Abstract: A connection component is provided. The connection component includes (1) a first interposer having a first surface to which a microelectronic may be mounted and a second surface opposite from the first surface, (2) a second interposer that is more flexible than the first interposer and that is disposed under the second surface of the rigid interposer, and (3) a plurality of conductive parts that may be positioned in the first and second interposers and that may be exposed at the first surface of the first interposer, a bottom surface of the second interposer, or both the first and bottom surfaces. The electrically conductive parts may include leads. A socket assembly or a microelectronic element such as semiconductor chip may be mounted onto the first surface of the rigid interposer. The connection component may be mounted onto a support substrate.
    Type: Grant
    Filed: January 26, 2001
    Date of Patent: June 3, 2003
    Assignee: Tessera, Inc.
    Inventors: Joseph Fjelstad, John Myers
  • Publication number: 20030090007
    Abstract: A housing assembly forms a package for an electronic device. The housing assembly has the electronic device, an external carrier and a housing frame. A capillary-acting epoxy resin is filled into the assembled housing assembly via a filling-in opening and, on account of its capillary action, closes the interspaces between the semiconductor chip and the housing frame.
    Type: Application
    Filed: September 30, 2002
    Publication date: May 15, 2003
    Inventors: Reinhard Fischbach, Manfred Fries, Manfred Zaeske